TGA2760-SM-T/R GHz Power Amplifier. Product Overview. Key Features. Applications. Functional Block Diagram. Ordering Information

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1 Product Overview Qorvo s is a packaged X-band high power amplifier utilizing Qorvo s production GaAs phemt and GaN processes. The operates from 11.7GHz and typically provides 16W saturated power with power-added efficiency of % and large signal gain db. Third-order intermodulation is better than -dbc at 3dB backed off from Psat. Along with the higher performance, an additional feature is an integrated power detector allowing the user to accurately monitor the output power of the unit. The is packaged in a small air-cavity surface mount package and matched to 5 ohms with integrated DC blocking capacitors on both RF I/O ports simplifying system integration. Lead-free and RoHS compliant Evaluation boards available upon request. Functional Block Diagram Key Features -Lead 8. x. x 2 mm Package Range: 11.7 GHz Power: +42 dbm Psat Gain: 33 db Integrated Power Detector Bias: VD1 = VD2 = +7 V, ID1 + ID2 = ma, VD3 = + V, ID3 = ma Package Dimensions: 8. x. x 2 mm Performance is typical across frequency. Please reference electrical specification table and data plots for more details Applications Point-to-Point Radio Ordering Information Top View Part No. ECCN Description -T/R, Sample 3A1.b.2.b.2 3A1.b.2.b.2 5 pieces on a 7 reel (standard) Waffle Tray with 2 pcs, Eval Board EAR99 Evaluation Board Data Sheet Rev. E, December 6, 16 Subject to change without notice 1 of

2 Absolute Maximum Ratings Parameter Rating Drain Voltage, VD1, VD2 +9 V Drain Voltage, VD3 + V Drain Current, ID1 + ID2 5 ma Drain Current, ID3 ma Power Dissipation, Driver Stages, PDISS 14.8 W Power Dissipation, Final Stage, PDISS.8 W RF Input Power, CW, 5 Ω, T = 25 C +29 dbm GaAs Channel Temperature, TCH 25 C GaN Channel Temperature, TCH 275 C Mounting Temperature ( Seconds) C Storage Temperature to C Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Recommended Operating Conditions Parameter Min Typ Max Units Operating Temp. Range C VD1, VD2 +7 V VD3 + V ID1 + ID2 ma ID3 ma VG12.7 V VG3 2.6 V ID1 + ID2 drive (at +39 dbm Pout) 18 ma ID3 drive (at +39 dbm Pout) 9 ma Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Electrical Specifications Parameter Conditions (1) Min Typ Max Units RF Range 11.7 GHz Small Signal Gain db Input Return Loss, IRL 8 db Output Return Loss, ORL 8 db Output Power at Pin = +12 dbm dbm Power Added Efficiency % Output Third Order Intercept, dbm/tone +52 dbm Gain Temperature Coefficient.5 db / C Power Temperature Coefficient.1 dbm / C Notes: 1. Test conditions unless otherwise noted: VD1 = VD2 = +7 V, ID1 + ID2 = ma, VG1 = VG2 =.7 V, VD3 = + V, ID3 = ma, VG3 = 2.6 V, Temp = +25 C, Z = 5 Ω Data Sheet Rev. E, December 6, 16 Subject to change without notice 2 of

3 Gain (db) Gain (db) Output Power (dbm) Output Power (dbm), Gain (db) Current, Id (ma) Gain (db) Return Loss (db) Gain (db) Return Loss (db) Performance Plots Test conditions unless otherwise noted: VG3 = 2.6 V, Temp = +25 C, Z = 5 Ω VD1 = VD2 = +7 V, ID1 + ID2 = ma, VG1 = VG2 =.7 V, VD3 = + V, ID3 = ma, S-Parameter vs. S-Parameter vs Gain IRL - ORL (GHz) 5 Gain IRL ORL (GHz) Output Power vs Psat P1dB Pout, Gain, Id vs. GHz Id1 + Id2 Id3 Pout Gain Input Power (dbm) Gain vs. vs. Bias (Vd1 and Vd2) Vd3 = V, Id3 = ma, Vg3 = -2.6 V Typical 6V 7mA 6V ma 7V 7mA 7V ma (GHz) Gain vs. vs. Bias (Vd3) Vd1 = Vd2 = 7 V, Id1 + Id2 = ma, Vg12 = -.7 V Typical 25V ma V ma V 5mA V 65mA (GHz) Data Sheet Rev. E, December 6, 16 Subject to change without notice 3 of

4 AM-PM (degrees) Vdiff (V) = Vdet - Vref P1dB (dbm) P1dB (dbm) Psat (dbm) Psat (dbm) Performance Plots Test conditions unless otherwise noted: VG3 = 2.6 V, Temp = +25 C, Z = 5 Ω VD1 = VD2 = +7 V, ID1 + ID2 = ma, VG1 = VG2 =.7 V, VD3 = + V, ID3 = ma, Psat vs. vs. Bias (Vd1 and Vd2) Vd3 = V, Id3 = ma, Vg3 = -2.6 V Typical 6V 7mA 6V ma 7V 7mA 7V ma Psat vs. vs. Bias (Vd3) Vd1 = Vd2 = 7 V, Id1 + Id2 = ma, Vg12 = -.7 V Typical 25V ma V ma V 5mA V 65mA P1dB vs. vs. Bias (Vd1 and Vd2) Vd3 = V, Id3 = ma, Vg3 = -2.6 V Typical 6V 7mA 6V ma 7V 7mA 7V ma P1dB vs. vs. Bias (Vd3) Vd1 = Vd2 = 7 V, Id1 + Id2 = ma, Vg12 = -.7 V Typical 25V ma V ma V 5mA V 65mA AM-PM vs. Pout vs. Power Detector vs. Pout vs. 9.5 GHz GHz.7 GHz 11.7 GHz GHz GHz.7 GHz 11.7 GHz Output Power (dbm) Output Power (dbm) Data Sheet Rev. E, December 6, 16 Subject to change without notice 4 of

5 Output dbm/tone (dbm) Output dbm/tone (dbm) IM3 (dbc) IM5 (dbc) Noise Figure (db) Output TOI (dbm) Performance Plots Test conditions unless otherwise noted: VG3 = 2.6 V, Temp = +25 C, Z = 5 Ω VD1 = VD2 = +7 V, ID1 + ID2 = ma, VG1 = VG2 =.7 V, VD3 = + V, ID3 = ma, Noise Figure vs TOI vs. vs. Pout/Tone Pout/Tone = 31 dbm 25 Pout/Tone = 33 dbm Pout/Tone = dbm (GHz) IM3 vs. Pout/Tone vs GHz -45. GHz GHz GHz Output Power (dbm/tone) IM5 vs. Pout/Tone vs GHz -. GHz GHz GHz Output Power (dbm/tone) TOI vs. vs. Bias (Vd1 and Vd2) Vd3 = V, Id3 = ma, Vg3 = -2.6 V Typical 6V 7mA 6V ma 7V 7mA 7V ma (GHz) TOI vs. vs. Bias (Vd3) Vd1 = Vd2 = 7 V, Id1 + Id2 = ma, Vg12 = -.7 V Typical 25V ma V ma V 5mA V 65mA (GHz) Data Sheet Rev. E, December 6, 16 Subject to change without notice 5 of

6 Vdiff (V) = Vdet - Vref Psat (dbm) P1dB (dbm) Gain (db) Output dbm Pout/Tone (dbm) Performance Plots Test conditions unless otherwise noted: VG3 = 2.6 V, Temp = +25 C, Z = 5 Ω VD1 = VD2 = +7 V, ID1 + ID2 = ma, VG1 = VG2 =.7 V, VD3 = + V, ID3 = ma, Gain vs. vs. Temperature - C +25 C +85 C (GHz) TOI vs. vs. Temperature C +25 C C Psat vs. vs. Temperature C +25 C +85 C P1dB vs. vs. Temperature - C C C Power Detector vs. Pout vs. Temperature 1 - C +25 C +85 C Output Power (dbm) Data Sheet Rev. E, December 6, 16 Subject to change without notice 6 of

7 Median Lifetime, T M (Hours) Thermal and Reliability Information (GaAs Driver Stages) Parameter Test Conditions Value Units Thermal Resistance (θjc) (1) CW 8.14 ºC/W Channel Temperature, TCH Tbaseplate = +85 C, VD Driver = +7 V, ID Driver = ma, 142 C Median Lifetime (TM) PDISS = 7. W 2. x 6 Hrs Thermal Resistance (θjc) (1) CW 8.17 ºC/W Channel Temperature, TCH (Under RF) Tbaseplate = +85 C, VD Driver = +7 V, ID Driver = 18 ma, 143 C POUT = +39 dbm, Median Lifetime (TM) PDISS = 7.1 W 1.8 x 6 Hrs Notes: 1. Thermal resistance measured at back of package. Median Lifetime 1E+13 Median Lifetime vs. Channel Temperature 1E+12 1E+11 1E+ 1E+9 1E+8 1E+7 1E+6 1E+5 1E+4 FET Channel Temperature, T CH ( C) Data Sheet Rev. E, December 6, 16 Subject to change without notice 7 of

8 Median Lifetime (Hours) Thermal and Reliability Information (GaN Final Stage) Parameter Test Conditions Value Units Thermal Resistance (θjc) (1) CW 5.1 ºC/W Channel Temperature, TCH Tbaseplate = +85 C, VD Driver = + V, ID Final = ma, 122 C Median Lifetime (TM) PDISS = 7.3 W 4.8 x Hrs Thermal Resistance (θjc) (1) CW 5.11 ºC/W Channel Temperature, TCH (Under RF) Tbaseplate = +85 C, VD Driver = + V, ID Final = 9 ma, 177 C POUT = +39 dbm, Median Lifetime (TM) PDISS = 18 W 1.1 x 8 Hrs Notes: 1. Thermal resistance measured at back of package. Median Lifetime 1E+18 1E+17 1E+16 1E+ 1E+14 1E+13 1E+12 1E+11 1E+ 1E+9 1E+8 1E+7 1E+6 1E+5 1E+4 Median Lifetime vs. Channel Temperature FET Channel Temperature ( C) Data Sheet Rev. E, December 6, 16 Subject to change without notice 8 of

9 Pin Configuration and Description Top View Pad No. Label Description 1 RF IN RF Input, matched to 5 Ω, AC Coupled. 2, VG12 Gate voltage. Bias network is required; can be biased from either pin, and nonbiased pin can be left open; see Application Circuit on page as an example. 3, 6, 9,, 16, 19 NC No internal connection; can be grounded on PCB. 4, 18 VD1 Drain voltage. Bias network is required; see Application Circuit on page as an example. 5, 17 VD2 Drain voltage. Bias network is required; see Application Circuit on page as an example. 7, VG3 Gate voltage. Bias network is required; can be biased from either pin, and nonbiased pin can be left opened; see Application Circuit on page as an example. 8, 14 VD3 Drain voltage. Bias network is required; see Application Circuit on page as an example. 11 RF OUT RF Output, matched to 5 ohms, AC Coupled. 12 VREF Reference diode output voltage. 13 VDET Detector diode output voltage. Varies with RF output power. 21 GND Backside Paddle. Multiple vias should be employed to minimize inductance and thermal resistance; see Mounting Configuration on page 13 for suggested footprint. Data Sheet Rev. E, December 6, 16 Subject to change without notice 9 of

10 Application Circuit Vg3 Vd3 Vg RF IN 1 11 RF OUT Vg12 Vd3 Vg3 VG12 can be biased from either side, and the non-biased side can be left open. VD1, VD2, VD3, must be biased from both sides. Bias-up Procedure VG12 set to 1.5 V VG3 set to 3.5 V VD1, VD2 set to +7 V VD3 sets to + V Adjust VG12 more positive until quiescent ID is ma. This will be ~ VG =.7 V typical Adjust VG3 more positive until quiescent ID is ma. This will be ~ VG = 2.6 V typical Apply RF signal Bias-down Procedure Turn off RF signal Reduce VG12 to 1.5 V. Ensure ID ~ ma Reduce VG3 to 3.5 V. Ensure ID ~ ma Turn VD1, VD2, VD3 to V Turn VG12, VG3 to V Data Sheet Rev. E, December 6, 16 Subject to change without notice of

11 Application Evaluation Board 1. Board Material is RO3.8 thickness with ½ oz. copper cladding Bill of Material Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo C1 C8 pf Cap, 2, +5 V, 5%, COG various C9 C18 1 µf Cap, 63, +5 V, 5%, X5R various R1 R4 Ω Res, 2, 1/16W, 5%, SMD various U GHz Power Amplifier Qorvo Data Sheet Rev. E, December 6, 16 Subject to change without notice 11 of

12 Package Marking and Dimensions Marking: Part Number Lot Code MXXXXXXX Notes: 1. All dimensions are in millimeters. Angles are in degrees. 2. This package is lead-free/rohs-compliant with an embedded heat spreader, and the plating material on the leads is NiAu. It is compatible with both lead-free (maximum C reflow temperature) and tin-lead (maximum 245 C reflow temperature) soldering processes. Data Sheet Rev. E, December 6, 16 Subject to change without notice 12 of

13 PCB Mounting Pattern RFin RFout Notes: 1. The pad pattern shown has been developed and tested for optimized assembly at Qorvo. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. 2. Ground vias are critical for the proper performance of this device. Vias should have a final plated thru diameter of.24 mm (.6 ). 3. For best thermal performance, vias under the ground paddle should be copper filled. Data Sheet Rev. E, December 6, 16 Subject to change without notice 13 of

14 Tape and Reel Information Feature Measure Symbol Size (in) Size (mm) Length A Cavity Width B.9.4 Depth K Pitch P Cavity to Perforation - Length Direction P Centerline Distance Cavity to Perforation - Width Direction F.9.4 Cover Tape Width C Carrier Tape Width W Data Sheet Rev. E, December 6, 16 Subject to change without notice 14 of

15 Handling Precautions Parameter Rating Standard ESD Human Body Model (HBM) Class 1A ESDA / JEDEC JESD22-A114 ESD Charged Device Model (CDM) Class C2a JEDEC JS-2-14 MSL Moisture Sensitivity Level Level 3 IPC/JEDEC J-STD- Caution! ESD-Sensitive Device Solderability Compatible with both lead-free ( C max. reflow temp.) and tin/lead (245 C max. reflow temp.) soldering processes. Solder profiles available upon request. Contact plating: NiPdAu RoHS Compliance This part is compliant with 11/65/EU RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment) as amended by Directive /863/EU. This product also has the following attributes: Lead Free Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (CH12Br2) Free PFOS Free SVHC Free Pb Contact Information Tape For the latest and specifications, Reel Information additional product information, Tape Length worldwide and sales and Label distribution Placement locations: Web: Tel: Notes: customer.support@qorvo.com 1. Empty part cavities at the trailing and leading ends are sealed with cover tape. See EIA A. 2. Labels are placed on the flange opposite the sprockets in the carrier tape. Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright 16 Qorvo, Inc. Qorvo is a registered trademark of Qorvo, Inc. Data Sheet Rev. E, December 6, 16 Subject to change without notice of