TQP MHz Power Amplifier. General Description. Product Features. Functional Block Diagram. Ordering Information

Transcription

1 General Description The is a high-efficiency two-stage power amplifier in a low-cost surface-mount package. The amplifier is able to achieve 31% power added efficiency at +27 dbm output power while operating with a low 84 ma idle current. The amplifier is designed to ensure that all oddorder IMD products are below 17 dbm at all output power levels below +24 dbm/tone. The integrates two high performance amplifier stages onto a module to allow for a compact system design and requires very few external components for operation. The amplifier is bias adjustable allowing the amplifier s power consumption to be optimized. The is available in a lead-free/rohs-compliant 13-pin 3.5 x 4.5mm surface mount package and is pin-compatible to the higher frequency band version in the family with the TQP9108 ( GHz). Functional Block Diagram 3.5 x 4.5 mm Leadless SMT Package Product Features MHz Frequency Range 35.5 db gain +46 dbm Output IP3 at Pout = +24 dbm/tone 31% PAE at +27 dbm Pout Internally Matched Integrated Inter-Stage Bias Adjustable Low idle current RFin V PD1 V PD2 RFout Applications Wireless Infrastructure AMP1 AMP2 Repeaters, Boosters, DAS Pin 1 Reference Mark Package Topside Exposed Backside Pad GND High Power Amplifiers Small cell BTS V BIAS V CC Top View Ordering Information Part No. -PCB Description MHz Power Amplifier Evaluation Board Data Sheet November 29, 2016 Subject to change without notice - 1 of 9 -

2 Absolute Maximum Ratings Parameter Rating Storage Temperature 55 to +150 C RF Input Power, CW, 50 Ω, T=25 C Supply Voltage (VCC) +7 dbm +6 V Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Recommended Operating Conditions Parameter Min Typ Max Units VCC V VBIAS +3.9 VCC V VPD1, VPD VCC V TCASE C Tj for >10 6 hours MTTF +190 C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Electrical Specifications Parameter Conditions (1) Min Typ Max Units Operational Frequency Range MHz Test Frequency 849 MHz Gain db Noise Figure 5 db Output P1dB 30.5 dbm Output IP3 Pout = +23 dbm/tone, Δf = 600 khz dbm IMD3, IMD5, IMD7 All power levels 23 dbm / tone 17 dbm Current, ICC Pout = +27 dbm 370 ma Power Added Efficiency Pout = +27 dbm 31 % Idle Current No RF Input Power 84 ma VSWR Survivability Pout = P1dB Signal: CW 10:1 All Phases VSWR Survivability Pout = +28 dbm Signal: 20 MHz LTE 1C, PAR = 9.5 db 6:1 All Phases Thermal Resistance, θjc Junction to case 30.1 C/W Notes: 1. Test conditions unless otherwise noted: V CC = +4.3 V, V PD1 = V PD2 = +4.0 V, Temp = +25 C, 50 Ω system. Data Sheet November 29, 2016 Subject to change without notice - 2 of 9 -

3 Application Circuit Schematic and Layout -PCB V PD C uf R1 0 R2 0 J1 RF Input J2 RF Output AMP1 AMP R3 300 C5 100 pf C6 10 uf V CC J3 C7 J6 R1 R2 J1 U1 J2 R3 C5 J4 C6 J5 R4 Bill of Material -PCB Reference Des. Value Description Manuf. Part Number n/a Nelco FR4, PCB APP BOARD Qorvo PC U1 2-Stage Power Amplifier Qorvo C5 100 pf CAP, 0603, 5%, 50V, NPO various C6 10 uf CAP, 6032, 20%, 50V, Tantalum various C uf CAP, 0603, 50V, X7R, 5% various R1, R2, R4 0 Ω RES, 0603, 5%, 1/16W, Chip various R3 300 Ω RES, 0603, 5%, 1/16W, Chip various Data Sheet November 29, 2016 Subject to change without notice - 3 of 9 -

4 OIP3 (dbm) IM3 and IM5 (dbm) IM3 (dbm) IM5 (dbm) IM3 and IM5 (dbm) IM3 and IM5 (dbm) IM3 and IM5 (dbm) Gain (db) PAE (%) IM3 (dbm) Typical Performance -PCB Parameter Conditions (1) Typical Value Units Frequency MHz Gain db IM3 Pout= +27 dbm, f= 600 KHz dbm IM5 Pout= +27 dbm, f= 600 KHz dbm Quiescent Collector Current, ICQ VPD = +4 V 84 ma Notes: 1. Test conditions unless otherwise noted: V CC = +4.3 V, V PD1= V PD2 = +4.0V, Temp.=+25 C Performance Plots -PCB Test conditions unless otherwise noted: V CC = +4.3 V, V PD1= V PD2 = +4.0V, Temp.=+25 C Gain vs. Frequency Frequency (MHz) IM3 and IM5 vs Total Pout (760 MHz) IM3 Lower IM3 Upper IM5 Lower IM5 Upper -47 IM3 and IM5 vs Total Pout (920 MHz) IM3 Lower IM3 Upper IM5 Lower PAE vs. Pout freq = 850 MHz IM3 and IM5 vs Total Pout (820 MHz) IM3 Lower IM3 Upper IM5 Lower -47 IM3 vs Total Pout over Temperature (850 MHz) 25degC 45degC 55degC 65degC 55 OIP3 vs Total Pout IM3 vs Total Pout (699 MHz) IM3 Lower IM3 Upper -47 IM3 and IM5 vs Total Pout (850 MHz) IM3 Lower IM3 Upper IM5 Lower -47 IM5 vs Total Pout over Temperature (850 MHz) 25degC 45degC 55degC 65degC MHz 760 MHz 820 MHz 850 MHz 920 MHz 30 Data Sheet November 29, 2016 Subject to change without notice - 4 of 9 -

5 Icc (ma) ACLR (dbc) Gain (db) P1dB (dbm) OIP3 (dbm) Typical Performance VCC = +5.0 V Parameter Conditions (1) Typical Value Units Frequency MHz Gain db Input Return Loss db Output P1dB dbm Output IP3 Pout= +24 dbm, f= 1 MHz dbm Quiescent Collector Current, ICQ VPD = +4.3 V 108 ma Notes: 1. Test conditions unless otherwise noted: V CC = +5.0 V, V PD1= V PD2 = +4.3V, Temp.=+25 C Performance Plots VCC = +5.0 V Test conditions unless otherwise noted: V CC = +5.0 V, V PD1= V PD2 = +4.3V, Temp.=+25 C Gain vs. Frequency P1dB vs Frequency MHz 840 MHz 880 MHz 940 MHz OIP3 vs. Pout/tone Frequency (MHz) Icc vs Pout Frequency (MHz) Pout/Tone (dbm) ACLR W-CDMA 3GPP Test Model 1+64 DPCH PAR = % Probability 3.84 MHz BW Freq = 840 MHz MHz 840 MHz 880 MHz 940 MHz Data Sheet November 29, 2016 Subject to change without notice - 5 of 9 -

6 Pin Configuration and Description RFin V PD1 V PD2 RFout AMP1 AMP2 Pin 1 Reference Mark Package Topside Exposed Backside Pad GND V BIAS V CC Top View Pad No. Label Description 1 VBIAS Provides reference voltage for internal active biasing circuit 2 VCC DC voltage supply connection 3, 4, 5, 6, 8, 9, 10 No internal connection. Provide grounded land pads for PCB mounting integrity. 7 RF out RF output pin. The DC is internally blocked at this pin. 11 VPD1 Power down for Amp 1. This voltage adjusts for the current draw in Amp VPD2 Power down for Amp 2. This voltage adjusts for the current draw in Amp RF in RF input pin. The DC is internally blocked at this pin. Backside Pad GND RF/DC ground. Use recommended via pattern to minimize inductance and thermal resistance; see PCB Mounting Pattern for suggested footprint. Data Sheet November 29, 2016 Subject to change without notice - 6 of 9 -

7 Package Marking and Dimensions Marking: Part Number Date YYWW Lot Code - AaXXXX 2x 0.10 C Pin #1 Locator 3.50±0.1 A B 0.10 C C 0.92± YYWW AaXXXX ± x 0.10 C 1.75 Top View Side View (1X) 0.770x X 0.340y 0.10 C A B 4.500± (10X) 0.270x X 0.340y 0.10 C A B PIN (1X) 1.270x X 0.340y 0.10 C A B (1X) shape 0.10 C A B ± Bottom View Notes: 1. All dimensions are in millimeters. Angles are in degrees. 2. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP Contact plating: Au over Ni Data Sheet November 29, 2016 Subject to change without notice - 7 of 9 -

8 PCB Mounting Pattern Recommend PCB land-pad pattern metallization (Top View) Recommended PCB solder mask opening (Top View) Notes: 1. A heat sink underneath the area of the PCB for the mounted device is strictly required for proper thermal operation. Damage to the device can occur without the use of one. 2. Ground / thermal vias are critical for the proper performance of this device. Vias should use a.35mm (#80 /.0135 ) diameter drill and have a final plated thru diameter of.25 mm (.010 ). 3. Add as much copper as possible to inner and outer layers near the part to ensure optimal thermal performance. Data Sheet November 29, 2016 Subject to change without notice - 8 of 9 -

9 Handling Precautions Parameter Rating Standard ESD Human Body Model (HBM) Class 1C ESDA / JEDEC JS ESD Charged Device Model (CDM) Class C3 JEDEC JESD22-C101F MSL Moisture Sensitivity Level Level 3 IPC/JEDEC J-STD-020 Caution! ESD-Sensitive Device Solderability Compatible with both lead-free (260 C max. reflow temp.) and tin/lead (245 C max. reflow temp.) soldering processes. Solder profiles available upon request. Contact plating: Electrolytic plated Au over Ni RoHS Compliance This part is compliant with EU 2002/95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment). This product also has the following attributes: Lead Free Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (C15H12Br402) Free PFOS Free SVHC Free Qorvo Green Pb Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations: Tel: Web: customer.support@qorvo.com For technical questions and application information: sjcapplications.engineering@qorvo.com Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright 2016 Qorvo, Inc. Qorvo is a registered trademark of Qorvo, Inc. Data Sheet November 29, 2016 Subject to change without notice - 9 of 9 -

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