TQP7M W High Linearity Amplifier. General Description. Product Features. Applications. Functional Block Diagram. Ordering Information

Transcription

1 General Description The is a high linearity driver amplifier in a lowcost, RoHS compliant, surface mount package. This InGaP/GaAs HBT delivers high performance across a broad range of frequencies with +44 dbm OIP3 and dbm P1dB while only consuming 135 ma quiescent current. All devices are 1% and DC tested. The incorporates on-chip features that differentiate it from other products in the market. The amplifier integrates an on-chip DC over-voltage and over-drive protection. This protects the amplifier from electrical DC voltage surges and high input input power levels that may occur in a system. On-chip ESD protection allows the amplifier to have a very robust Class 1C HBM ESD rating. The is targeted for use as a driver amplifier in wireless infrastructure where high linearity, medium power, and high efficiency are required. The device an excellent candidate for transceiver line cards in current and next generation multi-carrier 3G / 4G base stations. Functional Block Diagram Product Features 3 Pin SOT-89 Package 4 4 MHz dbm P1dB +44 dbm Output IP db Gain at 214 MHz +5 V Single Supply, 135 ma Current Internal Overdrive Protection Internal DC Overvoltage Protection On-Chip ESD Protection SOT-89 Package Applications Repeaters Mobile Infrastructure CDMA / WCDMA / LTE General Purpose Wireless Backside Paddle - GND IN GND OUT / V CC Top View Ordering Information Part No. Description.5 W High Linearity Amplifier -PCB MHz Evaluation Board -PCB GHz Evaluation Board -PCB GHz Evaluation Board Standard T/R size = 1 pieces on a 7 reel Datasheet December 26, 217 Subject to change without notice 1 of 26

2 Absolute Maximum Ratings Parameter Rating Storage Temperature -65 to 15 C Input Power, CW, 5Ω, T=25 C Device Voltage (VCC) +27 dbm +8 V Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Recommended Operating Conditions Parameter Min Typ Max Units Device Voltage (VCC) V TCASE C Tj for >1 6 hours MTTF +17 C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Electrical Specifications Parameter Conditions (1) Min Typ Max Units Operational Frequency Range 4 4 MHz Test Frequency 214 MHz Gain db Input Return Loss 12 db Output Return Loss 1 db Output P1dB dbm Output IP3 Pout = +8 dbm/tone, f = 1 MHz dbm WCDMA Channel Power 5 dbc ACLR, Note dbm Noise Figure 3.9 db Quiescent Current, ICQ ma Thermal Resistance, θjc Junction to case 5 C/W 1. Test conditions unless otherwise noted: VCC = +5 V, Temp. = +25 C, matched 214 MHz reference circuit 2. ACLR test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 1.2 db at.1% Probability Performance Summary Table Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm Output IP dbm 1. Test conditions unless otherwise noted: V CC = +5 V, Temp. = +25 C, matched reference circuit 2. Reference designs for the various frequencies are either included on this datasheet or may be obtained by contacting appsupport@qorvo.com Datasheet December 26, 217 Subject to change without notice 2 of 26

3 Gain (db) Device Characterization Data Input Smith Chart Output Smith Chart Gain and Maximum Stable Gain Gain (Max).8 4 GHz GHz 2.1 GHz Gain (S21) GHz Frequency (GHz) Note: The gain for the unmatched device in a 5 ohm system is shown as the black trace labeled "Gain (S21)". In a circuit tuned for a particular frequency, it is expected that actual gain will be higher, up to the maximum stable gain. The maximum stable gain is shown as the red trace [Gmax]. The impedance Smith chart plots are shown from.1 to 4 GHz. S-Parameters Freq (MHz) S11 (db) S11 (ang) S21 (db) S21 (ang) S12 (db) S12 (ang) S22 (db) S22 (ang) Test Conditions: V CC = +5 V, I CQ = 135 ma, Temp. = +25 C, unmatched 5 Ohm system, reference plane at device leads Datasheet December 26, 217 Subject to change without notice 3 of 26

4 MHz Reference Design J4 J3 J3 Vcc J4 GND 1 uf L2 L3 J1 Input 1 pf L2 1.5 nh ,4 3 1 pf 82 nh 85 L3 4.7 nh 1 pf J2 Output 12 pf 3.9 pf 1. See Evaluation Board PCB Information for material and stack up. 2. The recommended component values are dependent upon the frequency of operation. 3. All components are of 63 size unless stated on the schematic. 4. Critical component placement locations: Distance from Pin Pad 1 (left edge) to (right edge): 2 mils Distance from Pin Pad 1 (left edge) to L2 (right edge): 9 mils Distance from Pin Pad 1 (left edge) to (right edge): 235 mils Distance from Pin Pad 3 (right edge) to L3 (left edge): 12 mils Distance from Pin Pad 3 (right edge) to (left edge): 255 mils Bill of Material MHz Reference Design Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a ½ W High Linearity Amplifier Qorvo,, 1 pf CAP, 63, +/%. 1V NPO/COG various 12 pf CAP, 63, +/-2%. 5V. NPO/COG various 3.9 pf CAP, 63, +/-.1PF. 1V. NPO/COG various 1. uf CAP, 63, 1%, X5R, 1V various 82 nh IND, 85, 5%, Ceramic Coilcraft 85CS-82XJL L2 1.5 nh IND, 63 various L3 4.7 nh IND, 63 various 2.7 Ω Resistor, Chip, 63, 5%, 1/16W various Typical Performance MHz Reference Design Test conditions unless otherwise noted: V CC=+5 V, I CQ=137 ma (typ.), Temp.=+25 C Parameter Conditions Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm Output IP3 Pout= +15 dbm/tone, f= 1 MHz dbm LTE Chan. Power (1) 5 dbc ACLR dbm 1. ACLR test set-up: 1 CH, 2 MHz BW, LTE E-TM1.1, 9.5 db PAR at.1% Probability Datasheet December 26, 217 Subject to change without notice 4 of 26

5 OIP3 (dbm) ACLR (dbc) S22 (db) P1dB (dbm) Gain (db) S11 (db) Performance Plots MHz Reference Design Test conditions unless otherwise noted: VCC=+5V, ICQ=137 ma (typ.) 24 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency 29 P1dB vs. Frequency OIP3 vs. Pout/tone ACLR vs. Output Power 652 MHz 635 MHz 617 MHz MHz 635 MHz 617 MHz Pout/Tone (dbm) 5 LTE 1CH 2Mz, Adj ch IBW 18.2MHz, PAR 9.5dB no clipping Pout (dbm) Datasheet December 26, 217 Subject to change without notice 5 of 26

6 MHz Reference Design J4 J3 J3 Vcc J4 GND 1. uf L2 J1 Input 1 pf ,4 3 1 pf nh L2 4.7 nh 1 pf J2 Output 12 pf 4.7 pf 5. See Evaluation Board PCB Information for material and stack up. 6. The recommended component values are dependent upon the frequency of operation. 7. All components are of 63 size unless stated on the schematic. 8. Critical component placement locations: Distance from Pin Pad 1 (left edge) to (right edge): mils Distance from Pin Pad 1 (left edge) to (right edge): 6 mils Distance from Pin Pad 1 (left edge) to (right edge): 23 mils Distance from Pin Pad 3 (right edge) to L2 (left edge): mils Bill of Material MHz Reference Design Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a ½ W High Linearity Amplifier Qorvo,, 1 pf CAP, 63, +/%. 1V NPO/COG various 12 pf CAP, 63, +/-2%. 5V. NPO/COG various 4.7 pf CAP, 63, +/-.1PF. 1V. NPO/COG various 1. uf CAP, 63, 1%, X5R, 1V various 33 nh IND, 85, 5%, Ceramic Coilcraft 85CS-33XJL L2 4.7 nh IND, 63, +/-.3. >56MHZ Toko L68-FSL4N7S 3. Ω Resistor, Chip, 63, 5%, 1/16W various Typical Performance MHz Reference Design Test conditions unless otherwise noted: V CC=+5 V, I CQ=137 ma (typ.), Temp.=+25 C Parameter Conditions Typical Value Units Frequency MHz Gain db Input Return Loss 8 9 db Output Return Loss 1 8 db Output P1dB dbm Output IP3 Pout= +18 dbm/tone, f= 1 MHz dbm Datasheet December 26, 217 Subject to change without notice 6 of 26

7 S22 (db) OIP3 (dbm) Gain (db) S11 (db) Performance Plots MHz Reference Design Test conditions unless otherwise noted: VCC=+5V, ICQ=137 ma (typ.) 22 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency 5 OIP3 vs. Pout/tone MHz 746 MHz Pout/Tone (dbm) Datasheet December 26, 217 Subject to change without notice 7 of 26

8 MHz Evaluation Board ( PCB9) J4 J3 J3 Vcc J4 GND 1 uf L2 J1 Input 1 pf ,4 3 1 pf 33 nh 85 L2 3.3 nh 1 pf J2 Output 8.2 pf 3.3 pf 1. See Evaluation Board PCB Information for material and stack up. 2. Components shown on the silkscreen but not on the schematic are not used. 3. The recommended component values are dependent upon the frequency of operation. 4. All components are of 63 size unless stated on the schematic. 5. Critical component placement locations: Distance from Pin 1 (left edge) to (right edge): 9 mils (4.3 deg. at 92 MHz) Distance from (left edge) to (right edge): 7 mils (3.3 deg. at 92 MHz) Distance from Pin 3 (right edge) to L2 (left edge): 12 mils (5.7 deg. at 92 MHz) Distance from Pin 3 (right edge) to (left edge): 37 mils (17.6 deg. at 92 MHz) Bill of Material PCB9 Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a Amplifier, SOT-89 pkg. Qorvo 1.8 Ω Resistor, Chip, 63, 5%, 1/16W various L2 3.3 nh Inductor, 63, +/-.3 nh Toko L68-FSL3N3S 33 nh Inductor, 85, 5%, Coilcraft CS Series Coilcraft 85CS-33XJLB 8.2 pf Cap., Chip, 63, +/-.1pF. 2V. AVX 632U8R2BAT2A 3.3 pf NPO/COG Cap., Chip, 63, +/-.1pF. 2V. AVX 632U3R3BAT2A,, 1 pf NPO/COG Cap., Chip, 5%, 5V, NPO/COG various 1. uf Cap., Chip, 1%, 1V, X5R various Typical Performance PCB9 Test conditions unless otherwise noted: VCC=+5V, ICQ=137 ma (typ.), Temp.=+25 C Parameter Conditions Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm OIP3 Pout= +19 dbm/tone, Δf=1 MHz dbm WCDMA Channel Power (1) 5 dbc ACLR dbm Noise Figure db 1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 1.2 db at.1% Probability Datasheet December 26, 217 Subject to change without notice 8 of 26

9 Icc (ma) ACLR (dbc) OIP3 (dbm) Pout (dbm) ACLR (dbc) OIP3 (dbm) P1dB (dbm) Gain (db) S11 (db) S22 (db) Performance Plots PCB9 Test conditions unless otherwise noted: VCC=+5V, ICQ=137 ma (typ.) 24 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency C -1 4 C -1 4 C Freq (MHz) Freq (MHz) Freq (MHz) ACLR Vs. Output Power W-CDMA 3GPP Test Model 1+64 DPCH PAR = 1.2 Probability 3.84 MHz BW 4 C Freq.=92 MHz Freq.=92 MHz 1 MHz Tone Spacing OIP3 Vs. Pout/Tone 4 C P1dB vs. Frequency 4 C Pout (dbm) Pout/Tone (dbm) ACLR Vs. Output Power W-CDMA 3GPP Test Model 1+64 DPCH PAR = 1.2 Probability 3.84 MHz BW 96 MHz 92 MHz 869 MHz MHz Tone Spacing OIP3 Vs. Pout/Tone 96 MHz 92 MHz 869 MHz Output Power vs. Input Power Freq.= 92 MHz 4 C Pout (dbm) Pout/Tone (dbm) Pin (dbm) Frequency = 92 MHz Icc vs. Output Power C Pout (dbm) Datasheet December 26, 217 Subject to change without notice 9 of 26

10 7 1 MHz Reference Design J4 J3 J3 Vcc 1. uf.1 uf J4 GND L2 C7 L3 C8 J1 Input 1 pf L2 5.6 nh C ,4 3 1 pf 33 nh 85 L3 2.7 nh 1 pf C8 J2 Output 4.7 pf 12. pf 3.3 pf 1. The recommended component values are dependent upon the frequency of operation. 2. All components are of 63 size unless stated on the schematic. 3. Entire Bias network values are critical of linearity performance. 4. Critical component placement locations: Distance from Pin 1 (left edge) to (right edge): 1 mils (.5 deg at 92 MHz) Distance from (left edge) to C7 (right edge): 1 mils (.5 deg at 92 MHz) Distance from C7 (left edge) to L2 (right edge): 1 mils (.5 deg at 92 MHz) Distance from L2 (left edge) to (right edge): 2 mils (1. deg at 92 MHz) Distance from Pin 3 (right edge) to L3 (left edge): 29 mils (13.8 deg at 92 MHz) Distance from L3 (right edge) to C8 (left edge): 2 mils (1. deg at 92 MHz) Bill of Material 7 1 MHz Reference Design Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a ½ W High Linearity Amplifier Qorvo,, 1 pf 63, 5%, 5 V, NPO/COG various.1 μf 63, 1%, 5 V, X7R various 1. μf 63. 1%, 1 V, X5R Various LL-168-FSN2S 33 nh 85, 5%, cer core,85 Coilcraft Coilcraft 85CS-33XJL L2 5.6 nh 63, ±.3 nh, multilayer, Toko Toko L68-FSL5N6S L3 2.7 nh 63, ±.3 nh, multilayer, Toko Toko L68-FSL2N7S 4.7 pf 63, ±.1 pf, 2 V, NPO/COG, AVX U Series AVX 632U4R7BAT2A C7 12 pf 63, 2%, 5 V, NPO/COG Various C8 3.3 pf 63, ±.1 pf, 2 V, NPO/COG, AVX U Series AVX 632U3R3BAT2A Datasheet December 26, 217 Subject to change without notice 1 of 26

11 OIP3 (dbm) P1dB (dbm) Gain (db) Return Loss (db) Typical Performance 7 1 MHz Reference Design Test conditions unless otherwise noted: V CC = +5 V, I CQ=135 ma, Temp = +25 C, 5 Ω system Parameter Conditions Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm Output IP3 Pout= +16 dbm / tone, f= 1 MHz dbm Performance Plots 7 1 MHz Reference Design Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.), Temp.=+25 C 24 Gain vs. Frequency Return Loss vs. Frequency Input Return Loss Output Return Loss OIP3 vs. Pout/tone 3 P1dB vs. Frequency MHz 85 MHz 1 MHz Pout/Tone (dbm) Datasheet December 26, 217 Subject to change without notice 11 of 26

12 18 22 MHz 1 Watt Reference Design J4 J3 J3 +5V 1. uf J4 GND 22 pf L2 J1 Input L2 2.2 nh 1.5 pf , nh (85) 22 pf J2 Output 1.5 pf 1.8 pf 1. See Evaluation Board PCB Information for material and stack up. 2. Components shown on the silkscreen but not on the schematic are not used. 3. Ω resistors (R2) may be replaced with copper trace in the target application layout. 4. The recommended component values are dependent upon the frequency of operation. 5. All components are of 63 size unless stated on the schematic. 6. Critical component placement locations: Distance from Pin 1 (left edge) to (right edge): 25 mils Distance from Pin 1 (left edge) to (right edge): 145 mils Distance from Pin 1 (left edge) to (right edge): 9 mils Distance from Pin 3 (right edge) to (left edge): 145 mils Bill of Material MHz 1 Watt Reference Design Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a ½ W High Linearity Amplifier Qorvo, 22 pf CAP, 63, +/-1%. 2V NPO/COG various, 1.5 pf CAP, 63, +/-.1pF. 2V. NPO/COG various L2 2.2 nh Ind, chip, 63, +/-.3nH >6MHz Toko LL-168-FSN2S 1. uf CAP, 63, 1%, X5R, 1V various 18 nh IND, 85, 5%, Ceramic Coilcraft 85CS-18XJL 1.8pF CAP, 63, +/-.1pF. 2V. NPO/COG various 2.7 Ω RES, 63, 5% various Typical Performance MHz 1 Watt Reference Design Test conditions unless otherwise noted: VCC =+5V, ICQ=137 ma (typ.), Temp= Parameter Conditions Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm Output IP3 Pout= +15 dbm/tone, f= 1 MHz dbm Datasheet December 26, 217 Subject to change without notice 12 of 26

13 S22 (db) OIP3 (dbm) Gain (db) S11 (db) Performance Plots MHz 1 Watt Reference Design Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.), Temp.=+25 C 2 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency 45 OIP3 vs. Pout/tone MHz 25 MHz 19 MHz 18 MHz Pout/Tone (dbm) Datasheet December 26, 217 Subject to change without notice 13 of 26

14 MHz Evaluation Board ( PCB214) J4 J3 J3 Vcc 1. uf J4 GND 22 pf 18 nh J1 Input 39 pf 1.5 pf 1 2, pf J2 Output 1.8 pf.8 pf 1. See Evaluation Board PCB Information for material and stack up. 2. Components shown on the silkscreen but not on the schematic are not used. 3. The recommended component values are dependent upon the frequency of operation. 4. All components are of 63 size unless stated on the schematic. 5. Critical component placement locations: Distance from Pin 1 (left edge) to (right edge): 35 mils (3.9 deg. at 214 MHz) Distance from Pin 1 (left edge) to (right edge): 9 mils (9.9 deg. at 214 MHz) Distance from Pin 3 (right edge) to (left edge): 21 mils (23.2 deg. at 214 MHz) Bill of Material PCB214 Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a Amplifier, SOT-89 pkg. Qorvo 39 pf Cap., Chip, 63, +/-1%. 2V NPO/COG various 18 nh Inductor, 85, Coilcraft CS Series Coilcraft 85CS-18XJLB 1.5 pf Cap., Chip, 63, +/-.1pF. 2V. NPO/COG various 632R5BAT2A 3.3 pf Cap., Chip, 63, +/-.1pF. 2V. NPO/COG various 632U3R3BAT2A 22 pf Cap., Chip, 5%, 5V, NPO/COG various 1. uf Cap., Chip, 1%, 1V, X5R various 1.8 pf Cap., Chip, 63, +/-.1pF. 2V. NPO/COG various 632R8BAT2A.8 pf Cap., Chip, 63, +/-.5pF, 5V various 632UR8BAT2A Typical Performance PCB214 Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.), Temp=+25 C Parameter Conditions Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm OIP3 Pout= +9 dbm/tone, Δf=1 MHz dbm WCDMA Channel Power (1) 5 dbc ACLR dbm Noise Figure db 1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 1.2 db at.1% Prob Datasheet December 26, 217 Subject to change without notice 14 of 26

15 ACLR (dbc) Icc (ma) ACLR (dbc) ACLR (dbc) OIP3 (dbm) Pout (dbm) ACLR (dbc) OIP3 (dbm) P1dB (dbm) Gain (db) S11 (db) S22 (db) Performance Plots PCB214 Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.) 2 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency C 4 C Freq (MHz) C 4 C Freq (MHz) C 4 C Freq (MHz) ACLR Vs. Output Power W-CDMA 3GPP Test Model 1+64 DPCH PAR = 1.2 Probability 3.84 MHz BW Freq.= 214 MHz 4 C OIP3 Vs. Pout/Tone Freq.=214 MHz 1 MHz Tone Spacing +15 C 4 C P1dB vs. Frequency +15 C 4 C Pout (dbm) Pout/Tone (dbm) ACLR Vs. Output Power W-CDMA 3GPP Test Model 1+64 DPCH PAR = 1.2 Probability 3.84 MHz BW 217 MHz 214 MHz 211 MHz OIP3 Vs. Pout/Tone 1 MHz Tone Spacing 217 MHz 214 MHz 211 MHz Output Power vs. Input Power Freq.=214 MHz +15 C 4 C Pout (dbm) Pout/Tone (dbm) Pin (dbm) ACLR vs Output Power LTE 1CH 2MHz, Adj ch IBW 18.2MHz, PAR 9.5dB no clipping Frequency = 214 MHz Icc vs. Output Power ACLR vs Output Power LTE 1CH 2MHz, Adj ch IBW 18.2MHz, PAR 9.5dB no clipping Freq = 214 MHz MHz 214 MHz 211 MHz C 4 C C 4 C Pout (dbm) Pout (dbm) Pout (dbm) Datasheet December 26, 217 Subject to change without notice 15 of 26

16 23 27 MHz Reference Design J3 +5V J4 J3 1. uf J4 GND R2 J1 Input 1.8 pf , nh (85) 22 pf 22 pf J2 Output 1.5 pf.9 pf 1. See Evaluation Board PCB Information for material and stack up. 2. Components shown on the silkscreen but not on the schematic are not used. 3. Ω resistors (R2) may be replaced with copper trace in the target application layout. 4. The recommended component values are dependent upon the frequency of operation. 5. All components are of 63 size unless stated on the schematic. 6. Critical component placement locations: Distance from Pin 1 (left edge) to (right edge): 1 mils Distance from Pin 1 (left edge) to (right edge): 8 mils Distance from Pin 1 (left edge) to (right edge): 235 mils Distance from Pin 3 (right edge) to (left edge): 165 mils Bill of Material Reference Design Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a ½ W High Linearity Amplifier Qorvo 1.8 pf CAP, 63, ±.5 pf, 5V, ACCU-P AVX 635J1R8ABSTR 1.5 pf CAP, 63, ±.5 pf, 5V, ACCU-P AVX 635J1R5ABSTR, 22 pf CAP, 63, 5%, 5V, NPO/COG various 1. uf CAP, 63, 1%, X5R, 1V various.9 pf CAP, 63 AVX 635JR9ABSTR 2.2 Ω RES, 42 various R2 Ω RES, 63, 5%, 1/16W, Chip various 18 nh IND, 85, 5%, Ceramic Coilcraft 85CS-18XJL Datasheet December 26, 217 Subject to change without notice 16 of 26

17 S22 (db) OIP3 (dbm) Gain (db) S11 (db) Typical Performance Reference Design Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.), Temp=+25 C Parameter Conditions Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm OIP3 Pout= +9 dbm / Tone, Δf = 1 MHz dbm Performance Plots Reference Design Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.), Temp.=+25 C 16 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency 5 OIP3 vs. Pout / Tone MHz 25 MHz 27 MHz Pout / Tone (dbm) Datasheet December 26, 217 Subject to change without notice 17 of 26

18 GHz Evaluation Board ( PCB26) J4 J3 J3 +5V 1. uf J4 GND 22 pf R2 J1 Input 1.8 pf , nh (85) 22 pf J2 Output 1.5 pf.6 pf 1. See Evaluation Board PCB Information for material and stack up. 2. Components shown on the silkscreen but not on the schematic are not used. 3. Ω resistors (R2) may be replaced with copper trace in the target application layout. 4. The recommended component values are dependent upon the frequency of operation. 5. All components are of 63 size unless stated on the schematic. 6. Critical component placement locations: Distance from Pin 1 (left edge) to (right edge): 13 mils Distance from Pin 1 (left edge) to (right edge): 7 mils Distance from Pin 1 (left edge) to (right edge): 148 mils Distance from Pin 3 (right edge) to (left edge): 78 mils Bill of Material PCB26 Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a ½ W High Linearity Amplifier Qorvo 1.8 pf CAP, 63, ±.5 pf, 5V, ACCU-P AVX 635J1R8ABSTR 1.5 pf CAP, 63, ±.5 pf, 5V, ACCU-P AVX 635J1R5ABSTR, 22 pf CAP, 63, 5%, 5V, NPO/COG various 1. uf CAP, 63, 1%, X5R, 1V various.6 pf CAP, 63, ±.5 pf, 5V, ACCU-P AVX 635JR6ABSTR 1. Ω RES, 42, 1%, 1/16W. CHIP. various R2 Ω RES, 63, 5%, 1/16W, Chip various 18 nh IND, 85, 5%, Ceramic Coilcraft 85CS-18XJL Typical Performance PCB26 Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.), Temp.=+25 C Parameter Conditions Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm OIP3 Pout= +11 dbm/tone, Δf=1 MHz dbm WCDMA Channel Power (1) 5 dbc ACLR dbm 1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 1.2 db at.1% Prob. Datasheet December 26, 217 Subject to change without notice 18 of 26

19 OIP3 (dbm) ACLR (dbc) S22 (db) P1dB (dbm) Gain (db) S11 (db) Performance Plots PCB26 Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.), Temp.=+25 C 17 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency 3 P1dB vs. Frequency OIP3 vs. Pout/tone ACLR vs. Output Power WCDMA Test Model 1+64 Channels, probability, 3.84MHz BW, ±5MHz offset MHz 26 MHz 25 MHz MHz 26 MHz 25 MHz Pout/Tone (dbm) Pout (dbm) Datasheet December 26, 217 Subject to change without notice 19 of 26

20 34 36 MHz Reference Design J4 J3 J3 +5V 1. uf J4 GND 22 pf R2 J1 Input R2.7 pf 1 2, nh (85) 22 pf J2 Output.8 pf.7 pf 7. See Evaluation Board PCB Information for material and stack up. 8. Components shown on the silkscreen but not on the schematic are not used. 9. Ω resistors (R2) may be replaced with copper trace in the target application layout. 1. The recommended component values are dependent upon the frequency of operation. 11. All components are of 63 size unless stated on the schematic. 12. Critical component placement locations: Distance from Pin 1 (left edge) to (right edge): 87 mils Distance from Pin 1 (left edge) to (right edge): 21 mils Distance from Pin 3 (right edge) to (left edge): 15 mils Bill of Material MHz Reference Design Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a.25 W High Linearity Amplifier Qorvo R2 Ω RES, 63, 5PCT. 1/16W. CHIP various,.7 pf CAP, 63, ±.1 pf, 5V various.8 pf CAP, 63, ±.1 pf, 5V various, 22 pf CAP, 63, 5%, 5V, NPO/COG various 1. uf CAP, 63, 1%, X5R, 1V various 18 nh Inductor, 85, 5%, Coilcraft CS series Coilcraft 85CS-18XJLB Typical Performance MHz Reference Design Test conditions unless otherwise noted: VCC=+5V, ICQ=137 ma (typ.), Parameter Conditions Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm OIP3 Pout= +11 dbm/tone, Δf=1 MHz dbm WCDMA Channel Power (1) 5 dbc ACLR dbm 1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, +5 MHz offset, PAR = 1.2 db at.1% Prob Datasheet December 26, 217 Subject to change without notice 2 of 26

21 ACLR (dbc) P1dB (dbm) S22 (db) OIP3 (dbm) Gain (db) S11 (db) Performance Plots MHz Reference Design Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.), Temp= 16 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency 5 OIP3 vs. Pout/tone MHz 35 MHz 34 MHz Pout/Tone (dbm) ACRL vs. Pout WCDMA Test Model 1+64 Channels, probability, 3.84MHz BW, ±5MHz offset P1dB vs. Frequency MHz 35 MHz 34 MHz Pout (dbm) Datasheet December 26, 217 Subject to change without notice 21 of 26

22 Application Note GHz (1/2 Watt - 1 Watt) Tunable Reference Design This application note describes the ability to take the GHz design and tune it from 1/2 Watt to 1 Watt simply by changing the output match (one component). By use of Load-Pull data we were able to see the capability of this part to be tuned from +27 dbm P1dB to +3 dbm by trading off OIP3 performance. This gives the end user the option to run the as a 1 Watt device over a wide frequency band. Below are the different Reference Design options which show the performance trade-offs between P1dB and OIP3 by changing the value and placement of. Evaluation Board J4 J3 J3 +5V 1. uf J4 GND 22 pf J1 L2 J2 J1 Input L2 2.2 nh 1.8 pf , nh (85) 22 pf J2 Output 1.5 pf.8-2. pf 1. All components are of 63 size unless stated on the schematic. 2. The recommended component values are dependent upon the frequency of operation. 3. Critical component placement locations: Distance between Pin 1 Pad to (right edge): 1 mil Distance between Pin 1 Pad to (right edge): 11 mil Distance between Pin 1 Pad to (right edge): 65 mil Distance between Pin 3 Pad to (left edge): see below: Component Placement Option P1dB Value (pf) Line Length (mils) Electrical Length at 2 GHz (degrees) Datasheet December 26, 217 Subject to change without notice 22 of 26

23 P1dB (dbm) OIP3 (dbm) OIP3 (dbm) OIP3 (dbm) Gain (db) Input Return Loss (db) Output Return Loss (db) Performance Plots GHz (1/2 Watt - 1 Watt) Tunable Reference Design Test conditions unless otherwise noted: VCC=+5 V, ICQ=137 ma (typ.), Temp= 17 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency Option 1 Option 2 Option 3 Option 4-1 Option 1 Option 2 Option 3 Option 4-1 Option 1 Option 2 Option 3 Option OIP3 vs. Pout/tone Option 1 Option 2 Option 3 Option OIP3 vs. Pout/tone Option 1 Option 2 Option 3 Option OIP3 vs. Pout/tone Option 1 Option 2 Option 3 Option 4 4 Freq = 185 MHz Pout/Tone (dbm) 4 Freq = 196 MHz Pout/Tone (dbm) P1dB vs. Frequency 31 4 Freq = 217 MHz Pout/Tone (dbm) Option 1 Option 2 26 Option 3 Option Datasheet December 26, 217 Subject to change without notice 23 of 26

24 Pin Configuration and Description Backside Paddle - GND Pin No. Label Description IN GND OUT / V CC 1 IN input. External DC Block required. Requires conjugate match for optimal performance. 2, Backside Paddle GND /DC ground. Use recommended via pattern to minimize inductance and thermal resistance. See PCB Mounting Pattern for suggested footprint. 3 OUT / VCC output, matched to 5 ohms. External DC Block and bias voltage required. Evaluation Board PCB Information PC Board Layout PCB Material (stackup): 1 oz. Cu top layer.14 inch Nelco N-4-13, εr=3.7 1 oz. Cu MIDDLE layer 1 Core Nelco N oz. Cu middle layer 2.14 inch Nelco N oz. Cu bottom layer Finished board thickness is.62±.6 5 ohm line dimensions: width =.28, spacing =.28. The pad pattern shown has been developed and tested for optimized assembly at Qorvo. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from supplier to supplier, careful process development is recommended. Datasheet December 26, 217 Subject to change without notice 24 of 26

25 Package Marking and Dimensions Package Marking Product ID: 7M912 Trace Code: XXXX 1. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP Trace code up to 4 characters to be assigned by sub-contractor PCB Mounting Pattern 1. All dimensions are in millimeters. Angles are in degrees. 2. Use 1 oz. copper minimum for top and bottom layer metal. 3. Via holes are required under the backside paddle of this device for proper /DC grounding and thermal dissipation. 4. Do not remove or minimize via hole structure in the PCB. Thermal and grounding is critical. 5. We recommend a.35mm (#8/.135") diameter bit for drilling via holes and a final plated thru diameter of.25 mm (.1 ). 6. Ensure good package backside paddle solder attach for best electrical and thermal performance. Datasheet December 26, 217 Subject to change without notice 25 of 26

26 Handling Precautions Parameter Rating Standard ESD Human Body Model (HBM) Class 2 ESDA / JEDEC JS ESD Charged Device Model (CDM) Class ESDA / JEDEC JS MSL Moisture Sensitivity Level Level 1 IPC/JEDEC J-STD-2 Caution! ESD-Sensitive Device Solderability Compatible with lead-free (26 C max. reflow temp.) soldering process. Solder profiles available upon request. Contact plating: Annealed Matte Tin or Nickel Palladium Gold (NiPdAu) RoHS Compliance This part is compliant with 211/65/EU RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment) as amended by Directive 215/863/EU. This product also has the following attributes: Lead Free Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (5H12Br42) Free PFOS Free SVHC Free Pb Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations: Web: Tel: customer.support@qorvo.com For technical questions and application information: appsupport@qorvo.com Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PEORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright 217 Qorvo, Inc. Qorvo is a registered trademark of Qorvo, Inc. Datasheet December 26, 217 Subject to change without notice 26 of 26