TQM GHz 1/4W Digital Variable Gain Amplifier

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Elvin Hancock
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1 Product Overview The is a digital variable gain amplifier (DVGA) featuring high linearity and digital variable gain control in.5 db step sizes. This DVGA integrates a gain block, a digital-step attenuator (DSA), and a high linearity ¼-watt amplifier into a compact 4x4 mm package. The internal 6- bit DSA provides a.5 db gain control range and is controlled with a serial periphery interface (SPI TM ). The individual stages are accessible to external ports to allow for optimization of the last stage amplifier for use in any GPP telecom band and also allowing other functional blocks to be added in-between the stages. The features variable gain from db to db at.4 GHz, +4.5 dbm output IP, and +4 dbm PdB while only consuming 74 ma current from a 5V supply. The module is available in a compact 4-pin 4x4 mm leadless SMT package. 4 Pin 4x4 mm leadless SMT Package Key Features 6-4 MHz db Maximum Gain at 4 MHz.5 db Gain Range in.5 db Steps +4.5 dbm Output IP +4 dbm Output PdB.6 db Noise Figure -wire SPI Control Programming Tunable for any GPP telecom band Functional Block Diagram Applications Pin Marking 4 DSA Out Amp In Wireless Infrastructure Small cell BTS PreG / 5G Massive MIMO systems TDD-based architectures DSA In DSA 6 Amp Out / V C 4 5 LE Amp Out / V CC 5 6-BIT SPI 4 SID 6 CLK 7 8 Amp In SOD 9 Top View V DD Backside Paddle /DC GND Ordering Information Part No. Description T 5 pieces on a reel -PCB9 9 MHz Evaluation Board -PCB4 4 MHz Evaluation Board Datasheet, January 4, 8 Subject to change without notice of 9

2 Absolute Maximum Ratings Parameter Rating Storage Temperature 5 to 5 C Input Power, CW, 5Ω, T=5 C Supply Voltage () Digital Input Voltage + dbm +5.5 V +.5 V Operation of this device outside the parameter ranges given above may cause permanent damage. Recommended Operating Conditions Parameter Min Typ Max Units Supply Voltage () V TCASE C Tj for > 6 hours MTTF +7 C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Electrical Specifications Test conditions unless otherwise noted: =+5V, Temp= +5 C, matched 4 MHz reference circuit, max. gain setting Parameter Conditions Min Typ Max Units Operational Frequency Range 6 4 MHz Test Frequency 4 MHz Gain 9 5 db Gain Control Range.5 db Step Size.5 db Accuracy Error ±(.+5% of Attenuation setting) db Input Return Loss 7 db Output Return Loss db Output PdB + +4 dbm Output IP Pout = + dbm/tone, f = MHz dbm Noise Figure.5 db Total Supply Current 4 74 ma Amp Current 85 ma Amp Current 87 ma DSA Current ma Thermal Resistance, θjc Junction to case 6.7 C/W Datasheet, January 4, 8 Subject to change without notice of 9

3 Serial Control Interface The has a CMOS SPI TM input compatible serial interface. This serial control interface converts the serial data input stream to parallel output word. The input is -wire (CLK, LE and SID) SPI TM input compatible. At power up, the serial control interface resets the DSA to the minimum gain state. The 6-bit SID (Serial Input Data) word is loaded into the register on rising edge of the CLK, MSB first. When LE is high, CLK is internally disabled. Serial Control Timing Characteristics (Test conditions: V DD = +5 V, Temp.=5 C) Parameter Condition Min Max Units Clock Frequency 5% Duty Cycle MHz LE Setup Time, tlesup after last CLK rising edge ns LE Pulse Width, tlepw ns SID set-up time, tsdsup before CLK rising edge ns SID hold-time, tsdhld after CLK rising edge ns LE Pulse Spacing tle LE to LE pulse spacing 6 ns Propagation Delay tplo LE to Parallel output valid ns Serial Control DC Logic Characteristics (Test conditions: V DD = +5 V, Temp.=5 C) Parameter Condition Min Max Units Input Low State Voltage, VIL.8 V Input High State Voltage, VIH.4 V Output High State Voltage, VOH On SOD pin. V Output Low State Voltage, VOL On SOD pin.8 V Input Current, IIH / IIL On SID, LE and CLK pins + µa SID Control Logic Truth Table MSB 6-Bit Control Word LSB D5 D4 D D D D Gain Relative to Maximum Gain Maximum Gain.5 db db db 4 db 8 db 6 db.5 db Any combination of the possible 64 states will provide a reduction in gain of approximately the sum of the bits selected. Timing Diagram CLK is internally disabled when LE is high LE CLK SID D5-D MSB-LSB t PLO D5-D MSB-LSB t SDSUP t SDHLD t LESUP t LEPW Datasheet, January 4, 8 Subject to change without notice of 9

4 67 65 MHz Reference Design pf.9 nh 8. pf J5-9 C L U DSA SPI nh pf uf J R C5 pf R LE J5- DATA J5- C5.4 pf pf Output L 68 nh 6 CLK J5- J5. See Evaluation Board PCB Information section for material and stack-up.. All components are of 4 size.. The left edge of is placed 88 mil from the device package. J5-. uf J Input C pf SOD J5-4 J5- Bill of Material MHz Reference Design Reference Des. Value Description Manuf. Part Number U n/a ¼ W DVGA Qorvo C,,,, pf CAP, 4, 5%. 5V. NPO/COG various. uf CAP, 4, %, 6V, X7R various C5.4 pf CAP, 4, +/-.PF. 5V. NPO/COG various uf CAP, 4, %, V, X5R various 8. pf CAP, 4, +/-.PF. 5V. NPO/COG various L 68 nh IND, 4, 5%, ceramic core Coilcraft 4CS-68NXJL nh IND, 4, 5%, ceramic core Coilcraft 4CS-NXJL.9 nh IND, 4, CHIP Toko LL5-FHN9S.7 Ω RES, 4, +/- %, /W various R,,, Ω RES, 4, CHIP various Datasheet, January 4, 8 Subject to change without notice 4 of 9

5 PdB (dbm) Attenuation Accuracy OIP (dbm) ACLR (dbc) Gain (db) S (db) S (db) Typical Performance MHz Reference Design Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output PdB dbm Output IP Pout= +8 dbm/tone, Δf= MHz dbm LTE Chan. Power () 5 dbc ACLR dbm. ACLR test set-up: CH, MHz BW, LTE E-TM., 9.5 db PAR at.% Probability Performance Plots MHz Reference Design Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting 4 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency Attenuation Accuracy vs. Bit Step Bit Step OIP vs. Pout/tone MHz 65 MHz 5 67 MHz Pout/Tone (dbm) PdB vs. Frequency ACLR vs. Pout LTE CH Mz, Adj ch IBW 8.MHz, PAR 9.5dB no clipping 65 MHz 65 MHz 67 MHz Pout (dbm) Datasheet, January 4, 8 Subject to change without notice 5 of 9

6 -PCB9 Evaluation Board ( MHz) 6.8 pf. nh 4 9 J5-9 C L U DSA SPI nh pf uf J R pf R pf LE J5- DATA J5- Output L 68 nh 6 CLK J5- J5. See Evaluation Board PCB Information section for material and stack-up.. All components are of 4 size.. The left edge of is placed 88 mil from the device package. J5-. uf J Input C pf SOD J5-4 J5- Bill of Material -PCB9 Reference Des. Value Description Manuf. Part Number U n/a ¼ W DVGA Qorvo C,,, pf CAP, 4, 5%. 5V. NPO/COG various. uf CAP, 4, %, 6V, X7R various uf CAP, 4, %, V, X5R various 6.8 pf CAP, 4, +/-.PF. 5V. NPO/COG various L 68 nh IND, 4, 5%, ceramic core Coilcraft 4CS-68NXJL nh IND, 4, 5%, ceramic core Coilcraft 4CS-NXJL. nh IND, 4, CHIP Toko LL5-FHNS R,,,,, Ω RES, 4, CHIP various Datasheet, January 4, 8 Subject to change without notice 6 of 9

7 OIP (dbm) PdB (dbm) Noise Figure (db) Gain (db) S (db) S (db) Typical Performance -PCB9 Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency MHz Gain db Input Return Loss db Output Return Loss 4 4 db Output PdB dbm Output IP Pout= + dbm/tone, Δf= MHz dbm Noise figure... db Performance Plots -PCB9 Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting 45 4 Gain vs. Frequency - Input Return Loss vs. Frequency Output Return Loss vs. Frequency OIP vs. Pout/tone over Frequency 8 PdB vs. Frequency Noise Figure vs. Frequency MHz 95 MHz 869 MHz Pout/tone (dbm) Datasheet, January 4, 8 Subject to change without notice 7 of 9

8 Evaluation Board MHz Reference Design R6.5 pf.5 pf J5-9 C L U R6 DSA SPI nh pf uf J R pf R 8. pf LE J5- DATA J5- Output L 68 nh 6 CLK J5- J5 J5-. uf J Input C pf SOD J5-4 J5-. See Evaluation Board PCB Information section for PCB material and stack-up.. Components are 4 unless specified otherwise. Ohm resistors may be replaced with 5 Ohm traces in the target application layout. Bill of Material MHz Reference Design Reference Des. Value Description Manuf. Part Number U n/a Sample Qorvo C, pf CAP, 4, 5%. 5V. NPO/COG various 8. pf CAP, 4, +/-.5PF. 5V. NPO/COG various pf CAP, 4, 5%. 5V. NPO/COG various. uf CAP, 4, %, 6V, X7R various uf CAP, 4, %, V, X5R various,.5 pf CAP, 4, +/-.PF. 5V. NPO/COG various L 68 nh IND, 5PCT..6 GHz Coilcraft 4CS-68NXJL 8 nh IND, 4, 5%, ceramic core. Coilcraft 4CS-8NXJL 4. Ω RES, 4, 5%, /W, CHIP various R,,,, R6 Ω RES, 4, CHIP various Datasheet, January 4, 8 Subject to change without notice 8 of 9

9 PdB (dbm) Noise Figure (db) Attenuation Accuracy (db) OIP (dbm) ACLR (dbc) Gain (db) Input Return Loss (db) Output Return Loss (db) Typical Performance MHz Reference Design Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output PdB dbm Output IP Pout= +8 dbm/tone, Δf= MHz dbm WCDMA Channel Power () At 5 dbc ACLR dbm Noise Figure db. ACLR Test set-up: GPP WCDMA, TM+64 DPCH, +5 MHz offset, PAR =. db at.% Prob Performance Plots MHz Reference Design Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting 6 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency Attenuation Accuracy vs. Bit Step Part No: 85-88MHz OIP vs. Pout/tone 88 MHz 84 MHz 85 MHz ACLR vs. Pout 88 MHz 84 MHz 85 MHz Bit Step Pout/Tone (dbm) Pout (dbm) PdB vs. Frequency Noise Figure vs. Frequency Datasheet, January 4, 8 Subject to change without notice 9 of 9

10 -PCB4 Evaluation Board ( 7 MHz). nh.8 pf. pf J5-9 C L U DSA SPI nh uf pf J R pf R 8. pf LE J5- DATA J5- Output L 68 nh 6 CLK J5- J See Evaluation Board PCB Information section for material and stack-up.. All components are of 4 size. J5-. uf J Input C pf SOD J5-4 J5- Bill of Material -PCB4 Reference Des. Value Description Manuf. Part Number U n/a ¼ W DVGA Qorvo C, pf Cap 4 5% 5V NPO/COG various 8. pf Cap 4 ±. pf 5V NPO/COG AVX 45U8BATA. uf Cap 4 ±% 6V X7R various uf Cap 4 ±% V X5R various pf Cap 4 5% 5V NPO/COG various. pf Cap 4 ±. pf 5V NPO/COG AVX 4UCATA.8 pf Cap 4 ±.75 pf 5V NPO/COG AVX 45UR8BATA L 68 nh Ind 4 various 8 nh Ind 4 various. nh Ind 4 various R,,, Ω Res 4 various 4. Ω Res 4 various Datasheet, January 4, 8 Subject to change without notice of 9

11 Attenuation Accuracy (db) OIP (dbm) PdB (dbm) NF (db) Gain (db) S (db) S (db) Typical Performance -PCB4 Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency 4 7 MHz Gain db Input Return Loss db Output Return Loss 5 4 db Output PdB dbm OIP Pout= + dbm/tone, Δf= MHz dbm Noise figure db Performance Plots -PCB4 Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting 9 Gain vs. Frequency Input Return Loss vs. Frequency Output Return Loss vs. Frequency C +5 C 4 C C +5 C 4 C C +5 C 4 C OIP vs. Frequency 6 PdB vs. Frequency NF vs. Frequency 5 45 Pout=+ dbm/tone MHz tone spacing +85 C +5 C 4 C C +5 C 4 C C +5 C 4 C Attenuation Accuracy vs. Attenuation.5 7 MHz MHz MHz Attenuation (db) Datasheet, January 4, 8 Subject to change without notice of 9

12 7 MHz Reference Design pf. pf 4 9 J5-9 C L U DSA SPI nh pf uf J R pf R pf LE J5- DATA J5- Output L 8 nh 6 CLK J5- J5 J5-. uf J Input C pf SOD J5-4 J5-. See Evaluation Board PCB Information section for PCB material and stack-up.. Components are 4 unless specified otherwise. Ohm resistors may be replaced with 5 Ohm traces in the target application layout. Bill of Material 7 MHz Reference Design Reference Des. Value Description Manuf. Part Number N/A N/A Printed Circuit Board Qorvo 9578 U N/A Variable Gain Amplifier Qorvo C,, pf CAP, 4, 5%. 5V. NPO/COG various pf CAP, 4, +/-.5PF. 5V. NPO/COG various. uf CAP, 4, %, 6V, X7R various uf CAP, 4, %, V, X5R various. pf CAP, 4, +/-.5PF. 5V. ACCU-P AVX 4JABSTR pf CAP, 4, +/-.5PF. 5V. NPO/COG various L, 8 nh IND, 4, 5%, ceramic core. Coilcraft 4CS-8NXJL R,,,,, Ω RES, 4, CHIP various Datasheet, January 4, 8 Subject to change without notice of 9

13 PdB (dbm) OIP (dbm) Gain (db) Return Loss (db) Typical Performance 7 MHz Reference Design Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency MHz Gain db Input Return Loss db Output Return Loss 6 db Output PdB dbm Output IP Pout= + dbm/tone, Δf= MHz dbm Performance Plots 7 MHz Reference Design Test conditions unless otherwise noted: =+5 V, Temp=+5 C, DSA at max. gain setting Gain vs. Frequency - Return Loss vs. Frequency Output RL Input RL PdB vs. Frequency OIP vs. Pout/tone over Frequency MHz 6 MHz 5 MHz Pout/tone (dbm) Datasheet, January 4, 8 Subject to change without notice of 9

14 4 6 MHz Reference Design.6 pf 4 9 J5-9 L SPI nh pf uf L4 C U DSA 6 C.pF J R C Place piece of trace to cover the gap pf L 8 nh R pf LE J5- DATA J5- CLK J5- Output J5 J5-. uf J Input C pf L4. nh SOD J5-4 J5-. See Evaluation Board PCB Information section for PCB material and stack-up.. Components are 4 unless specified otherwise. Ohm resistors may be replaced with 5 Ohm traces in the target application layout. 4. Critical component placement: a. Distance between U to L4 (left edge): 8 mils b. Distance between to C (edge to edge): mils Bill of Material 4 6 MHz Reference Design Reference Des. Value Description Manuf. Part Number N/A N/A Printed Circuit Board Qorvo 9578 U N/A Variable Gain Amplifier Qorvo C,, pf CAP, 4, 5%. 5V. NPO/COG various pf CAP, 4, +/-.5PF. 5V. NPO/COG various. uf CAP, 4, %, 6V, X7R various uf CAP, 4, %, V, X5R various Use Copper/Metal strip to connect gap various.6 pf CAP, 4, +/-.5PF. 5V. ACCU-P AVX 4JBBSTR C.pF CAP, 4, +/-.5PF. 5V. ACCU-P AVX 4JABSTR L, 8 nh IND, 4, 5%, ceramic core. Coilcraft 4CS-8NXJL L4.nH IND, 4 Multilayer Chip Toko LL5-FHNS R,,,, Ω RES, 4, CHIP various Datasheet, January 4, 8 Subject to change without notice 4 of 9

15 OIP (dbm) PdB (dbm) Gain (db) Return Loss (db) Typical Performance 4 6 MHz Reference Design Test conditions unless otherwise noted: =+5V, Temp= +5 C, DSA at max. gain setting Parameter Conditions Typical Values Units Frequency MHz Gain db Input Return Loss 8 9 db Output Return Loss db Output PdB dbm Output IP Pout= + dbm/tone, Δf= MHz dbm Performance Plots 4 6 MHz Reference Design Test conditions unless otherwise noted: =+5 V, Temp=+5 C, DSA at max. gain setting Minimum Attenuation State Gain vs. Frequency Minimum Attenuation State Return Loss vs. Frequency Input Return Loss Output Return Loss Minimum Attenuation State OIP vs. Pout/tone 6 PdB vs Frequency MHz 5 MHz 6 MHz 8 9 Pout/Tone (dbm) Datasheet, January 4, 8 Subject to change without notice 5 of 9

16 Detailed Device Description The is a digital variable gain amplifier (DVGA) featuring high linearity over the entire gain control range. The amplifier module features the integration of a 5 Ω internally matched high linearity low noise amplifier gain block, a digital step attenuator (DSA), along with a high linearity ¼W amplifier as shown in the functional diagram below. The DVGA has an operational frequency range from.7 4. GHz. The three stages are individually accessible via package I/O contacts. This permits full flexibility to insert other components or filters between the stages. Functional Schematic Diagram AMP DSA AMP SPI AMP AMP is a high linearity low noise amplifier. The amplifier has high gain across a broad range of frequencies while also providing very low noise. It is internally matched and only requires an external choke and blocking/bypass capacitors for operation from a single +5V supply. The internal active bias circuit also enables stable operation over bias and temperature variations. At.9 GHz, the amplifier typically provides 9.8 db gain, +6 dbm OIP, and. db Noise Figure while only drawing 85 ma of current. DSA (Digital Step Attenuator) The DSA is a high linearity, low insertion loss, 6-bit,.5 db Digital Step Attenuator (DSA) operating over the 7-4 MHz frequency range. The digital step attenuator uses a single positive 5V supply and has a serial periphery interface (SPI TM ) for changing attenuation states. This product maintains high attenuation accuracy over frequency and temperature. No external matching components are needed for the DSA. AMP AMP is a high-linearity driver amplifier that delivers high performance past 4GHz. With external tuning it can achieve over +4 dbm OIP with +5 dbm PdB while only consuming 87 ma of quiescent current. Chain Analysis Table This table provides the typical performance of individual stages in the module as well as overall module performance. Frequency = 4 MHz. Parameter AMP DSA AMP Overall Module Units Gain db NF db OIP dbm PdB.9.9 dbm Icc ma Datasheet, January 4, 8 Subject to change without notice 6 of 9

17 Pin Configuration and Description Pin Marking 4 DSA Out Amp In DSA In DSA 6 Amp Out / V C 4 5 LE Amp Out / V CC 5 6-BIT SPI 4 SID 6 CLK Amp In SOD V DD Backside Paddle /DC GND Pin No. Label Description,, 4, 6, 7, 9,, 7, No electrical connection. Land pads should be provided for PCB mounting 8, 9,,, 4 integrity. DSA In DSA Input 5 Amp Out / VCC output / DC supply (Amp). 8 Amp In input (Amp). Band-specific matching circuit required. SOD Serial Output Data DC Supply CLK Serial Clock 4 SID Serial Input Data 5 LE Latch Enable 6 Amp Out / VC output / DC supply (Amp). Band-specific matching circuit required. Amp In input (Amp). Band-specific matching circuit required. DSA Out DSA Output Backside Paddle /DC GND /DC ground. Use recommended via pattern to minimize inductance and thermal resistance. See PCB Mounting Pattern. Evaluation Board PCB Information Qorvo PCB 9578 Material and Stack-up.4".6 ±.6 Finished Board Thickness.4" Nelco N-4- Nelco N-4- ε r =.7 typ. Nelco N-4- oz. Cu top layer oz. Cu inner layer oz. Cu inner layer oz. Cu bottom layer Datasheet, January 4, 8 Subject to change without notice 7 of 9

18 Mechanical Information Package Marking and Dimensions Marking: Part number Year/week/country code - YYWW CCCC Trace Code Up to 6 characters. All dimensions are in millimeters. Angles are in degrees.. Dimension and tolerance formats conform to ASME Y4.4M The terminal # identifier and terminal numbering conform to JESD 95- SPP-. PCB Mounting Pattern 6X PACKAGE OUTLINE 4X.8.5 PITCH R.9.9 4X COMPONENT SIDE. All dimensions are in millimeters. Angles are in degrees.. Use oz. copper minimum for top and bottom layer metal.. Vias are required under the backside paddle of this device for proper /DC grounding and thermal dissipation. 4. Do not remove or minimize via hole structure in the PCB. Thermal and grounding is critical. 5. We recommend a.5mm (#8/.5") dia. bit for drilling via holes and a final plated thru diameter of.5 mm (. ). 6. Ensure good package backside paddle solder attach for reliable operation and best electrical performance. 7. There is no effect to the performance if Pads 9 and are removed from the land pattern. Datasheet, January 4, 8 Subject to change without notice 8 of 9

Handling Precautions Parameter Rating Standard ESD Human Body Model (HBM) Level A ESDA / JEDEC JS-- ESD Charged Device Model (CDM) Level JEDEC JESD-CF MSL Moisture Sensitivity Level Level IPC/JEDEC

19 Handling Precautions Parameter Rating Standard ESD Human Body Model (HBM) Level A ESDA / JEDEC JS-- ESD Charged Device Model (CDM) Level JEDEC JESD-CF MSL Moisture Sensitivity Level Level IPC/JEDEC J-STD- Caution! ESD-Sensitive Device Solderability Compatible with both lead-free (6 C max. reflow temp.) and tin/lead (45 C max. reflow temp.) soldering processes. Solder profiles available upon request. Contact plating: Electrolytic plated Au over Ni RoHS Compliance This part is compliant with EU /95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment). This product also has the following attributes: Product uses RoHS Exemption 7c-I to meet RoHS Compliance requirements Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (C5HBr4) Free PFOS Free SVHC Free Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations: Web: Tel: customer.support@qorvo.com For technical questions and application information: appsupport@qorvo.com Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PEORMAE, USAGE OF TRADE OR OTHERWISE, ILUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright 7 Qorvo, Inc. Qorvo is a registered trademark of Qorvo, Inc. Datasheet, January 4, 8 Subject to change without notice 9 of 9

TQM GHz ¼W Digital Variable Gain Amplifier

TQM GHz ¼W Digital Variable Gain Amplifier Applications 3G / 4G Wireless Infrastructure Repeaters LTE / WCDMA / CDMA 4 Pin 4x4 mm leadless SMT Package Product Features Functional Block Diagram 7-4 MHz 3 db Maximum Gain at 4 MHz 3.5 db Gain Range