Introduction to Power Integrity SPI 2016

Size: px

Start display at page:

Download "Introduction to Power Integrity SPI 2016"

Quentin Whitehead
6 years ago
Views:

1 Introduction to Power Integrity SPI 2016 by Steve Sandler - Picotest CEO Steve@picotest.com and Heidi Barnes Keysight Technologies heidi_barnes@keysight.com

2 POWER INTEGRITY BASICS IN 3.5 HOURS Electronics are increasingly more sensitive to the quality of power, while also placing greater demands on the power system design. Lower voltages, higher currents, and faster speeds all drive challenges. What you ll gain today An understanding of what power integrity is and the Rules of Engagement The four main components of a power distribution system How power related noise degrades system performance and what to do about it Why flat PDN impedance is important and how to achieve it Introduction to Power Integrity measurements and simulation MORE INTERACTIVE = MORE GAIN! Copyright 2016 Picotest.com, All Rights Reserved 2

3 And Just a Bit About Steve 38 Years Experience (1977-present) AEi Systems Founder and CTO (1995-) Picotest Founder and Managing Director (2010-) Experience: Space Shuttle, Space Station, GPS, Large Hadron Collider and many other military and commercial projects Primarily focused on RF, Analog, and Distributed Power Systems I enjoy writing lecturing lab time and making pizza Copyright 2016 Picotest.com, All Rights Reserved 3

4 And Just a Bit About Heidi 30 Years Experience (1986-present) High Speed Digital RF/uW Packaging Sensors and Instrumentation BS EE California Institute of Technology, Present Keysight EEsof EDA Tools Signal Integrity and Power Integrity I enjoy writing simulating measuring and all forms of H20 Copyright 2016 Picotest.com, All Rights Reserved 4

And With the Power Related Stuff Ripple stripper Amp bias with 4 stages of noise reduction Noise averaging voltage bias with 3 filtering stages Current reg for reduced modulation Power / bias

7 And With the Power Related Stuff Ripple stripper Amp bias with 4 stages of noise reduction Noise averaging voltage bias with 3 filtering stages Current reg for reduced modulation Power / bias Oscillator There s much more circuitry dedicated to the power and bias than to the oscillator! Courtesy Copyright 2016 Picotest.com, All Rights Reserved 7

8 A Simple Power Distribution Network (PDN) INPUT FILTER REGULATOR PCB CAPACITORS INPUT POWER EMI FILTER DECOUPLING VRM PLANES / CABLES r CAPACITORS LOAD SIMPLE POWER SYSTEM IT S ALL ABOUT THE LOAD Copyright 2016 Picotest.com, All Rights Reserved 8

9 AND CONTINUING INTO THE LOAD BOND WIRES MORE ICs / DEVICES CAPS PINS IC / DEVICE BJT DIE MORE ICs / DEVICES MORE ICs / DEVICES PERFORMANCE LOAD PI is about delivering the APPROPRIATE power quality here. Copyright 2016 Picotest.com, All Rights Reserved 9

10 INPUT So What Are the Fundamental Noise Paths? Input Feedthru Z interconnect Filter Related Single Power Distribution Path Filter Planes/Traces Regulator Planes/Traces Turn on overshoot is a frequently overlooked noise signal VRM Internal ripple and/or noise including DC Load induced ( I Z) Z interconnect Load LNA VCO ADC FPGA CPU MEMORY USB3 Copyright 2016 Picotest.com, All Rights Reserved 10

The PDN Seen as a Series of Networks Passive Network Active Network 1 2 3 4 Passive Network 5 6 INPUT Z interconnect Filter Planes/Traces Vref VRM Vref is a dominant noise source, though it is not

11 The PDN Seen as a Series of Networks Passive Network Active Network Passive Network 5 6 INPUT Z interconnect Filter Planes/Traces Vref VRM Vref is a dominant noise source, though it is not generally accessible Planes/Traces Z interconnect Load LNA VCO ADC FPGA CPU MEMORY USB3 Low noise is obtained by: Minimizing interaction between network ports [2,3] and [4,5] Maximizing isolation between network ports [1,2], [3,4] and [5,6] Minimizing self generated noise within each network Copyright 2016 Picotest.com, All Rights Reserved 11

13 The VRM is Also a Noise Hub [4,3] = PSRR (power supply rejection ratio) [3,3] = Input Impedance (can be negative!) [4,4] = Output Impedance (R-L network) [3,4] = Reverse Transfer [Vref,4] = Turn on Overshoot and Noise Path Active Network 3 4 Vref VRM The VRM also generates internal noise. This can be comprised of switching ripple, spike noise, modulation noise, shot and flicker noise, etc. The VRM is an ACTIVE network, meaning that it has a feedback loop, which is important to consider. Copyright 2016 Picotest.com, All Rights Reserved 13

Reverse Transfer - (S12) All of the Noise Paths are

Ratio Input Impedance - (S11) Input impedance can

14 Reverse Transfer - (S12) All of the Noise Paths are Related Output Impedance - (S22) Iin/Iout PSRR - (S21) Port 1 VRM Port 2 Iin Iout Vin IN OUT Vout RTN Output Noise/Spikes Power Supply Rejection Ratio Input Impedance - (S11) Input impedance can be NEGATIVE! Copyright 2016 Picotest.com, All Rights Reserved 14

All Are Related to Impedance The degree of

greater due to the different y-axis scaling

16 If All are Related, Why Choose Impedance? Modern circuits are DENSE..and continuously shrinking 6 Output Power Supply 2013 egan 2014 LDO 8.5mm 72mm 2 8.5mm More Power Supplies The output capacitor is one place that is almost always available to measure (miniscule though it may be) 12mm 2 AND, as we said, all performance paths are related to impedance Copyright 2016 Picotest.com, All Rights Reserved 16

These Can be Active or Passive Elements There is little difference in the impact of active and passive elements other than where to go to improve performance.

19 These Can be Active or Passive Elements There is little difference in the impact of active and passive elements other than where to go to improve performance. Voltage regulators usually result in active inductors L = Ro + Rj a G + 2 Ro = Bulk regulator resistance Rj = Dynamic regulator resistance a = Control loop pole G = DC control loop gain And conversely, current regulators (and electronic loads) usually result in active capacitors Copyright 2016 Picotest.com, All Rights Reserved 19

20 Source = Interconnect = Load VRM Simply Defined PDN Load Z o = L C = 1 This is why RF instruments are 50Ω source, 50Ω cable, and 50Ω load R1 = R2 = Zo FLAT Q = Z o R1 + R2 What happens when they DON T match? And what does that have to do with PI? Copyright 2016 Picotest.com, All Rights Reserved 20

10 7 f/hz OPEN : Mag(Impedance) MATCH : Mag(Impedance) SHORT

23 Really Simple Demonstration Load VRM 1m 50Ω COAX cable TR1/Ohm Open Match Short f/hz OPEN : Mag(Impedance) MATCH : Mag(Impedance) SHORT : Mag(Impedance) Copyright 2016 Picotest.com, All Rights Reserved 23

50Ω PCB trace VRTS3 Training Demo Board A Simple ADS-PCB Demonstration Load TR1/Ohm 10 5 10 4 10 3 10 2 10 1 10 0 10-1 10-2 microstrip VRM f/hz TR1/Ohm 1 Cursor 1 10.065M 2.694 ωc 709.

24 50Ω PCB trace VRTS3 Training Demo Board A Simple ADS-PCB Demonstration Load TR1/Ohm microstrip VRM f/hz TR1/Ohm 1 Cursor M ωc Quick Tip Open Match Short f/hz OPEN : Mag(Impedance) MATCH : Mag(Impedance) SHORT : Mag(Impedance) Z o = ωl ωc ωl = L C = 43.8Ω Copyright 2016 Picotest.com, All Rights Reserved 24

25 Simulation Tricks The PCB Layout Simulations in the frequency domain are very fast: Results can be expressed in S, Y, or Z values Distributed Models: Electrical Delay and Parasitics Transmission Line Algorithmic Model or Z = V when AC stimulus is 1 Amp S-Parameter Behavioral Model EM Simulated Copyright 2016 Keysight Technologies, All Rights Reserved 25

26 L/C Parallel Resonance Problem in the PDN Design f resonance khz 126 mω Z o = L C = 50nH 100uF = 22.4mΩ Q = Z o R = 22.4mΩ 4mΩ = 5.6 Z peak = Z o Q = 125mΩ f 1 2π LC 1 2π 50nH 100uF 71kHz ΔV=ΔI Z peak =250mV pp Copyright 2016 Keysight Technologies, All Rights Reserved 26

27 L-C Series Resonance Problem with Capacitors Capacitor Model Z Impedance Curve ESRcap j ESLcap 1 j C Series C-R-L Impedance vs. Frequency Voltage and current are in phase at f cap 1 fcap 2 ESL C cap Damping factor (D) expresses the sharpness of the transition from C to L. Higher D =slower phase change at f 0 phase of I leads V phase of V leads I D 1 ESR 2Q 2 cap C ESL cap f cap V in phase with I (Pure resistance) Copyright 2016 Keysight Technologies, All Rights Reserved 27

TR1/Ohm 10 5 10 4 10 3 10 2 10 1 10 0 10-1 10-2 Adding a

The L above 21MHz is the ESL of the decoupling capacitor PLUS PCB

28 TR1/Ohm Adding a Decoupling Capacitor at the Load f/hz OPEN 15nF : Mag(Impedance) MATCH 15nF : Mag(Impedance) SHORT 15nF : Mag(Impedance) This is the R for frequencies above 21MHz. The L above 21MHz is the ESL of the decoupling capacitor PLUS PCB and interconnect inductance Load Load Copyright 2016 Picotest.com, All Rights Reserved 28

29 An Actual Circuit Clock and buffer The Picotest VRTS3 training board includes an example with a VRM connected to a clock. Several output capacitor choices are available to highlight the impedance issues. Added PCB inductance 10nF cap output caps Copyright 2016 Picotest.com, All Rights Reserved 29

30 Injecting the Harmonic Comb signal at the Clock capacitor shown earlier reveals the impedance resonance Harmonic Comb Example Clock and buffer Sensitivities identified by interrogating with the comb 10nF cap Copyright 2016 Picotest.com, All Rights Reserved 30

In this example, a 7MHz resonance in the

31 In this example, a 7MHz resonance in the PDN shows up as clock jitter. Reducing the VRM impedance increases jitter at 7MHz. Focus on the Load NOT the VRM Trace resonance at 10nF cap VRM stability High ESR Low ESR Copyright 2016 Picotest.com, All Rights Reserved 31

with multiple impedance resonances with flat impedance Multiple resonances can accumulate into a rogue wave How to Design for Power Integrity: Finding Power Delivery Noise Problems www.youtube.

32 with multiple impedance resonances with flat impedance Multiple resonances can accumulate into a rogue wave How to Design for Power Integrity: Finding Power Delivery Noise Problems Ltq84kH8xZ9HIYgBYDsP7TbqBpftidzI8&index=6 The same transient load step stimulus Resulted in these very different voltage transients Copyright 2016 Keysight Technologies, All Rights Reserved 32

Determining the Target Impedance There are many sources of noise and noise sources are additive I f 4 π f=0 Z f V V n 100uV 50kHz noise=23db degradation n=0 The

33 Determining the Target Impedance There are many sources of noise and noise sources are additive I f 4 π f=0 Z f V V n 100uV 50kHz noise=23db degradation n=0 The total noise budget for this FPGA is 30mVpk Oscillators, sensors, ADC s and DAC s are often sensitive to uvs of noise Copyright 2016 Picotest.com, All Rights Reserved 33

35 Reasons We Make Measurements To obtain unavailable data Because the manufacturer s data is erroneous or lacks sufficient detail To compare devices or topologies To troubleshoot non-functional or under performing hardware To validate or verify design performance (as in ATP) To obtain statistics regarding tolerances Copyright 2016 Picotest.com, All Rights Reserved 35

36 Recipe for a High Fidelity Measurement Correct instrument/domain Correct probe and connections Correct measurement method and technique Correct measurement frequency range Correct calibration And KNOW what you expect to see! Copyright 2016 Picotest.com, All Rights Reserved 36

Relating Bandwidth and Rise Time BW(T rise10 ) = 0.34966 90 T rise10 90 T rise10 (BW) = 0.

37 Relating Bandwidth and Rise Time BW(T rise10 ) = T rise10 90 T rise10 (BW) = BW This is true for all single order systems (1-pole) which includes many oscilloscopes Though some oscilloscopes stretch this slightly higher up to 0.4/Trise The bandwidth of most instruments is only a few percent greater than the specified bandwidth in order to minimize noise Copyright 2016 Picotest.com, All Rights Reserved 37

38 Cascading Rise Times Direct connection P2101 Probe Tr=34.79ps Tr=276.94ps T rise = n i=1 2 T rise n = T 2 rise signal + T 2 rise T riseprobe = ps ps 2 = ps scope + T rise 2 probe BW probe = ps = 1.27GHz Copyright 2016 Picotest.com, All Rights Reserved 38

39 Probes - Voltage This simple circuit is the basic representation of a voltage probe Reference Plane The circuit impedance interacts with the probe impedance and can result in undesirable responses The probe loading impedance forms a divider with the circuit impedance and probe interconnects Copyright 2016 Picotest.com, All Rights Reserved 39

40 Probes - Voltage This comparison shows the transient response to a fast step using ¼ inch leads (blue) and a 3.5 inch ground clip (red) A series resistor can also be used to damp the probe ringing The addition of the damping resistor flattens the response and eliminates the ringing The simulated AC response is shown in the figure with and without a 91Ω series resistor using ¼ inch leads (blue) and a 3.5 inch ground clip (red) Copyright 2016 Picotest.com, All Rights Reserved 40

Selecting a Voltage Probe In order to minimize the interaction between the probe and the circuit: 1. The probe s loading impedance should be greater than sum of the circuit impedance 2.

41 Selecting a Voltage Probe In order to minimize the interaction between the probe and the circuit: 1. The probe s loading impedance should be greater than sum of the circuit impedance 2. The probe connection impedance should be up to at least the minimum acceptable measurement bandwidth The probe impedance needs to be 4x-10x the circuit impedance Often a 50 Ohm unity gain probe is the best choice Copyright 2016 Picotest.com, All Rights Reserved 41

cable and instrument up to more than 1GHz Unity gain probes offer the best SNR

42 1 Port and 2 Port Transmission Line Probes Can be used to assess impedance, stability, PDN, and circuit sensitivity to the power supply Each port is precisely 50Ω to match the cable and instrument up to more than 1GHz Unity gain probes offer the best SNR Bidirectional sends stimulus and or receives stimulus Copyright 2016 Picotest.com, All Rights Reserved 42

Bode Plots The open loop Bode plot of the AD820 opamp shows a gain margin of 4dB and a phase margin of 28.

45 Bode Plots The open loop Bode plot of the AD820 opamp shows a gain margin of 4dB and a phase margin of degrees, which matches the GM and PM derived using the Nyquist plot The phase shift falls below 0 degrees indicating at least one more pole The stability margin can t be determined from the Bode plot -content/uploads/2016/01/killingthe-bode-plot-final.pdf Copyright 2016 Picotest.com, All Rights Reserved 45

46 Nyquist Plot and Stability Margin The gain margin is assessed as the length along the horizontal axis between the unstable point and the loop gain curve The phase margin is assessed as the angle formed by the horizontal axis and the unity gain length connection from (0,0) to the loop gain curve The stability margin (0.3066) is less stable than either the GM (0.371) or PM (0.500) Copyright 2016 Picotest.com, All Rights Reserved 46

Measuring Low ESR Capacitors PICOTEST J2160A Polymer Capacitor DUT KEYSIGHT ENA5061B Export Touchstone Impedance file # Hz Z RI R 50 [Number of Ports] 1 [Number Of Frequencies] 201 [Network Data]!

47 Measuring Low ESR Capacitors PICOTEST J2160A Polymer Capacitor DUT KEYSIGHT ENA5061B Export Touchstone Impedance file # Hz Z RI R 50 [Number of Ports] 1 [Number Of Frequencies] 201 [Network Data]!freq ReZ11 ImZ Measured Model Copyright 2016 Picotest.com, All Rights Reserved 47

48 Measuring Impedance Method is chosen primarily by impedance magnitude APPROXIMATE Measurement Ranges 1-port reflection 0.5Ω-2.5kΩ 2-port shunt thru 250uΩ-25Ω * 2-port series thru 25Ω-1MΩ 3-port voltage/current 1mΩ-2kΩ Impedance adapters 0.1 Ω-400kΩ Most Power Integrity Measurements use the 2-port shunt thru method * Later we ll show how to extend this range Impedance (Ohms) 3-port FRA Freq (Hz) 1-port VNA 2-port VNA* *Shunt Thru Copyright 2016 Picotest.com, All Rights Reserved 48

1-Port Reflect vs 2-Port Shunt Through 2-Port Shunt is a 4-wire sensing method that increases sensitivity 220uF Aluminum Polymer 1-port reflection Port 1

49 1-Port Reflect vs 2-Port Shunt Through 2-Port Shunt is a 4-wire sensing method that increases sensitivity 220uF Aluminum Polymer 1-port reflection Port 1 Injects Current Current Density at 1MHz Zshunt = 25 S21 1 S21 2-port shunt thru Port 2 Measures Voltage Copyright 2016 Picotest.com, All Rights Reserved 49

2-Port Impedance Measurement Z DUT = 25 S21 1

VNA input isolates the 50 Ohm instrument

or P2130A J2102A 1 2 Gnd DC Blockers Common

be used, simplifying the connections and

50 2-Port Impedance Measurement Z DUT = 25 S21 1 S21 Connecting low frequency DC Blocks at the VNA input isolates the 50 Ohm instrument loading from the circuit 2-Port Probe J2130A or P2130A J2102A 1 2 Gnd DC Blockers Common Mode Coaxial Transformer -- Ground Loops 1mΩ measurement with and without coaxial transformer In some cases, a 2-port probe can be used, simplifying the connections and getting into small spaces Copyright 2016 Picotest.com, All Rights Reserved 50

IMPEDANCE (OHMS) Separating PCB Mounting L from C ESL MEASURED Shorting the Capacitor Pads to Simulate/Measure the PCB Mounting Inductance 0805 Mounting Inductance PCB EM MODEL +

51 IMPEDANCE (OHMS) Separating PCB Mounting L from C ESL MEASURED Shorting the Capacitor Pads to Simulate/Measure the PCB Mounting Inductance 0805 Mounting Inductance PCB EM MODEL + TUNED C-L-R MODEL L PCB_0805 = 548 ph Current Density at 10 MHz IDEAL 2-PORT SHUNT THROUGH L short = 362pH FREQUENCY (Hz) Copyright 2016 Keysight Technologies, All Rights Reserved 51

2-Port Extended Range Impedance Measurement Z

52 2-Port Extended Range Impedance Measurement Z DUT(min) = RS RS RS Z DUT(max) = RS RS uF with RS=200Ω RS=200Ω can measure approximately 1mΩ to 4kΩ (50 + RS) S21 Z = 2 1 S21 Copyright 2016 Picotest.com, All Rights Reserved 52

TR2 TR2/ TR1/dB -10-20 -30 NISM Non-Invasive Stability Measurement 12 10 1 10 0 10-1 Impedance reflects the stability margin (and so do all other closed loop measurements) -40-50 60 40 10 2 10 3 10 4

53 TR2 TR2/ TR1/dB NISM Non-Invasive Stability Measurement Impedance reflects the stability margin (and so do all other closed loop measurements) TR1: Mag(Gain) f/hz TR2: QTg(Gain) TPS40222 Buck Regulator TR1/dB A 5-V Input, 1.6-A Output, Non-Synchronous Buck Converter TR1: Mag(Gain) f/hz TR2: Unwrapped Phase(Gain) -150 Copyright 2016 Picotest.com, All Rights Reserved 53

Noise Density Noise = Noise_Density RBW Noise amplitude measurement using an oscilloscope spectrum option and various Resolution Bandwidth (RBW) Power Supply Noise Density and Instrument Noise Floor

54 Noise Density Noise = Noise_Density RBW Noise amplitude measurement using an oscilloscope spectrum option and various Resolution Bandwidth (RBW) Power Supply Noise Density and Instrument Noise Floor Measuring noise density directly dbmv Volts BW V/SQRT(BW) E E E E E E E E E E E E-07 Average 4.01E-07 Noise density measurement Measurement noise floor Copyright 2016 Picotest.com, All Rights Reserved 54

55 Clocks Make Great Noise Meters Achieving the optimum performance from the load is dependent getting the power right at the load. This often means the best measurements should be made in the system The noise at the load is generally computed as Higher linear reg impedance yields Higher mid-band noise Linear regulator PCB resonance n i=1 noise i 2 But noise sources can be directly additive Switching POL has spurs But lower impedance is Better in mid-band Copyright 2016 Picotest.com, All Rights Reserved 55

Modulating a clock to determine power supply sensitivity Power Supply Sensitivity Signal Generator 40dB attenuator Line Injector 100uV 50kHz noise=23db degradation 23dB Clock

56 Modulating a clock to determine power supply sensitivity Power Supply Sensitivity Signal Generator 40dB attenuator Line Injector 100uV 50kHz noise=23db degradation 23dB Clock power supply Measurement port Clock output To E5052B Oscillators, sensors, ADC s and DAC s are often sensitive to uv s of noise Copyright 2016 Picotest.com, All Rights Reserved 56

58 And Reconstructing It For Simulation The flatness could be greatly improved by increasing the decoupling capacitance while slightly increasing the ESR 36uF 2mΩ VRM/Bulk Cap Decoupling 90uF 3mΩ Copyright 2016 Picotest.com, All Rights Reserved 58

Designing the Flat Impedance VRM Choose a controller with an external compensation pin Pole often unknown Using a current mode switching VRM allows Rout to be easily set by the the DC error amp gain

60 Designing the Flat Impedance VRM Choose a controller with an external compensation pin Pole often unknown Using a current mode switching VRM allows Rout to be easily set by the the DC error amp gain Not easy to control DC resistance in an LDO Output capacitance and ESR are critical Series resistor is often required Comp Power stage Gfs (PG fs ) is often unknown Internal pole and slope compensation set effective inductance R1, R2 and PG fs set Rout R1 R out = R2 PG fs Copyright 2016 Picotest.com, All Rights Reserved 60

Capacitor ESR must be equal to the desired impedance Quick Tips Noise Budget = DC regulation + Ripple + IRdrop + Startup Overshoot/Step load excursion + Noise C = L Z2 desired Minimizing inductance

61 Four Step Design Process to Flat Impedance 1. Create a noise budget 2. Set impedance level using noise (rail voltage deviation) budget 3. Set the VRM output resistance equal to the desired impedance level (tolerances!) 4. At each node, cancel excess inductance with a capacitor. Capacitor ESR must be equal to the desired impedance Quick Tips Noise Budget = DC regulation + Ripple + IRdrop + Startup Overshoot/Step load excursion + Noise C = L Z2 desired Minimizing inductance reduces capacitor size Higher bandwidth, locate regulator closer to the load, wide planes thinner PCB dielectric There s a lot of variation in voltage regulators, choose wisely lower output inductance wins Ferrite beads are VERY inductive and as a rule should be avoided like the plague Linear regulator inductance varies inversely with load current - assess at the lowest operating current Copyright 2016 Picotest.com, All Rights Reserved 61

LOAD CURRENT Vcomp (V) Iout (A) 1.761 0.00 1.771 0.10 1.783 0.20 1.796 0.30 1.807 0.40 1.818 0.50 1.830 0.60 1.844 0.70 1.859 0.80 1.872 0.90 1.883 1.00 1.910 1.25 1.935 1.50 1.969 1.75 1.986 2.

90 Determining Power Stage Transconductance 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 Measurements are often surprising. Using a 10mΩ resistor should result in PGfs of 10 and it does not. y = 8.

62 LOAD CURRENT Vcomp (V) Iout (A) Determining Power Stage Transconductance Measurements are often surprising. Using a 10mΩ resistor should result in PGfs of 10 and it does not. y = x R² = Slope=PG fs Power Stage Gfs VCOMP LM25116 Evaluation Board PG fs can also be computed from an Rout measurement PG fs = R1 R2 R out Copyright 2016 Picotest.com, All Rights Reserved 62

C = Choosing the Output Capacitor L 2 Z desired Undersized output capacitor reveals the inductance resulting from the internal pole and slope compensation Cap ESL The capacitor is chosen to match the

63 C = Choosing the Output Capacitor L 2 Z desired Undersized output capacitor reveals the inductance resulting from the internal pole and slope compensation Cap ESL The capacitor is chosen to match the desired impedance and to counteract the inductor C out = 1 2π(68kHz)(35mΩ) = 72uF +3dB=68kHz/35mΩ Rout C esr = Rout = 25mΩ Polymer capacitors tend to have flat ESR vs. frequency which works best in these applications Cap ESR Copyright 2016 Picotest.com, All Rights Reserved 63

Four capacitors were chosen to create 4 different flat resistance VRMs Each of the 3 solutions was constructed and measured.

64 Case Study Integrated Switch Step-Down A state space average model was constructed in ADS from several measurements. A number of potential output capacitors were selected and measured then converted to Touchstone files for co simulation. Four capacitors were chosen to create 4 different flat resistance VRMs Each of the 3 solutions was constructed and measured. The TI LM20143 Evaluation board was also measured. The measured impedance results were converted to touchstone files using the BodeFile converter so that they can be displayed along with the simulation result LM20143 Demo Board USB input Load Rfeedback Measurement ports Output cap Copyright 2016 Picotest.com, All Rights Reserved 64

67 IMPEDANCE (OHMS) IMPEDANCE (OHMS) VRM Impedance Model PDN Capacitors AC Sweep for Z Flat Z at lower frequencies reduces the package/ DUT anti-resonance at higher frequencies! VRM Impedance Model Reference Design does not fit an R/L Model! PDN Capacitors AC Sweep for Z VRM Impedance Decoupling Package R/L model assumes a flat PDN design! FREQUENCY (Hz) Copyright 2016 Picotest.com, All Rights Reserved 67

68 IMPEDANCE (OHMS) VRM Impedance Model PDN Capacitors AC Sweep for Z Many VRMs can be tuned for Flat Z. So how do we choose the right one? IMPROVED DESIGN FREQUENCY (Hz) Copyright 2016 Picotest.com, All Rights Reserved 68

69 State 1: SW1 = On and SW2= Off Cin Vc SW1 SW2 Cin RDS_SW1 DCR_Lout Lout Cout STATE SPACE AVERAGED MODEL Duty = Ton_SW1 Fsw Vout = Vin Duty Vc Vout = Vin Vramp State 2: SW1 = Off and SW2= On Lout DCR_Lout RDS_SW2 Cout Copyright 2016 Picotest.com, All Rights Reserved 69

70 State 1: SW1 = On and SW2= Off Cin Vc SW1 SW2 Cin Iout Lout Cout STATE SPACE AVERAGED MODEL Duty = Ton_SW1 Fsw State 2: SW1 = Off and SW2= On Lout Vout = Vin Duty Iout = k Vc Ri Iout Cout Copyright 2016 Picotest.com, All Rights Reserved 70

71 IMPEDANCE (OHMS) PSRR (db) Nominal Impedance is the same, Voltage Mode is very sensitive to tolerances Rout_CM = Ri 1 + Av Rout_VM = DCR Lo + RDSon bot + RDSon top RDSon bot Vin 1 + Av Vramp Vo Vin Nominal PSRR is very different between Current Mode and Voltage Mode PSRR = Vo (ac) Vin (ac) Power Supply Rejection Ratio (PSRR) DCR_Lout +/- 45% Voltage Mode Voltage Mode Current Mode Current Mode FREQUENCY (Hz) FREQUENCY (Hz) Copyright 2016 Picotest.com, All Rights Reserved 71

72 Error Amp Out (volts) Error Amp Out (volts) Error Amp Out (volts) SERIES FEEDBACK Av_series = R3 (Gm R2 1) R1 + R3 + Gm R1 R3 = SHUNT FEEDBACK Av_shunt = R3 Gm R2shunt R1 + R3 = R1 R3 R2 Gm δav_series δgm = R1 R3 R2 Gm δav_shunt δgm = Gfs Error Amp Min = 1.4 e-3 Nominal = 1.7 e-3 Max = 2.0 e-3 Frequency (Hz) Frequency (Hz) Gfs Error Amp Copyright 2016 Picotest.com, All Rights Reserved 72

73 Voltage Mode with Shunt Feedback Error Amp Gain Slope (db) Output Impedance (Ohms) Voltage Mode Series vs Shunt Voltage Mode Series vs Shunt SERIES SHUNT SHUNT SERIES FREQUENCY (Hz) FREQUENCY (Hz) Copyright 2016 Picotest.com, All Rights Reserved 73

74 Output Impedance (ohms) Output Impedance (ohms) Monte Carlo Distribution of VRM Tolerances Tolerance Distribution DCR_Lo=30m 7%+0.4%/degC=50% Transconductance Error Amplifier Gm=10% Vin=10% Vramp=10% (Gslope comp) Lout=25% Cbulk_ESR=20% Cbulk_ESL=20% Monte Carlo of Voltage Mode vs Current Mode Voltage Mode Series Feedback Current Mode Series Feedback Frequency (Hz) Frequency (Hz) Copyright 2016 Picotest.com, All Rights Reserved 74

Model + Measured Co-Simulation Measurement Based State Space Averaged Model.

77 Selecting the Decoupling Capacitors for Flat PDN How to select the right de-coupling capacitors to insure stable low noise performance at minimal cost. Aluminum Bulk Cap only 1 st Decoupling cap 1 st and 2 nd Decoupling cap FLAT PDN = Guaranteed Stability Copyright 2016 Picotest.com, All Rights Reserved 77

Current Example: 4 A 3.3 V 2 A VRM 3.3 V Power Plane Z Target V I (3.

78 Is Target Impedance Really this Simple? Z Target Target Impedance Calculation ( Power _ Supply _ Voltage) ( Allowed _ Ripple) Current Example: 4 A 3.3 V 2 A VRM 3.3 V Power Plane Z Target V I (3.3V ) (5%) ZTarget(3.3V) 82. 5m 2A Target Impedance is the goal that designers should hit!!! Copyright 2016 Keysight Technologies, All Rights Reserved 78

79 Spectral Content of the Sink Digital Switching Spectral Content Edge speeds determine the di/dt maximum for Ldi/dt ripple voltage. I(t) waveform determines the spectral content, digital patterns have a wide bandwidth (peaks at odd harmonics) Dynamic Switching Load Response ON p PRBS OFF n SINE OFF ON p n Copyright 2016 Keysight Technologies, All Rights Reserved 79

Another Example: 1 Volt, 40 Amps Equivalent Series Resistance (ESR) causes a voltage drop (droop) in the supply when the Load draws power from the capacitors in the PDN.

80 Another Example: 1 Volt, 40 Amps Equivalent Series Resistance (ESR) causes a voltage drop (droop) in the supply when the Load draws power from the capacitors in the PDN. Max ESR to prevent Supply Voltage Droop & Kick Example Bulk C ESR ESR ESR I DUT PCT V Supply max_ripple 0.5 PCT max_ripple average transient expected V amount of Supply I supply vol tage in Volts ( PCT Load PCT DUTsupply current in Amps transient current as a droop transient allowable supply droop across 0.5) estimated maximum parallel capacitor ESR in Ohms droop percentage of I DUT the ESR cap I Load PCT V Supply PCT 40 A transient 1V droop 100% 10% ESR max_ripple 1.25 mω V Load V Cap ( I ESR ) cap Load Note: ½ of Voltage Droop caused by ESR and ½ by Capacitor Discharging only valid for simple RC model! Copyright 2016 Keysight Technologies, All Rights Reserved 80

5nH 300pH 100pH Paralleling ceramics is important for meeting target Z x10 x100 x1 Note: Parallel ceramics of the same value have

81 How to Select the PDN Capacitors Limited Bandwidth Requires Multiple Values Effective ESL is Limited by PCB Mounting 4.7uF 100nF 10nF 1.5nH 300pH 100pH Paralleling ceramics is important for meeting target Z x10 x100 x1 Note: Parallel ceramics of the same value have n x C, ESL/n and ESR/n and the f cap does not change A capacitor becomes an inductor above f cap, so it is important to find ways to lower the impedance at higher frequencies f cap 1 2 ESL C Copyright 2016 Keysight Technologies, All Rights Reserved 81

Not All Capacitors are Created Equal Bulk Caps *Datasheets specify a maximum so this table shows actual measured data for some of the capacitors.

82 Not All Capacitors are Created Equal Bulk Caps *Datasheets specify a maximum so this table shows actual measured data for some of the capacitors. For a given capacitor that meets D min, use them in parallel to achieve C Total and ESR max for the ripple target of the Load. Copyright 2016 Keysight Technologies, All Rights Reserved 82

5 nh 0402 ~.4 nh Rs =10mΩ 47uF TR1 10-1 10-2 Ceramic + Rs Ceramic 10 4 10 5 10 6 10 7 f/hz 47uF 6.

83 Ceramic Decoupling Capacitors 47uF External resistors can be used with standard ceramic capacitors with slightly higher inductance but much better selection and lower cost PACKAGE ESL 1206 ~ 1 nh 0805 ~.6 nh 0603 ~.5 nh 0402 ~.4 nh Rs =10mΩ 47uF TR Ceramic + Rs Ceramic f/hz 47uF 6.3V 1206 : Mag(Gain) 47uF 6.3V 10m : Mag(Gain) Convert measurement to Touchstone or RLC Copyright 2016 Picotest.com, All Rights Reserved 83

84 Ceramic Decoupling Capacitors ESR controlled ceramic capacitors such as the TDK s YNA series can be used or external resistance can be used with standard ceramic capacitors, though with higher inductance Copyright 2016 Picotest.com, All Rights Reserved 84

Tuning for Flat Z Requires Measured Models R-L-C Lumped Model in Blue S-Parameter Measured Model in Red RLC model has difficulty capturing the high

85 Tuning for Flat Z Requires Measured Models R-L-C Lumped Model in Blue S-Parameter Measured Model in Red RLC model has difficulty capturing the high frequency characteristics. Xilinx WP411 Jan. 30, 2012 Simulating Power Integrity Using S-Parameter Models Copyright 2016 Keysight Technologies, All Rights Reserved 85

86 PCB Footprints for Ceramic vs Bulk Capacitors Loop Inductance + - L Ceramic Caps Lower ESL helps Bandwidth Via in Pad Lowest L Highest Density Via on Side Low L Bulk Tantalum and Electrolytic Higher ESL is Okay C and ESR are more important then ESL C = L slope 2 Z desired L increases with + and via separation V1 Gnd V2 Bus Bar Design V3 Flexibility for adding different types of capacitors to tune the PDN after assembly based on measured data. Copyright 2016 Keysight Technologies, All Rights Reserved 86

87 Ceramic Capacitor Placement Banks of different size and value caps around the edge of the Package along with small caps placed directly on the BGA vias provide the lowest inductance for high current applications / / / 0402 Designs have even alternated the + and terminals of adjacent capacitors to lower the Inductance. Less mutual inductance. + - The L plane of a buried capacitive layer at the top of the board with topside decoupling capacitors is lower then L via for long PCB Board vias. Ideal Dual Top and Bottom L via DUT L via L plane High dk Layer Simple Design - + Capacitors at the bottom always have the inductance of the Via in the path. Copyright 2016 Keysight Technologies, All Rights Reserved 87

88 Example High Layer Count PCB for ATE 36 Layer PCB, 260 mils 3M ECM High Dielectric Power Via Return Via Ground Plane Power Plane 2.5 mil FR4 3M ECM 11 um Copyright 2016 Keysight Technologies, All Rights Reserved 88

Co-Simulated Results With Decoupling Capacitors The decoupling capacitors can be converted to RLC models or the Touchstone files can be combined directly in a mix and match selection.

90 Co-Simulated Results With Decoupling Capacitors The decoupling capacitors can be converted to RLC models or the Touchstone files can be combined directly in a mix and match selection. Here we are showing a large signal simulation combined with a Touchstone capacitor on one trace. The measured Touchstone result is then combined with touchstone decoupling capacitors to see the flatness with and without the external 10mΩ external resistor. Simulation with Touchstone Bulk capacitor only Touchstone measurement with Touchstone 47uF 10mΩ decoupling Touchstone measurement with Touchstone 47uF without 10mΩ Copyright 2016 Picotest.com, All Rights Reserved 90

Advanced Topics What is SI and PI Co-Simulation

Power Distribution Networks (PDN) 16 Layer PCB

91 Advanced Topics What is SI and PI Co-Simulation and why do I care about PCB EM Simulation? Modern Applications with Multiple PDNs Xilinx Kintex VCU105 Board: Power Planes 15 Major Power Distribution Networks (PDN) 16 Layer PCB Copyright 2016 Keysight Technologies, All Rights Reserved 91

It s All About the Load Target Z Signal Integrity Drives PI Target Z ADS SI Pro + Channel Simulation SI simulation with injected noise Max timing jitter

93 It s All About the Load Target Z Signal Integrity Drives PI Target Z ADS SI Pro + Channel Simulation SI simulation with injected noise Max timing jitter and ripple calculation to set Target Z Measure Supply Induced Amplitude Ripple Timing Jitter Copyright 2016 Keysight Technologies, All Rights Reserved 93

The PI Eco-System VRM + PDN + Load Kill the Rogue Waves with Flat Z PI only Simulation with SI Requirements ADS PI Pro + Transient Simulation VRM Control Loop Stability,

94 The PI Eco-System VRM + PDN + Load Kill the Rogue Waves with Flat Z PI only Simulation with SI Requirements ADS PI Pro + Transient Simulation VRM Control Loop Stability, Active Z PDN PCB and Capacitor Passive Parasitics IR Drop, PDN Z, and Plane Resonances Sink Dynamic Broadband Load Copyright 2016 Keysight Technologies, All Rights Reserved 94

passing Sink-1 VRM : MAX15303 Sink : 2-5

95 PI Min/Max Ripple Includes DC IR Drop Tolerances DC Simulation Result Voltage Drop (Compliance) Sink-1: Controller Power Net : VCC1v2_FPGA With 5% Margin Voltage drop is passing Sink-1 VRM : MAX15303 Sink : 2-5 Copyright 2016 Keysight Technologies, All Rights Reserved 95

coupling between geometries to improve component, via, and capacitor

96 Additional EM - Field Data AC Field Simulation Electric Field 100 MHz Power Plane Cavity Resonances Objective : Evaluates electromagnetic coupling between geometries to improve component, via, and capacitor placement Copyright 2016 Keysight Technologies, All Rights Reserved 96

That results in a target impedance of 0.075 Ohm.

97 PI Analysis Setup : Transient ( Dynamic IR Drop) PDN impedance seen from the IC (U1) The VRM provides 1.2 Volt, the IC pulls 0.8 A Ampere and a 5% tolerance on the supply voltage is allowed. That results in a target impedance of Ohm. We can look at what that implies in the time domain assuming the IC sink would draw current at a frequency of respectively 10 and 100 MHz Copyright 2016 Keysight Technologies, All Rights Reserved 97

PDN Transient Load Simulation - Dynamic IR Drop Without Decaps 10 MHz With Decaps Vcc

99 What the Netlist Doesn t Tell You PCB PDN Design SI and PI Co-EM Simulation ADS SI Pro EM Simulation Signal Net S-Parameters PDN Impedance PCB Resonances PCB Coupling Power, Ground, Signal SI Only Power Aware SI + PI Copyright 2016 Keysight Technologies, All Rights Reserved 99

SI and PI Co-EM Simulation Power and Signal Nets in the same EM simulation Write Channel scheme

SI and PI Co-EM Simulation: S-Parameters Simulation with Decaps ( includes Power

extremely fast. IBIS buffer macromodels are commonly applied for system-level SI simulations instead of transistor-level netlists.

Power-Aware IBIS v5.0 models are used to represent the non ideal power effects.

103 Power Aware IBIS v5.0 Models IBIS (Input/output Buffer Information Specification) models are behavioral using I-V and V-t look-up tables that make simulations extremely fast. IBIS buffer macromodels are commonly applied for system-level SI simulations instead of transistor-level netlists. Simulation time, memory consumption, and convergence issues are all dramatically reduced versus transistor-level simulation. Power-Aware IBIS v5.0 models are used to represent the non ideal power effects. There are two BIRDs related to the power awareness of the IBIS v5.0 models Example IBIS Model Micron EDY4016AABG-DR-F - The first power aware BIRD is 95.6 : Power Integrity Analysis using IBIS - The second power aware BIRD is : Gate Modulation Effect Copyright 2016 Keysight Technologies, All Rights Reserved 103

Power Aware IBIS SI Simulation : Approach-1 SSN analysis with a separate EM simulations for the PDN model and the signal lines The only coupling between the PDN and the Signal lines is through the

104 Power Aware IBIS SI Simulation : Approach-1 SSN analysis with a separate EM simulations for the PDN model and the signal lines The only coupling between the PDN and the Signal lines is through the IBIS model, not the PCB layout. PDN EM S-Parameter Model PI-AC in PIPro Power Aware IBIS DQ Signals S-Parameter Model Power Aware IBIS PI- SI in SIPro Copyright 2016 Keysight Technologies, All Rights Reserved 104

105 Power Aware IBIS SI Simulation : Data Signal (DQ0) with and without PDN impedance attached 0 SI Only Simulation ( no PDN effect) in simulation Power Aware SI Simulation with PDN effects in the simulation Eye Diagram without the effect of the PDN Eye is more open Eye Diagram with PDN ( Power Aware SI) Copyright 2016 Keysight Technologies, All Rights Reserved 105

106 Power Aware IBIS with SI/PI Coupled EM Model : Approach-2 Taking both Power Nets and Signal Nets in a single EM simulation. EM Model with Power and Signal Nets Power Aware IBIS Power Nets Power Aware IBIS Signal Net Copyright 2016 Keysight Technologies, All Rights Reserved 106

Power Aware SI (Approach-2 ): Transient Test Bench Sim Result

Important to Lay the Groundwork for SI and PI Co-Simulation - Start simple and build the complexity It is all about the Load SI only Simulation with added PI Noise ADS SI Pro + Channel Simulation

108 Important to Lay the Groundwork for SI and PI Co-Simulation - Start simple and build the complexity It is all about the Load SI only Simulation with added PI Noise ADS SI Pro + Channel Simulation What the Netlist Doesn t Tell You! SI and PI Co-EM Simulation Crosstalk ADS SI Pro EM Simulation Flat PDN Deisgn Kills the Rogue Wave PI only Simulation with SI Requirements ADS PI Pro + Transient Simulation Simulating the PDN Eco-System Power Aware IBIS SI and PI Co-Simulation ADS PI Pro + SI Pro + Transient Copyright 2016 Keysight Technologies, All Rights Reserved 108

109 Thanks for Sharing Your Time Today It was a pleasure speaking with you today. We hope you found this tutorial session to be helpful and look forward to your feedback so that we can continue to improve our lectures. Want to learn more about Power Integrity? We ll be answering questions and performing simulation demos at the Keysight booth, so feel free to stop by. Feel free to contact Steve at Steve@Picotest.com or through LinkedIn and feel free to join the Picotest LinkedIn Group - Power Integrity for Distributed Systems Copyright 2016 Picotest.com, All Rights Reserved 109

110 Definitions Power Integrity The quality of the power delivered from the supply through the PDN to the loads VRM Voltage Regulator Module - Either a linear or switching regulator, supplies power to a system or load PDN - Power Distribution Network - How power gets from VRMs to ICs Resonance A peak in the PDN impedance profile (impedance vs. frequency) PSRR Power Supply Rejection Ratio Rogue Wave Changes in the power required by the load are not DC, they occur in steps. Those steps can line up and reinforce one another resulting in large voltage excursions on the line ADS Keysight s (formerly Agilent) simulator Noise Budget The voltage deviation as determined by the needs of the loads (usually must be less than the absolute maximum for the ICs being driven but other performance factors (e.g. frequency content) are important too). Noise Budget = DC regulation + Ripple + IRdrop + Step load excursion/startup Overshoot + Noise Gfs The ratio of the change in output current resulting from a change in input voltage Reverse Transfer The change in input current for a change in output current VNA Vector Network Analyzer, used for measuring impedances, s-parameters, gain/phase, Bode plots, non-invasive stability NISM Non-Invasive Stability Measurement, a method of determining the phase margin from an output impedance test FRA Frequency Response Analyzer, used for measuring gain/phase, Bode plots BOL/ EOL Beginning of Life/End of Life Copyright 2016 Picotest.com, All Rights Reserved 110

111 ADS Simulation Workspaces DesignCon 2016 Power Integrity Boot Camp with Hands-On ADS Labs Youtube Video: How to Design for Power Integrity: PDN Rogue Waves Youtube Video: How to Design for Power Integrity: Selecting a VRM Copyright 2016 Picotest.com, All Rights Reserved 111

Power integrity is more than decoupling capacitors The Power Integrity Ecosystem. Keysight HSD Seminar Mastering SI & PI Design

Power integrity is more than decoupling capacitors The Power Integrity Ecosystem Keysight HSD Seminar Mastering SI & PI Design Signal Integrity Power Integrity SI and PI Eco-System Keysight Technologies