Reducing Noise in Power Distribution Networks On time and In Budget

Transcription

1 TITLE Reducing Noise in Power Distribution Networks On time and In Budget Steve Sandler, (Picotest) Image

2 Reducing Noise in Power Distribution Networks On time and In Budget Steve Sandler, (Picotest)

3 So, What is noise

4 And What is a PDN R R1 V_Noise SRC1 L L1 TLIN TL1 SRL SRLC SRLC1 TLIN TL1 SRL1TLIN TL1 SRL SRL1 C C1 SRL SRL1 R R1 C R C1 R1 I_Noise SRC2 I_Noise SRC2 Loads VRM

5 Reverse (S12) A VRM is a Noise Hub Output Impedance (S22) PSRR (S21) Input impedance (S11) Port 1 Iin Vin In Out Rtn Port 2 Iout Vout Output noise/spikes (S22)

6 Know Your Loads What can they tolerate and what can t they tolerate 4E-08 3E-08 Clock Jitter Sensitivity 100uV 50kHz noise=23db degradation s/v 2E-08 1E E E E E+06 Frequency (Hz) Oscillators, sensors, ADCs and DACs are often sensitive to uvs of noise

7 Linear Regulators and LDO s are not the same, though either can have spurs! And Your VRMs 100uV 50kHz noise=23db degradation Switching regulators can modulate generating low frequency noise

8 Set and Maintain Goldilocks Impedance Not too low Not too high Just right CC = LL TR1 ZZ2 dddddddddddddd 6*10 0 2* * f/hz Setting impedance too high results in noise Too low results in resonances or excessive (expensive) capacitance Moving regulators closer to the load reduces L

9 Spend Most of Your Time Evaluating NOT Designing If you selected a clock with high sensitivity at 30kHz (??) don t choose a regulator with high impedance at 30kHz! s/v Clock Jitter Sensitivity 3.5E-08 3E E-08 2E E-08 1E-08 5E E E E E+06 Frequency (Hz)

10 Choose Components Wisely Ceramic is almost always a poor choice so include series resistance options 10mΩ New components are like a box of cracker Jacks SURPRISE INSIDE

11 Consider the Unexpected OOPS happens! Suffers from high Z power At 30kHz Then POWER-SAVER came on

12 Think RF/uWave PCB Simulation is Important Capacitors and PCB s can easily form a resonator Q=4 12dB C603=10nF C603=0nF 20MHz resonance Cause by 10nF cap

13 Troubleshoot Efficiently Two domains are better than one and three are better than 2 Plane Impedance Near Field emissions over plane This 29MHz noise (and EMI) are the result of two capacitors resonating a PCB plane

14 Interrogate your PDN Even if It Looks OK Nobody likes surprises (especially when they occur in the field) A wideband harmonic comb and browser probe can quickly identify PDN soft spots between 1kHz and more than 1GHz

15 Summary 1.Set impedance wisely and keep it flat 2.Spend more time evaluating and less time designing 3.Prepare for the unexpected 4.Troubleshoot efficiently 5.Interrogate to identify weak or sensitive spots Thank You!

16 Thanks for Attending! Steve Sandler has been involved with power system engineering for more than 37 years. Steve is the founder of of PICOTEST.com, a company specializing in accessories for high performance power system and distributed system testing. He frequently lectures and leads workshops internationally on the topics of power, PDN and distributed systems. He is also the other of Power Integrity from McGraw-Hill He was also the recipient of the ACE 2015 Jim Williams Contributor of the Year ACE Award for his outstanding and continuing contributions to the engineering industry and knowledge sharing. Contact me through our LinkedIn group Power Integrity for Distributed Systems or me at Steve@Picotest.com

17 TITLE Reducing Noise in Power Distribution Networks On time and In Budget Tom De Muer Image Keysight Technologies

18 Power Delivery Network Design Board Impedance VRM Capacitors Resonances Board And Capacitor Resonances Courtesy of Xilinx

19 Reducing Noise in Power Distribution Networks On Time Reduce # of spins of board Early insight in design phase by simulation In Budget Reduce part count and part diversity 100uV (BOM) 50kHz noise=23db degradation EDA Tools help Complexity of boards is beyond back of the envelope calculations Effects interact on various scales and often require an EM-based solution Lower barrier for designers to perform PI analysis early in the design cycle

20 EDA Tools are Easier to Use EDA Tools bring a cohesive and performance based flow from board design to analysis and manufacturing to avoid Manual operations and translations between tools as a source of error Time consuming brute-force simulations EDA tools matured over the years 100uV 50kHz noise=23db degradation Bringing together design and various analysis capabilities to more timely and easily verify and predict performance Dedicated (SI and) PI capabilities increase designer s user experience and speak the language of the designer

21 Simulation Capacity has Increased Dramatically Ubiquitous availability of Large amounts of high-speed memory Multi-core processing power Cost of 1 GFlop in 2000 was > 500$, cost in 2015 < 0.08$ Cost of 1 GB in 2000 was > 1500$, cost in 2015 < 8$ Simulators (need to) keep up Prefer parallelization to take advantage of multi-core Can trade an increase memory for boost in performance Use domain expertise in more evolved simulators Exchange performance for accuracy dynamically where acceptable Automatically distribute work to sub-simulators with better characteristics while tracking relevant EM effects across elements of simulations But can we keep up with ever increasing design complexity?

22 TITLE Unachievable Goal: REDUCING NOISE IN POWER DISTRIBUTION NETWORKS ON TIME AND IN BUDGET Image Dan Oh Altera Corporation

23 Basics of PDN Design + _ PCB cap PKG cap On Chip Decap VRM PCB PDN Package PDN Chip PDN (log) Z PDN PCB Bulk Caps PCB SMC Pkg Cap Low-frequency (VRM, Bulkcaps) 10K 500KHz Mid-frequency (PCB,PKG caps) 10M 400MHz High-frequency (ODC, Jitter) (log)

24 PDN Budgeting and Planning Lpkg Power (Max, leakage) Activity Pattern Board PDN Components Vreg Tolerance On-Die Cap (MiMcap, Symbiotic caps) Changes during design cycle Noise Specs Noise spec is derived based on rough estimation or target values

25 PDN Design Challenges Process technology continue to shrink More transistors power increase On-chip decap does not scale as it is a purely proportional to area MIM cap technology improves slowly due to reliability concern Think dielectric layer or new dielectric material is needed to increase cap (C ~ A/d) No improvement in packaging technology from power delivery perspective Ball and bump counts very slowly increase PTH count also does not increase so much PCB decoupling technology remains same The available area to place decaps does not increase

26 How Noise Spec is Used in Design Architecture Definition Noise is translated to voltage corners for IPs Package Inductance Change Decap Density Change Silicon Tapeout Product Release Static Timing Analysis (STA) timing models are generated at the voltage corners (Noise is mapped to DC timing delays in STA IP LIBs) STA performs analysis including DC timing delay caused by noise Power Change An inherent gap between the final noise versus initial spec due to inevitable design changes

27 Potential Solutions Extra noise can be modeled as an equivalent timing margin in the final STA timing closure Timing error due to noise can be significantly reduced if noise frequency is considered FPGA advantages Adequate timing margin can be enforced based on customer design Our DesignCon presentations: WED 9:30AM: impacts of dynamic noise in multi-core or SOC designs TH 2:00PM: chip, package, and pcb co-design methodology to address PDN design challenges for high-performance SOCs and FPGAs

28 Benefits of STAJ Arrival Path Source Destination INBU F PLL Required Path Sensitivity reduction over the frequency modeled (LF) Longer Delay Low frequency reduced Jitter tracking between arrival and required paths (HF) anti-correlation (2 at 0.5*fck) -20dB/dec Conventional STA -3dB point (0.7 at ~0.1*fck)

29 Pessimism Removal Due to Jitter Modeling 267ps using static delay (0.2 tck) 70ps if jitter frequency and tracking is modeled accurately 34mV 108mV

30 TITLE REDUCING NOISE IN POWER DISTRIBUTION NETWORKS ON TIME AND IN BUDGET Image Vishram Pandit Intel Corporation

31 Introduction Noise in Power Distribution Network (PDN) has multiple effects (1) Higher Jitter Logic Failure EMI Coupling to signal lines Typical Noise influencing parameters PDN Network: On-chip capacitance/ package inductance; pkg capacitors; board capacitors/ inductance. Di/dt, Skews/ delays, Power Management Voltage regulators Optimization of PDN Bill of Material (BOM) cost

32 Signaling Impact PDN noise and its impact on system performance (2) Jitter Jitter Tolerance and System Margin PDN Noise coupling to signal lines: (1) (3) (4) Referencing Via placement/ stitching, connectivity Power/ground shapes Capacitors

33 PDN Coupling Effects Coupling criterion: Noise and jitter SoC Coupling effects need to be considered Coupling through silicon and pkg (9) Different types of coupling IP to IP coupling may deteriorate performance of sensitive circuits Various techniques to reduce the coupling Chip/ Pkg/ PCB level isolation Location of different components

34 Improving PDN Designs Power grid impact on the system Power Integrity (5) Symbiotic or intrinsic capacitance (6) Placement of on-chip capacitance Ground current impact (7) Considering power management (6,7) Frequency dependency of noise. (8) Jitter amplification within the building blocks in data path. Protocol based analysis with realistic usage model. Concurrent analysis of the entire I/O interface (clocking, driver, predriver) Simultaneous analysis of different interfaces to evaluate coupling.

35 References 1. Vishram, WH Ryu, MJ Choi, Power Integrity for I/O Interfaces: With Signal Integrity Power Integrity co-design, Prentice Hall, Xiaoping Liu, Mackenzie Scott, Vishram Pandit, Almario F. Delos Angeles, Power delivery noise and its impact on jitter and system margin for multi Gbps high speed serial interfaces, DesignCon Vira Ragavassamy, Jiangqi He, Arul Kandasamy, Y L Li, Vishram Pandit, An efficient Power Integrity design methodology to prevent Platform failures for high density designs, DesignCon M. Wang, WH Ryu, System level impact of stitching vias and capacitors on High Speed Differential Link, ECTC Thao Pham, Vishram S. Pandit, Almario F. Delos Angeles, Power Grid Parasitic Impact on System Level Power Integrity, DesignCon Suzanne Huh, Xiaoping Liu, Vishram Pandit, Supply Noise Simulation and Correlation for a Multi-GHz High- Speed Serial Link, DesignCon Brian Wang, Vishram Pandit, Complete Analysis and Design of Power Integrity for Advanced Memory Technology (DDR4), DesignCon V. Pandit, A. N. Pardiwala, Hsiao-ching Chuang, M. J. Choi, Md. R. Quddus, SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity, DesignCon Brian Wang, Vishram Pandit, Xiaoqing Wang, Aaron Martin, Coupling of Two Power Rails Through Both Package and Silicon, IEEE Chip Packaging Co-Design Workshop, Sep

36 Our DesignCon Presentations 1] Wednesday, January 20 9:20am - 10:00am Manjunath, Prakash, Vishram, Evaluation of PDN Coupling on SoC Room: Ballroom B 2] Thursday, January 21 11:05am - 11:45am Almario, Vishram, Emily, Sriram and Min, Signal and Power Integrity PCB Characterization for Multi GHz High Speed Interface Room: Ballroom GH 3] Thursday, January 21 2:50pm - 3:30pm Brian and Vishram, "What-If' jitter analysis from synthesized realistic PD noise Room: Ballroom A

37 TITLE REDUCING NOISE IN POWER DISTRIBUTION NETWORKS ON TIME AND IN BUDGET Image Antonio Ciccomancini Scogna, Computer Simulation Technology (CST)

38 Importance of Power Delivery Network (PDN) Ensure clean power PDN Signal Integrity EMC Limit

39 Power Distribution Network Bulk caps MB caps DSC Die VRM Motherboard LSC Package The anti-resonance peak occurs at the cross point of package inductance and chip capacitance. This is called chip-package antiresonance.

40 PDN in time domain: design challenges First droop Reducing inductance to package caps (Lpkg) Increasing on-die capacitance (Cdie) Increasing leakage current and reducing the current step in the di/dt profile Second droop Increasing package caps (Cpkg) and reducing inductance to MB caps optimization Third droop Reducing package, socket, and MB resistance Increasing MB caps (CMB) Increasing VR switching frequency to improve VR response

41 Pre-layout PDN optimization example 1GHz in nh mils 20mils 30mils 40mils 50mils mils 20mils 30mils 40mils 50mils

42 Post-layout PDN optimization example DDR2-400 I/O Buffer IBIS PRBS N=7 Maximum voltage overshoot: before: V, and after: V ( same number of decaps, but saving 0.43$/board)

43 SIPI co-extraction SI-PI co-simulation is common practice for simultaneous switching noise (SSN) analysis at system level including PCB, package and die However, SPICE models of the signal nets and the power delivery network (PDN) are usually extracted separately and most of time using different tools, due to different simulation requirements. In our study, a new SI-PI co-extraction methodology is proposed and applied to a DDR3 memory interface. 3D EM full wave simulation is used to capture signal to power coupling and to investigate SSN (#) A NEW SI-PI CO-EXTRACTION METHODOLOGY & HSPICE CO-SIMULATION SIMPLIFICATION FOR A DDR3 MEMORY INTERFACE, THURSDAY JAN 21ST 10.15AM

44 24 lines + power rail Example S-parameters Time domain (FIT) # of unknowns (mesh cells) 104Million Memory usage (RAM) Simulation time 235GB 1days, 2h, 21sec (4 GPU card)

45 Comments o Power Delivery is a System Level problem, therefore a Chip + Package + board co-design is required o Several emerging applications are requiring this o Slow response time to load condition requires to move the regulator close to the load (IVR) o Storage elements (L&C) have large parasitic, embedding them into the package can mitigate the problem o PI and SI influences each other o Thermal management is also critical, partitioning the Power Delivery into several ICs is necessary

46 Time response comparison 4 ohm 1ns

47 PCB/PKG co-design PDN model PCB+PKG

48 TITLE REDUCING NOISE IN POWER DISTRIBUTION NETWORKS ON TIME AND ON BUDGET Image Sam Chitwood Product Engineer Cadence Design Systems, Inc.

49 Simultaneous Switching Noise (SSN / SSO) - Both SI and PI must be considered simultaneously! - SSN is dominated by return path issues - SSN is grossly underestimated with SIonly analysis tools Ideal PDN Minimal SSN predicted Real PDN Actual significant SSN effects

50 Signal Nets and PDN Which Tool to Use? Top Layer Bottom Layer Stack-up

51 Power Integrity and Signal Integrity! solid lines Circuit Analysis and 3DEM Analysis (channels and locally shorted planes, loss, slight impedance mismatch) dashed lines SI/PI Full-package Analysis (channel and full planes, includes power plane resonances) WARNING: A false sense of security is established if only circuit simulation is applied. If 3DEM simulation is later applied as a verification, this sense of security can be falsely reinforced if the full power planes are not included properly in the simulation.

52 DC / IR Drop Analysis Wizard-driven GUI and customizable workflows extremely easy for novice and occasional users Multi-fabric electrical + thermal co-simulation Automatically determine optimum VRM sense line locations for maximum system-level margin Electrical constraint management Power tree setup automation Detailed results and signoff reports

53 Decap Optimization - Impedance vs. Cost Red original impedance Blue optimized impedance at lower cost

54 Add Decaps Intelligently Red No EMI decaps Blue 1 decap Green 3 decaps

55 PI Simulation from Within Layout Tools Enable the whole design process to be completed on time Constraint-driven decap design flow PI Constraint Sets guide PCB designer on decoupling cap placement Integrated DC analysis and design DRC markers resulting from analysis annotated to the layout Cross-probing between layout design and analysis results Decap back-annotation from simulation results to layout env. Batch mode to run analysis engine reduces the complexity of tools, more focus on problems Reuse analysis setup from PI expert What if Layout Engineers could do basic PI analysis? PI Experts could then focus on the fun simulations

56 Thank you! --- QUESTIONS?