Electromagnetic Analysis and Verification of Probe Card Performance for First Pass System Success

Transcription

1 San Diego, CA Electromagnetic Analysis and Verification of Probe Card Performance for First Pass System Success Cristian Gozzi Application Engineer Manager

2 Introduction Today in Multi Probe wafer level, test is increasing with highly needed frequency capability demands: RF ICs Wafer sort (WLAN, Bluetooth, GPS, WiMax etc.) Final Test capabilities at EWS (multi Gigabit x second channel) Known Good Dice (KGD) New high speed ATE platform are already in the market This creates new and exciting ii challenges hll for Probe Card development IEEE SW Test Workshop 2

3 Objective Probe Card lead time becomes the main challenges for high frequency design: An example could be 5 6 working weeks for vertical PC This means a very short time window for Probe Card design (usually no more than 2 weeks) There is not enough time for prototyping and lab test/debug: Directly deliver good and full functional PC to customer The goal of this presentation is to show the usage of HF Simulation Methodology for addressing all design issues prior to manufacture Probe Card IEEE SW Test Workshop 3

4 Agenda Probe Card Design Flow for high speed performance Step by step Signal Integrity Analysis and simulation exampleson Probe Card system Step by step Power Integrity Analysis and simulation examples on Probe Card system High Frequency Probe Card example IEEE SW Test Workshop 4

5 Wafer DIE: Many HF Standard

6 Standard High Speed Data Rate Standard PCI Express 25/ / 8 USB Data Rate (GT/s) RapidIO 1.25 / 2.5 / / 5 / 6.25 DDR / 2133 HDMI 10.2 DisplayPort 1.62 / 2.7 / 5.4 InfiniBand 2.5 / 5 / 10 / / Serial ATA 1.5 / 3 / 6 Serial Attached SCSI 15/ / 6 Fibre Channel / / 4.25 / 8.5 / / GT/s Giga Transfer per Second raw bit rate (i.e. including balance bits due to 8B/10B encoding) IEEE SW Test Workshop 6

7 EWS System: Many Interconnections High speed test card Tx Coaxial cable Pogo Tower Clean, open, logical 1 & 0 at launch from transmitter + - Wafer DUT + - Rcv Load Board ATE SYSTEM + Needles Probe Head Probe Card PCB Logical 1 & 0 hard to t distinguish di ti i h att end interconnects; CLOSED EYE - PROBE CARD SYSTEM IEEE SW Test Workshop 7

8 Traditional PC Design Flow Layout Tool: Cadence, Mentor, Zuken, Altium PC manufacturing f t i EWS pass test? Drawbacks Money for PC re build Time for building them CUSTOMER CLAIMS Start again IEEE SW Test Workshop 8

9 High Frequency PC Design Flow Layout Tool: Cadence, Mentor, Zuken, Altium Virtual Prototype: Field Solver + Circuit Simulator Simulation: Fit Specs? Benefits No prototypes Save time and money Choose your strategy and e y itt by ssimulation u at o verify IEEE SW Test Workshop 9

10 HF PC Design Flow Requirements Design challenges to take into account during Probe Card development: Low voltage, high current Power Delivery System (PDS): Need to accurately control Power Integrity High frequency, high speed analog and digital signals: Need to accurately control Signal Integrity IEEE SW Test Workshop 10

11 Signal Integrity Check List Stackup analysis and Impedance control Frequency Domainanalysis analysis (Linear Network Analysis): Insertion Loss (IL), Return loss (RL), Coupling (X talk), Bandwidth performance ( 1dB; 3dB) Time Domain analysis (Transient analysis): TDR/TDT, rise/fall time, overshoot/undershoot, VIL/VOHmargin margin, ringing etc. Cross Talk analysis: Near End Xtalk (NEXT), Far End Xtalk (FEXT), noise from multiple aggressor SSNO analysis (Simultaneous Switching Noise Output ) EYE diagrams, BER, Jitter, Skew etc. IEEE SW Test Workshop 11

12 Power Integrity Check List Verify noise margin: IR Drop (DC) Power Plane impedance profile vs frequency (AC) Current distribution: High density current, bottleneck hot/heat source Decoupling capacitor solutions, tuning and optimization: Decoupling capacitor configuration, number of components, placement location, mounting effect, parasitic effect (ESR,ESL) Resonance modes: Identify location and frequency of natural cavity resonances thatexist between planes (power and ground bouncing) IEEE SW Test Workshop 12

13 Which ElectroMagnetic Simulator? 3D Electromagnetic Field Solver E Need to accurately characterize and optimize p 3D interconnections ((needles, connectors, VIAs etc.) Solve the full Maxwell s Equations on each mesh element (FEM) Rigorous and accurate approach, but cannot be used for PDS characterization B t H J D t D B 0 2.5D Electromagnetic Field Solver Need to accurately characterize and optimize PCB power delivery system (impedance/inductance, decoupling capacitors etc.) Hybrid solver technologies is used for speed up simulation and characterize full PCB IEEE SW Test Workshop 13

14 ACTIVE LOAD CL AM P ACTIVE LOAD CL AM P ACTIVE LOAD CL AM P ACTIVE LOAD CL AM P ACTIVE LOAD CL AM P ACTIVE LOAD CL AM P ACTIVE LOAD CL AM P ACTIVE LOAD CL AM P ACTIVE LOAD CL AM P ACTIVE LOAD CL AM P V Circuit Environment: Simulate Entire EWS System POGO TESTER - ACTIVE LOADS LOAD PE POGO DQ5_PC LOAD PE POGO DQ0_PC EM Models S Parameters DUT - ACTIVE DRIVERS VCCQ_DUT VCCQ_DUT COMP DRIVER DRVIN DQ5_LOAD COMP DRIVER DRVIN DQ0_LOAD DQ0_DUT V192 DQ5_DUT V COMP COMP COMP DRIVER DRVIN DRIVER DRVIN DRIVER DRVIN LOAD PE DQ6_LOAD LOAD PE DQ7_LOAD LOAD PE DQ8_LOAD POGO POGO POGO DQ6_PC DQ7_PC DQ8_PC COMP COMP COMP DRIVER DRVIN DRIVER DRVIN DRIVER DRVIN LOAD LOAD LOAD PE DQ1_LOAD PE DQ2_LOAD PE DQ3_LOAD POGO POGO POGO DQ1_PC DQ2_PC DQ3_PC CH23_71_J47 DQ9_PC CH49_71_J47 DQ0_PC CH50_71_J47 DQ1_PC CH51_71_J47 DQ2_PC CH52_71_J47 DQ3_PC CH53_71_J47 DQ4_PC CH54_71_J47 DQ5_PC CH55_71_J47 DQ6_PC CH56_71_J47 DQ7_PC CH99_71_J47 DQ8_PC PPS1F_71_J47 VCCA_PC PPS2F_71_J47 VCCQ_PC Load Board CH23_71_GOMM24 CH49_71_GOMM24 CH50_71_GOMM24 CH51_71_GOMM24 CH52_71_GOMM24 CH53_71_GOMM24 CH54_71_GOMM24 CH55_71_GOMM24 CH56_71_GOMM24 CH99_71_GOMM24 GOMM24_PPS1F_71_Group GOMM24_PPS2F_71_Group R85 30mOhm L87 60nH V84 INTERPOSER CH23_71_GOMM24 CH23_71_INT-1 DQ9_DUT CH49_71_GOMM24 CH49_71_INT-1 DQ0_DUT CH50_71_GOMM24 CH50_71_INT-1 DQ1_DUT CH51_71_GOMM24 CH51_71_INT-1 DQ2_DUT CH52_71_GOMM24 CH52_71_INT-1 DQ3_DUT CH53_71_GOMM24 CH53_71_INT-1 DQ4_DUT CH54_71_GOMM24 CH54_71_INT-1 DQ5_DUT CH55_71_GOMM24 CH55_71_INT-1 DQ6_DUT CH56_71_GOMM24 CH56_71_INT-1 DQ7_DUT CH99_71_GOMM24 CH99_71_INT-1 GOMM24_PPS1F_71_Group DQ8_DUT INT-1_PPS1F_71_Group VCCA_DUT GOMM24_PPS2F_71_Group INT-1_PPS2F_71_Group VCCQ_DUT L88 R86 VCCQ_PC 4nH 4mOhm DQ1_DUT DQ2_DUT DQ3_DUT VCCQ_DUT VCCQ_DUT VCCQ_ DUT VCCQ_DUT 0 DQ6_DUT V DQ7_DUT V DQ8_DUT V200 0 VCCQ_DUT VCCQ_DUT VCCQ_ DUT VCCQ_DUT 0 V203 0 V204 0 V205 0 LOAD PE POGO DQ9_PC LOAD PE POGO DQ4_PC 0 DC=1.8V DQ4_DUT DQ9_DUT COMP DRIVER DRVIN DQ9_LOAD COMP DRIVER DRVIN DQ4_LOAD ATE model DUT models: IBIS or SPICE V V206 IEEE SW Test Workshop 14

15 Agenda Probe Card Design Flow for high speed performance Step by step Signal Integrity Analysis and simulation exampleson Probe Card system Step by step Power Integrity Analysis and simulation examples on Probe Card system High Frequency Probe Card example IEEE SW Test Workshop 15

16 Signal Integrity: STEP #1 Needle Characterization bad good RETURN LOSS (Reflection Coefficient) IEEE SW Test Workshop 16

17 Signal Integrity: STEP #2 Needle Performance Optimization bd bad good Bandwidth improvment: from 200MHz to 1GHz Before After RETURN LOSS (Reflection Coefficient) 17

18 Signal Integrity: STEP #3 PCB Stackup Analysis and Controlled Impedance Differential Pair Target Zo=100Ohm IEEE SW Test Workshop 18

19 Signal Integrity: STEP #4 PCB Interconnection Optimization VIA stub impact: Routing Analysis Layer #5 vs Layer #9 IEEE SW Test Workshop 19

20 Signal Integrity: STEP #5 Cross Talk Analysis IEEE SW Test Workshop 20

21 Signal Integrity: STEP #6 TDR Analysis Impedance Improvement 21

22 Signal Integrity: STEP #6 EYE Analysis Gigabit Channel Improvement Eye source pattern PRBS15 with 8b10bEncoding, 80ps rise/fall time, 5 Gbps of Datarate, 2 Vpp and 100 Ohm differential load at Pogo pads IEEE SW Test Workshop 22

23 Agenda Probe Card Design Flow for high speed performance Step by step Signal Integrity Analysis and simulation exampleson Probe Card system Step by step Power Integrity Analysis and simulation examples on Probe Card system High Frequency Probe Card example IEEE SW Test Workshop 23

24 Power Integrity: STEP #1 Check DC PDS Specification What is the best DC PDS performance? Devices see voltage closet to nominal voltage Low IR drop Well balanced DC voltages among devices on the same rail Low Temperature Rise on Metal Low Current Density IEEE SW Test Workshop 24

25 DC Power Delivery System Simulation VDD Core Voltage Drop DC IR Analysis VDD Core Current Distribution High current density - bottleneck 30mV drop

26 Power Integrity: STEP #2 Check AC PDS Specification What is the best AC PDS performance? Low noise Low loop inductance Low and Flat impedance What are the PDS design issues? Number of Caps, location/placement l t Number of Vias, signals routing issue Component mounting effect PCB plane location/stack up Interposer effect V Noise PWR % ZTarget Current IEEE SW Test Workshop 26

27 Power Delivery System Topology IEEE SW Test Workshop 27

28 AC Power Delivery System Simulation Impedance vs Frequency Analysis di VN L dt VN Z I SYZ Sweep 1 PWR Impedance Technoprobe INTERPOSER_PC_ Curve Info Mag(Z(INT-1_PPS1F_71_Group,INT-1_PPS1F_71_Group)) SYZ Sw eep 1 Mag(Z(INT-1_PPS2F_71_Group,INT-1_PPS2F_71_Group)) SYZ Sw eep 1 m2 m3 Name m1 X Y m m2 m Z Mag [Ohm] TARGET IMPEDANCE Compute Power Plane Self Impedance Z(f) 1.00 VCCQ VCC 0.10 P k Impedance Peaks I 250MHz, 250MH 340MH 340MHz and d 410MH 410MHz Freq [MHz] IEEE SW Test Workshop

29 AC Power Delivery System Simulation Resonance Modes Analysis PWR plane bouncing below DUT High Impedance hot spot area Decaps are mounted in this area: too far away from DUT VCCQ Resonant 250MHz IEEE SW Test Workshop 29

30 AC Power Delivery System Simulation Wide DQ BUS causes SSN/SSO (power and ground bounce, AC drop) Simultaneous Switching Noise (SSN) Technoprobe POWER Switching Noise 2.40 m m2 t=4ns Curve Inf o V(VCCQ_DUT) Transient Allowed AC ripple noise V(VCCQ_DUT) [V] Name X Y m m Name Delta(X) Delta(Y) Slope(Y) InvSlope(Y) d(m1,m Time [ns] VCCQ VCC Fres=1/ t=250mhz 30

31 Power Integrity: STEP #3 Optimize Decoupling Capacitors Decoupling caps p p g capacitor? p Whyy optimize arrayy decoupling Chose the right number of decoupling capacitors to meet Ztarget Save space for signals routing, reduce design constrains and effort Chose the right package size, size value and mounting footprint Minimize mounting inductance, improve PWR impedance profile vs frequency IEEE SW Test Workshop 31

32 Decoupling Capacitor Selection Why use only classic 10nF, 100nF? Select the right capacitor values and package from Cap Vendor s library to obtain the best PWR Impedance profile vs Frequency MOUNTING DESIGN PACKAGE SIZE 32

33 Decaps Reduction Same Impedance Performance Reduced number off capacitors it IEEE SW Test Workshop 33

34 Agenda Probe Card Design Flow for high speed performance Step by step Signal Integrity Analysis and simulation exampleson Probe Card system Step by step Power Integrity Analysis and simulation examples on Probe Card system High Frequency Probe Card example IEEE SW Test Workshop 34

35 HF Cantilever Probe Card for RF Wafer Sort Suitable forwireless RF front end wafer sort solution: Bluetooth (2.4 GHz) b/g/n (2.4GHz) y (3.7GHz) ac (<6GHz) WiMAX (2.3 GHz, GHz, GHz) Etc. IEEE SW Test Workshop 35

36 VNA Measurement FIRST PASS SYSTEM SUCCESS GOOD Performance up to 6GHz IEEE SW Test Workshop 36

37 SUMMARY Many high frequency standards are present in the market today, this require new methodology for Probe Card Design Usage of complete simulation environment allow Engineers to accurate check bothsignal and Power Integrity A step by step approach has been shown The speed up and accuracy of Electromagnetic Simulator, combined with Circuit Environment, allow to control ENTIRE EWS SYSTEM and Probe Card performance prior to manufacture FIRST PASS SYSTEM SUCCESS IEEE SW Test Workshop 37

38 Acknowledgment Thanks to Massimo Capodiferro (Ansoft Italy) for his support duringrecentrecent years on simulation setup/check Thanks to Flavio Maggioni (Technoprobe Italy) for his valuablecontribute on high frequency PCB design Future Works Continuous R&D simulation effort for improving high frequency PC performance and extend production of HF and KGD PC IEEE SW Test Workshop 38

39 Questions and Answers Q IEEE SW Test Workshop 39