3D IC-Package-Board Co-analysis using 3D EM Simulation for Mobile Applications

Transcription

1 3D IC-Package-Board Co-analysis using 3D EM Simulation for Mobile Applications Darryl Kostka, CST of America Taigon Song and Sung Kyu Lim, Georgia Institute of Technology Outline Introduction TSV Array Cross Talk Analysis Return Path Discontinuity Modeling 2.5D Link Analysis 3D IC Link Analysis Conclusion 1

2 Introduction to 3D Integration System-on- Chip (SoC) System-in- Package (SiP) Source: Cadence Design Systems, Inc. 3D ICs with TSVs Design Challenges and Requirements 2.5D Stacking 3D IC TSV Signal-Ground Pair Insertion Loss (db) D=100μm, R=15μm, L=100μm, d ox =0.1μm, ε SiO2 =3.9 (tand=0.001), ε Si =11.9 (cond=10s/m) Sharp slope due to transition from slow wave to quasi-tem mode Losses due to displacement currents in Si 2

3 Cross Talk: TSV Array Aggressor via Neighboring Victim via Shielded Victim via Return vias Victim vias Baseline: D=100μm, R=10μm, L=200μm, d ox =1μm, ε SiO2 =3.9 (0.001), ε Si =11.9 (10S/m) 5x5 TSV array with 1 driven aggressor and two victim vias; Aggressor (TSV1) is driven with a pulse (risetime=100ps, amplitude=2v) using a 50Ohm source resistor. Far end of aggressor TSV and both sides of all other signal TSVs are terminated in 50Ohms Cross Talk: TSV Array NEXT Frequency domain NEXT Time domain Neighboring victim Shielded victim Thicker oxide liners help reduce cross talk for low resistivity substrates High resistivity substrates act as low loss dielectrics and therefore help reduce cross talk Low resistivity substrate has a larger peak voltage and longer coupled noise duration (ISI) Chip-package co-design since TSV response in the chip stack can propagate into package 3

4 Interposer: Return Path Discontinuities Surface current distribution showing cavity resonance Microstrip-to-microstrip transition causes a change in the reference plane (RPD) Results in large SSN voltage induced between planes at resonance frequencies Increased insertion loss Eye Diagrams for Silicon and Glass Interposers Glass 3.2 Gbps PRBS stream Silicon 17.89p s 282.6p s 0.29V 6.7ps 295.2p s 0.31V Jitter and eye opening are considerably improved in the Silicon interposer, in comparison with the Glass interposer Performance of glass interposer can be improved by using decoupling capacitors 4

5 2.5D Link Test Case Signal Signal Die size: 1 mm x 1 mm, 250 um thickness (Die 1 is identical to Die 2) Double Sided Silicon Interposer size: 40 mm x 40 mm, 300 um thickness u-bump dimensions: 60 um diameter, 52 um height, 200 um pitch TPV dimensions: 40 um diameter, 300 um height, 200 um pitch IC Design I/O Pad Map Silicon IC BEOL M1 GDSII Import from Cadence Virtuoso M10 u-bump NCSU FreePDK 45nm technology library 10 metal layers, 12um thick Cu backend 11 signals total 5

6 Double Sided Silicon Interposer Design Interposer IC 1 IC 2 20mm 40mm Microstrip-to-microstrip signal routing used to maximize RPD effects (worst case scenario) (Eps = 2.51, tand = 0.004) 2.5D Link: Analysis Methodology I Method 1: Complete chip-interposer-chip link co-simulation Pos: Highest level of accuracy since all 3D coupling effects between the ICs and interposer are captured Neg: Not computationally feasible (3D full-wave analysis) due to the complexity of the IC design and the aspect ratios involved 6

7 2.5D Link: Analysis Methodology II Method 2: Decoupling / Cascading approach Reference Plane Center of the u-bump array is used as the reference plane (electric wall) All signal, power and ground nets need to be terminated to maintain return current path continuity Electric Wall used as Discrete Port Reference port + Electric Wall used as Discrete Port Reference S-parameters (Die 1) S-parameters (Interposer) S-parameters (Die 2) 2.5D Link: Analysis Methodology II IC PEC sheet reference Interposer PEC sheet reference 7

8 2.5D Link: Analysis Methodology III Method 2: Decoupling / Cascading approach Reference Plane Reference Plane The reference plane is selected along a uniform section of the signal traces to ensure TEM propagation mode. Excitation Port Definition Die 1 Die 2 Port 5 Port 7 Port 1 Port 2 Port 3 Port 4 Port 6 Port 8 Die 1 and Die 2 are identical 8

9 IC: Surface Current Distribution 100 MHz 2 GHz Signal Excitation Port Signal Excitation Port Coupling to surrounding (non neighboring) nets can be observed at higher frequencies S-Parameter Results Port 5 Port 7 Port 1 Port 3 RL Port 2 Port 4 Port 6 Port 8 IL For the fewer pins case, only the PWR/GND pins neighboring the signal pins were included Results demonstrate that good correlation can be achieved provided the return current path continuity is preserved NEXT FEXT 9

10 3D IC Link Test Case Signal Signal Die size: 1 mm x 1 mm, 250 um thickness Tier 3 = Signal I/Os, PDN distributed between Tier 2 and Tier 1 Double Sided Silicon Interposer size: 40 mm x 40 mm, 300 um thickness u-bump: 36 um diameter, 200 um pitch flip-chip bump: 60um diameter TSV: 12 um diameter, 50 um height TPV: 40 um diameter, 300 um height 3D IC Link: Analysis Methodology Method A Full 3D link Method B Method C Center of the u-bump and flip-chip bump arrays are used for the reference plane locations All signal, power and ground nets are terminated to maintain return current path continuity 10

11 S-Parameter Results IL RL Stronger coupling between TSV s is observed in 3D IC s and therefore using a decoupling simulation strategy provides inaccurate results especially for cross talk. NEXT FEXT Conclusion Demonstrated 3D full-wave electromagnetic analysis of a chip to chip channel using a simple IC (few I/O s) and Si interposer prototype TSV s demonstrate high levels of cross talk due to the conductive Silicon substrate For 2.5D applications, it is possible to decouple the IC from the interposer and obtain accurate results up to around 20 GHz For 3D IC applications, the strong coupling between the TSV s in the IC stack makes it impossible to perform a decoupled analysis 11