Power Plane and Decoupling Optimization. Isaac Waldron

Transcription

1 Power Plane and Decoupling Optimization p Isaac Waldron

2 Overview Frequency- and time-domain power distribution system specifications Decoupling design example Bare board Added d capacitors Buried Capacitance Conclusion

3 Frequency Domain PDS Targets Excessive impedance seen by a device drawing power from a PDS will cause power voltage to fluctuate On a board, impedance must be below target from DC to several hundred MHz Working in the frequency domain allows quick estimation of power quality Mag. of Z Z target Z f

4 PDS Components Mag. of Z Z target Z f 1KHz 1MHz 100MHz 1GHz Switching Power Supply Electrolytic Bulk Capacitors High Frequency Ceramic Capacitors Power/Ground Planes Buried Capacitance

5 Time Domain PDS Targets S-parameters and impedance are calculated in the frequency domain Device specifications are typically given in the time domain Example: maximum VCC excursion 10% of nominal value 1.8 V VCC has an allowable range of 1.62 V to 1.98 V

6 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

7 Board Imported from Layout Measuring impedance at the six VCC pins on U41

8 Defining the Target Impedance Package Model C58 Cpkg L59 Lpkg R60 0 Rpkg VRM V35 VRM pullup logic_in io enable out_of_in pulldown 0 Driver R5 50 VRM VR RM A Name=vrm V33 DC=VCC 0 To define the target impedance we need to consider two factors: Peak current Determines maximum impedance Spectral power Determines cutoff frequency

9 Peak Current Peak current ma Six drivers and 0.18 V maximum voltage swing: Ansoft Corporation Driver Current Curve Info mag(ipositive(vrm)) se max Driver V ( ma) = 800 mω mag(ipos sitive(vrm)) [ma] Time [ns]

10 Driver Spectrum 95% of driver power is Ansoft Corporation 1.00E-003 below 667 MHz 1.00E-004 XY Plot MHz MHz Curve Info mag(vrm_pow er) Driver 1.00E E-006 rm_power) mag(v 1.00E E E E E E Spectrum [GHz]

11 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

12 Bare Board Target impedance 800 mohm to 667 MHz Bare Board

13 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

14 Time Domain Schematic C58 Cpkg L59 Lpkg R60 0 Rpkg VCC C_U41-2 Di Driver V35 logic_in enable VCC C_U41-2 pullup io out_of_in pulldown 0 R5 50 x6 VCC_U41-2 VCC_U41-21 VCC_U41-42 VCC_U41-2 VCC_U41-21 VCC_U41-42 J5_VC CC J5_VCC C VCC_U41-44 VCC_U41-63 VCC_U41-84 Board VCC_U41-44 VCC_U41-63 VCC_U41-84 J5_VCC 800 Mbps data rate VRM V33 DDR2 IBIS driver into ideal termination used as load for PDS DC=VCC 0 Package decoupling modeled using a capacitor w/ ESR, ESL

15 Switching Power Noise Ansoft Corporation 2.40 U41 Power Curve Info pk2pk Bare V(VCC_U41-2) V(VCC_U41-21) V(VCC_U41-42) V(VCC_U41-44) V(VCC_U41-63) Y1 [V] 1.80 V(VCC_U41-84) Shaded area represents time domain specification 1.8 V ± 10% Time [ns]

16 Spectral Analysis Ansoft Corporation 2.40 Y1 [V] Y U41 Power ~11-12 ns period Curve Info V(VCC_U41-2) V(VCC_U41-21) V(VCC_U41-42) V(VCC_U41-44) V(VCC_U41-63) V(VCC_U41-84) pk2pk Bare Ansoft Corporation Time [ns] m ns period corresponds to frequency of MHz This is confirmed by the spectral plot and correlates with the ideal driver simulation ua shown earlier e 83 MHz) Spectral Name 90 X MHz Y m m Curve Info db(v(vcc_u41-2)) db(v(vcc_u41-21)) db(v(vcc_u41-42)) db(v(vcc_u41-44)) Bare m2 db(v(vcc_u41-63)) Y db(v(vcc_u41-84)) Spectrum [MHz]

17 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

18 Adding Bulk Capacitors Added two 47 uf capacitors as specified by VRM manufacturer

19 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

20 Bare Board vs. Bulk Capacitors Target impedance 800 mohm to 667 MHz 50 MHz Bare Board Board w/ Bulk Caps

21 Bulk Capacitors Target impedance 800 mohm to 667 MHz 50 MHz Board w/ Bulk Caps

22 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

23 Switching Power Noise Ansoft Corporation 2.40 U41 Power ~ ns period Curve Info V(VCC_U41-2) Bulk pk2pk V(VCC_U41-21) V(VCC_U41-42) V(VCC_U41-44) V(VCC_U41-63) Y1 [V] 1.80 V(VCC_U41-84) Shaded area represents time domain specification 1.8 V ± 10% Time [ns]

24 Spectral Analysis Ansoft Corporation U41 Power ~11-12 ns period Curve Info V(VCC_U41-2) V(VCC_U41-21) V(VCC_U41-42) Bulk pk2pk Same ns period as exhibited by bare board 2.00 V(VCC_U41-44) V(VCC_U41-63) Y1 [V] 1.80 V(VCC_U41-84) Ansoft Corporation Time [ns] m1 Spectral MHz Name X Y m1 MHz m Bulk Curve Info db(v(vcc_u41-2)) db(v(vcc_u41-21)) db(v(vcc_u41-42)) 42)) db(v(vcc_u41-44)) db(v(vcc_u41-63)) db(v(vcc_u41-84)) Note that 50 MHz is not excited due as indicated by low spectral content at that frequency Y m Spectrum [MHz]

25 Resonance at 50 MHz U41

26 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

27 Choosing a Capacitor To reduce the effect of a resonance, choose a capacitor with a low impedance at the resonant frequency 22 nf Capacitor Board w/ Bulk Caps

28 Added HF Capacitors nf capacitors were added across the board to reduce high-frequency impedance and to cancel resonance at 50 MHz

29 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

30 Bulk vs. HF Capacitors 1 Target impedance 800 mohm to 667 MHz Board w/ Bulk Caps Board w/ HF Caps 1 No 50 MHz

31 HF Capacitors 1 Target impedance 800 mohm to 667 MHz Exceeds MHz Board w/ HF Caps 1 No 50 MHz

32 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

33 Switching Power Noise Ansoft Corporation 2.40 U41 Power Curve Info pk2pk HF1 V(VCC_U41-2) V(VCC_U41-21) V(VCC_U41-42) V(VCC_U41-44) V(VCC_U41-63) Y1 [V] 1.80 V(VCC_U41-84) Shaded area represents time domain specification 1.8 V ± 10% Time [ns]

34 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

35 Extending Low Impedance nf capacitors were added across the board to extend minimum highfrequency impedance 12nF 1.2 capacitor was chosen due to low impedance at 200 MHz 4 of these were located near U41 Added capacitors

36 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

37 HF 1 vs. HF 2 Target impedance 800 New 80 MHz mohm to 667 MHz Board w/ HF Caps 1 Board w/ HF Caps 2 Impedance exceeds MHz

38 HF 2 Target impedance 800 New 80 MHz mohm to 667 MHz Board w/ HF Caps 2 Impedance exceeds MHz

39 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

40 Switching Power Noise Ansoft Corporation 2.40 U41 Power Curve Info pk2pk HF2 V(VCC_U41-2) V(VCC_U41-21) V(VCC_U41-42) V(VCC_U41-44) V(VCC_U41-63) Y1 [V] 1.80 V(VCC_U41-84) Shaded area represents time domain specification 1.8 V ± 10% Time [ns]

41 Resonance at 80 MHz U41

42 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

43 Removing a Resonance Added capacitors Six 8 nf capacitors were added near U41 to cancel resonance at 80 MHz

44 Choosing a Capacitor To reduce the effect of a resonance, choose a capacitor with a low impedance at the resonant frequency 82nF 8.2 Capacitor Board w/ HF Caps 2

45 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

46 HF 2 vs. HF 3 Target impedance 800 mohm to 667 MHz Board w/ HF Caps 2 Board w/ HF Caps 3 No 80 MHz Impedance crosses MHz

47 HF 3 Target impedance 800 mohm to 667 MHz Board w/ HF Caps 3

48 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

49 Switching Power Noise Ansoft Corporation 2.40 U41 Power Curve Info pk2pk Final V(VCC_U41-2) Maximum peak to peak noise of 371 mv V(VCC_U41-21) V(VCC_U41-42) V(VCC_U41-44) V(VCC_U41-63) Y1 [V] 1.80 V(VCC_U41-84) Shaded area represents time domain specification 1.8 V ± 10% Time [ns]

50 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

51 Buried Capacitance Due to parasitic inductance it will be impossible to further decouple the board with capacitors Using a thinner dielectric layer between power and ground planes introduces additional capacitance and reduces high frequency impedance Capacitance of parallel plates: C A = ε d

52 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

53 HF 3 vs. Buried Capacitance Target impedance 800 mohm to 667 MHz Board w/ HF Caps 3 Board w/ Buried Capacitance Impedance crosses 800 >667 MHz

54 Buried Capacitance Target impedance 800 mohm to 667 MHz Target impedance specification met Board w/ Buried Capacitance

55 PDS Design Flow EM extraction of impedance for critical devices Determine frequencies of specification Simulate in time domain to check for compliance Choose capacitor or geometric change to address Alter design according to findings

56 Switching Power Noise Ansoft Corporation 2.40 U41 Power Curve Info pk2pk Buried V(VCC_U41-2) Maximum peak to peak noise 273 mv 24% smaller than limit V(VCC_U41-21) V(VCC_U41-42) V(VCC_U41-44) V(VCC_U41-63) Y1 [V] 1.80 V(VCC_U41-84) Time-domain noise specification met Shaded area represents time domain specification 1.8 V ± 10% Time [ns]

57 Conclusion Ansoft software allows PCB engineers to design effective decoupling solutions for their PCBs Impedance and resonant mode simulations connect the frequency domain to the spatial domain and allow selection of capacitor value and placement Frequency domain extractions are useful for quickly optimizing PDS designs, but time domain simulations are necessary to ensure compliance with device specs