Design, Modeling and Characterization of Embedded Capacitor Networks for Mid-frequency Decoupling in Semiconductor Systems

Transcription

1 Design, Modeling and Characterization of Embedded Capacitor Networks for Mid-frequency Decoupling in Semiconductor Systems Prathap Muthana, Madhavan Swaminathan, Rao Tummala, P.Markondeya Raj, Ege Engin,Lixi Wan, Devarajan Balaraman, Swapan Bhattacharya Packaging Research Center, Georgia Institute of Technology Atlanta, USA Abstract Embedded passives are gaining in importance due to the reduction in size of consumer electronic products. Among the passives, capacitors pose the biggest challenge due to the large capacitance required for decoupling high performance circuits. This paper focuses on the characterization and modeling of embedded capacitors. Design and modeling of embedded capacitor networks for decoupling semiconductor systems in the mid-frequency band (100 MHz to GHz) will be highlighted in this paper. Keywords-Embedded capacitors, modeling, characterization midband frequency, decoupling. I. INTRODUCTION Embedded passives are gradually replacing discrete passives due to the miniaturization of electronic products. Integration of these passives within the package increases the real estate for active components. This would increase the functionality of the system. Capacitors pose the biggest challenge for integration due to the high value of capacitances required for decoupling semiconductor systems. Decoupling in today s systems is achieved by using discrete surface mount capacitors. The effectiveness of these capacitors is reduced beyond 100 MHz because of the high inductances associated with the leads of the capacitors. Embedded capacitors overcome this drawback because of the low inductances and high capacitance associated with them. Embedded capacitor performance in boards and power ground planes in packages has been investigated in [1,]. This paper will highlight the performance of discrete thin film embedded capacitor s in packages to provide decoupling in the mid frequency bandwidth of 100MHz to GHz in order to meet the required target impedance for future processors. This paper is organized as follows- Section deals with the processor requirements in terms of power dissipation, core voltage, current and target impedance for the 65nm technology node. The modeling and characterization process of the embedded capacitors along with the package requirements is described in Section 3. II. PROCESSOR REQUIREMENTS Microprocessor power densities have grown over the technology nodes due to the increase in the number of transistors and increase in the processor operating frequency. The major contributors to the power dissipation in the sub 100nm node are active and static power dissipation. The power dissipation for future cost performance processors is expected to be close to 450W by the end of the decade. Such high value of power dissipation would not be acceptable for single chip package solutions. A method of reducing the power dissipation and improving the performance of single core processors is by using a multi-core approach [3]. A major challenge for future technology nodes is to keep the impedance of the power distribution network (PDN) as seen by the processor less than the target impedance over a frequency bandwidth. The target impedance must be met at all frequencies where current transients exist. This frequency band extends from the lower khz s to the chip operating frequency depending on the processor function. These operations could involve data transfer to and from the hard disk, data transfer to and from the DRAM or on chip processing. Due to the fast switching speed of circuits which results in sudden current demands, noise is generated that can hinder performance. A major source of this noise is due to the power distribution system of the package and the board, which if poorly designed can result in ground bounce. One methodology to reduce noise it to design the PDN by identifying a target impedance, which has to be met over a broad frequency range. The target impedance is a function of the current and the core voltage of the processor and is given by Z TARGET V 0.05 = I 50% Where V is the core voltage of the processor and I is the current used by the processor. The target impedance for a single chip package was calculated based on the power dissipation numbers for a high performance logic- cost performance processor as listed in the ITRS. The table below compares the target impedance values calculated by using the methodology in [3] for a single and multicore processor with the numbers given in the ITRS for the 65nm node. The above table lists the advantage of a multi-core processor from a power and target impedance perspective. An integral part of the PDN is the decoupling capacitors which act as reservoirs of charge () /05/$ IEEE. 638

2 TABLE 1: TARGET IMPEDANCE VALUE COMPARISON FOR 65NM NODE 007 Single core Single core Multicore (ITRS) (Analysis) (Analysis) Power 103.6W 61.78W 10W Core Voltage 0.9V 1.1V 1.1V Target 0.7 mohm 0.4mohm 1mohm impedance for the switching circuits. Based on the current demands, decoupling has to be provided in the low frequency (DC to 100MHz), mid band frequency (100MHz to GHz) and high band frequency (GHz onwards) by the proper placement of decoupling capacitors in the power distribution network. The role of embedded decoupling capacitors within a package has been highlighted in this paper. One proposed solution to provide decoupling from within a package is to use a high dielectric material between the power and ground planes of the package. There are a few limitations of this approach; the first one is a large value for the minimum series resistance (ESR). The ESR of the power ground plane may not be as low as the target impedance required by the processor. For a power ground plane pair of thickness 9um and dielectric constant 11, the ESR value is 8.1mohm, which exceeds the calculated target impedance value. The second limitation is the frequency band over which this target impedance can be met by a single power plane structure. This paper highlights a methodology that overcomes the above limitations by using discrete embedded capacitors within the package. Discrete embedded capacitors are capacitive structures that are much smaller in size as compared to the power ground plane of a package. The minimum and maximum sizes of the capacitors are decided by their process ground rules. One advantage is that a large number of these capacitors can be connected in parallel with the power ground plane of the package to reduce the power ground impedance as seen by the processor. The flexibility in size allows the capacitor network to be designed in a manner such that the resonances of the power plane and other capacitors in the package can be suppressed over a frequency range by the introduction of the proper size and value capacitor. The resulting structure is that of a capacitive array in the package that can be designed to keep the impedance of the power ground plane below the target impedance over a given frequency band. Figure 1, shows the cross section of a capacitive network. This capacitor array has levels of discrete capacitors and vias that connect the capacitor network to the power ground plane of the package. The design of capacitor networks as described in Section 3 has been done with the aim of meeting the ITRS roadmap numbers, over the mid band frequency range of 100 MHz to GHz. III. EMBEDDED CAPACITORS A. Materials and Process Details The design of individual embedded capacitors for decoupling is highly dependent on the frequency band under consideration. The most effective design would come from Figure 1. Cross section of a package with discrete capacitor layers both the electrical and materials perspective. The details of the different capacitors that were used in the design of the capacitor decoupling networks are described in this section. The characterized capacitors were thin film Barium titanate (BaTiO 3 ) capacitors, fabricated using a hydrothermal process. These capacitors were fabricated at the Packaging Research Center (PRC). The cross section details of the barium titanate capacitor are given in Figure. Figure. Cross section of thin film barium titanate capacitors In this work, nanograined ultrathin crystalline Barium Titanate thin films were synthesized on laminated copper foils using the low cost low temperature (<100 o C) hydrothermal process. Hydrothermal synthesis of BaTiO 3 involves treating Ti-coated copper clad laminates with Ba + ions in highly alkaline solution at 95 C. With this method high k thin films can be integrated into organic packages using standard Printed Wiring Board processes such as lamination and lithography. The resultant films 300 nm thick exhibited a dielectric constant close to 300, loss less than 0.06 and a capacitance density greater than 1 µf/cm. The size of the grains of the barium titanate varies from 60nm to 80nm. The top electrode is um thick copper and the bottom electrode is 1um copper with 500nm of titanium. The measurement results of a square capacitor 1mm on a side and a circular capacitor with.1mm diameter along with the methodology used in characterizing these capacitors is explained later in part B of this section. B. Characterizaton The characterization of the capacitors was done by using the methodology described in [4]. The equations used for extracting the real and imaginary part of the capacitive structure is given below /05/$ IEEE. 639

3 ( dut) ( Re( S1) ( 1 Re( S1) ) Im( S1) ) ( 1 Re( S1) ) + Im( S1) ) Im( S 1) ( 1 Re( S1) ) + Im( S 1) Re = 5 ( dut ) ( ) Im = 5 () 3 ( ) Re(dut) and Im(dut) are the real and imaginary parts of the capacitive structure respectively. Re(S1) and Im(S1) are the real and imaginary parts of the measured S parameters between port1 and port of the device under test. The above mentioned measurement procedure requires a port VNA probe station. The cross section of a capacitor with the probe placement is shown in the Figure 3. The probes used were 500um Fixed Pitch Compliant(FPC) signal-ground and ground-signal probes. The VNA used was Agilent s 870ES with a bandwidth of 50MHz to 0.5GHz. The probes were calibrated by the standard SOLT calibration method from 50MHz to 3GHz Figure 4. Measurement results of a 1mm X 1mm capacitor Figure 3. Cross section of a capacitor showing the probing methodology Figure 5. Modeled frequency response of 1mm X 1mm capacitor C. Model to hardware corelation The capacitors were modeled by using the Transmission Matrix Method [5]. The model to hardware correlation of the different capacitors is described in this section. The barium Titanate capacitor measurement using the method described above is shown in Figure 4. The measurements were done by placing the 500um pitch GS and SG probes 75um apart from each other. The initial modeling result of the same structure is shown in Figure 5. The structure resonates at 1.3GHz. The capacitance of the structure is 9nF. The equivalent series inductance (ESL) and series resistance (ESR) of the capacitor according to the modeling is 1.85pH and 16.9mohms respectively. As can be seen by comparing the initial model to the measurement, there is a large discrepancy in the results. In order to match the measurement results, the inductance associated due to the probes was extracted from the measurement set up. This was done by placing both the probes on the ground electrode exactly the same distance apart as they were on the DUT. The extracted inductance between the probes is shown in Figure 6. The model was compensated for by defining ports 75 um apart and including the extracted inductance of 37.5pH to the impedance between the ports. The correlation of the hardware to the new model is shown in Figure 7. The capacitance of the structure was extracted and is plotted in Figure 8. The measurement and modeling result of a.1mm diameter circular capacitor is shown in Figure 9 and Figure 10 respectively. The capacitance of the structure is 7.9nF and the ESR is approximately 0mohms. In order to match the model to the hardware, the inductance associated Figure 6. Extracted inductance of the probes placed 75um apart with the probes was extracted as done earlier. The spacing between the probes was also 75um in this case. The extracted inductance is shown in Figure 11, this inductance value was included in the model and the correlation between the updated model and measurement is shown in Figure 1. The capacitance of the structure was extracted and is plotted in Figure 13. Figure 14 shows the comparison between the measured values of different sized capacitors. The dimensions of the structures are 0.9mm square, 1mm square and a.1mm diameter circular capacitor. The measurement results show that the impedance responses of the capacitive structures are extremely sensitive to the probe inductances. D. Design of a capacitor network for decoupling The capacitor network has been designed by modeling thin film capacitors fabricated using the hydrothermal process /05/$ IEEE. 640

4 mentioned in Part A of this section. The design of the network is highly dependent on the process ground rules, which translates into the effective bandwidth that can be targeted for decoupling. The analysis done below is based on the System on Package (SOP) technologies ground rules developed at the PRC. Figure 10. Modeled frequency response of the circular capacitor of diameter.1mm. Figure 7. Model to hardware correlation with probe compensation inductance Figure 11. Extracted inductance of the probes placed 75um apart Figure 8. Extracted capacitance of 1mm X 1mm capacitor Figure 1. Model to hardware correlation with probe compensation inductance Figure 9. Measurement results of.1mm diameter capacitor. The (SOP) technology ground rules of the PRC process is summarized in Table. The capacitor network was designed to meet the target impedance number of 0.7 mohms (ITRS) over the mid band frequency range (100 MHz to GHz). An important parameter in the design of a power distribution system is the inductances associated with the power ground plane, via and solder balls. Figure 13. Extracted capacitance from measured results /05/$ IEEE. 641

5 Figure 14. Comparison of measured capacitors of different sizes TABLE : PROCESS GROUND RULES FOR THE PRC SOP TECHNOLOGY PARAMETERS Power Ground plane Dielectric thickness Power Ground plane Dielectric Constant VALUE 9um.65 Loss Tangent Line and space 10um Via diameter 0 um Via Pad size 40um Via Pitch 60um Single via pair inductance 0pH Capacitor minimum size 300um side Capacitor maximum size Spacing between capacitors 3000um side 100um This part of the section analyses the effect of the above mentioned inductances. The processor power and ground solder balls are assumed to be equally spread across the processor. An equal distribution of current is assumed across all the power and ground solder balls on the processor. For a 1TeraByte off chip bandwidth, the number of power ground solder balls far exceeds the number of via connections from the capacitors to the power-ground plane of the package. Therefore, through proper design each via could be directly connected to a solder ball. The spacing between the power and ground planes is 9um for future SOP s. The combination of the thin planes and uniform current distribution due to the power ground bumps would minimize the spreading inductance of the planes to a great extent. For the above scenario the spreading inductance has been neglected in the case where the capacitors are placed directly below the processor. The variation of spreading inductance with power ground plane thickness is given in [6]. Fast Henry was used in the inductance extraction of a power ground solder bump pair. The diameter of a solder bump is 50um and the pitch of the solder balls is 117um. The extracted inductance value was 14.56pH.There are 348 pairs of solder bumps in parallel as per the above analysis, giving an effective inductance of 4.4fH. The microvias are 0 um in diameter and the via pitch is 60um as given in Table. The inductance of a power-ground via pair as extracted from Fast Henry is 0pH. The solder ball and via inductances have been included in the simulation model. The design of the capacitor network along with the simulation results are described in the remaining part of this section. Based on the PRC process only 1 layer of discrete capacitors has been assumed. For the simulation results in Figures 15, 16 and 17 all the capacitors were placed just under or slightly around the periphery of the processor. Routing of the signal interconnects and influences of the spreading inductance were the main reasons for the compact placement of the capacitors. The package with the embedded capacitors was modeled using the Transmission Matrix Method [5]. The effect of the spreading inductance for capacitors placed outside the periphery of the processor was captured by the modeling methodology. Figure 15 shows the bandwidth over which the target impedance that can be met with barium titanate capacitors. The inductance (ESL) associated with these capacitors are of the order of 1pH as per the modeling in Part C of this section. In the figure below, the lower frequency band of the mid frequency range has been targeted. Figure 15. Lowerband decoupling with capacitor network In order to get the above response, 40 square capacitors of 1.75mm a side were used. 40 capacitors in parallel reduce the effective via inductance to 0.5pH. The sizes of the capacitors along with the via inductances decide the frequency at which they will resonate. In Figure 16, the higher band of the mid frequency range has been targeted. 80 capacitors of 0.75mm along with 80 capacitors of 1mm a side capacitors were used to obtain the above response. From the above analysis it can be observed that based on the current ground rules and material properties it would not be possible to achieve the target impedance from 100MHz to GHz. Therefore, in Figure 17, a similar analysis was carried out with capacitor layers to meet the target impedance over the mid frequency band. The capacitors used in Figure 15 along with 1 capacitors of.58mm a side were combined to get the response. From the above figure the mid frequency band under consideration can be targeted with capacitor layers. The target impedance of a multicore processor is 1mohm, which could be easily met with the capacitor network. The total capacitance of the network is.163uf. For the frequency s below 100 MHz and above GHz, surface mount and on chip decoupling capacitors can be used respectively. E. Package Design The package was designed to support a multi-core processor in the 65 nm node. The total number of powerground and signal solder bumps required to support 1 Tera /05/$ IEEE. 64

6 byte of off chip bandwidth are 6856 and 348 respectively, assuming a 50% overhead in signal lines [3]. is 0.65mm. Assuming that the number of power and ground pins on the package to the board has a 1:4 ratio to the power ground pins on the chip to the package, the total number of power-ground BGA s is The number of signal BGA s is 348, giving a total BGA count of 514. For a square package this number translates to 7 BGA bumps a side. Therefore the package size would be 46.6mm by 46.6mm. Figure 16. Higher band decoupling with capacitor network SMT S On chip decoupling Figure 18. Proposed cross section of 007 multi-core processor package supporting 1Terabyte/s off chip bandwidth. As can be seen from figure 18, there are 10 metal levels required for the package to support the capacitor layers, metal routing layers and the power-ground layers. Figure 17. Target impedance decoupling in mid frequency band The high number of solder balls would require a pitch of 117um on a 140mm chip. The details of the solder balls are given in Table 3. Assuming the size of the solder balls to be 50um in diameter and the line width to be 10 um as per the PRC ground rules, an estimate as to the number of layering levels is done next. The 348 signal bumps are assumed to be placed on the periphery of the processor. The width available for escape between solder balls is 67um. Therefore, 155 lines can escape to the first signal level. Carrying out a similar analysis the number of metal levels required to route all the signal levels are 3. Figure 18 shows the proposed cross section of the package. TABLE 3: SOLDER BALL DETAILS FOR A MULTI-CORE PROCESSOR Total number of solder balls 1084 Power ground solder balls 6856 Signal solder balls 348 Ball diameter 50um Number of solder balls per processor 101 edge Solder ball pitch 117um The ball grid pitch at the bottom of the package will decide it s size. From ITRS, the Ball Grid Array (BGA) pitch for 007 IV. CONCLUSION This paper highlights the importance of embedded capacitors in providing decoupling in the mid band frequency range. An efficient method of modeling and measuring embedded capacitors has been highlighted. Based on the decoupling and wiring requirements a 10 metal level package has been proposed to for future processors. REFERENCES [1] Hyungsoo Kim, Byung Kook Sun, and Joungho Kim, Suppression of GHz range power/ground inductive impedance and simultaneous switching noise using embedded film capacitors in Multilayer Packages and PCB s, IEEE Microwave and Wireless Components Letters, Vol 14, NO, February 004 [] Richard Ulrich, Embedded Resistors and Capacitors for Organic-Based SOP, IEEE Transactions on Advanced Packaging,Vol 7, NO., May 004 [3] Prathap Muthana, Madhavan Swaminathan, Packaging of Multi-core processors: Tradeoffs and Potential Solutions, ECTC 005., in press. [4] Istvan Novak, Jason R.Miller, Frequency Dependent characterization of Bulk and Ceramic Bypass Capacitors, Poster material for the 1 th Topical Meeting on Electrical Performance of Electronic Packaging, October 003. [5] Joong-Ho Kim and Madhavan Swaminathan, Modeling of Multilyaer Power Distribution Planes using Transmission Matrix Method, IEEE Transactions on Advanced Packaging, Vol 5, NO., May 005 [6] Tanmoy Roy, Larry Smith, ESR and ESL of Ceramic capacitor applied to Decoupling Applications, Electrical Performance of Electronic Packaging, October /05/$ IEEE. 643