Over GHz Electrical Circuit Model of a High-Density Multiple Line Grid Array (MLGA) Interposer

Transcription

1 90 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003 Over GHz Electrical Circuit Model of a High-Density Multiple Line Grid Array (MLGA) Interposer Seungyoung Ahn, Junho Lee, Junwoo Lee, Jonghoon Kim, Student Member, IEEE, Woonghwan Ryu, Byung-Hun Kum, Hyun-Seok Choi, Chong K. Yoon, and Joungho Kim Abstract The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. High-frequency electrical model was extracted from microwave -parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 ph of self inductance, 49 ph of mutual inductance with the nearest ground conductor line, and 186 ff of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz. Index Terms Equivalent circuit model, GHz frequency, highdensity package, multiple line grid array (MLGA), -parameter measurement, TDR/TDT. I. INTRODUCTION IN RECENT years, the demand for high-density packages with many hundreds of I/Os has steadily increased. The Semiconductor Industry Association (SIA) predicts that in the near future packages of more than two thousand I/Os and with more than one gigahertz off-chip clock frequency will be introduced. To date, ball-type grid array (BGA) packages have been used predominantly to meet current high-density package requirements. A BGA has a smaller feature size and narrower spacing than conventional bonding methods and, consequently, it has desirable electrical transmission characteristics and very small parasitic effects [1]. However, single-chip packages using a BGA with 0.65 mm pitch are still at the research stage and a BGA with 0.50 mm pitch is not expected to be in commercial Manuscript received December 1, 2002; revised March 4, S. Ahn, J. Lee, J. Lee, J. Kim, W. Ryu, and J. Kim are with the Terahertz Interconnection and Package Laboratory, Department of Electrical Engineering and Computer Science, Korean Advanced Institute of Science and Technology, Taejon , Korea ( javang@eeinfo.kaist.ac.kr). B.-H. Kum, H.-S. Choi, and C. K. Yoon are with Glotech, Inc., Seoul, Korea ( yoonck@glotech.co.kr). Digital Object Identifier /TADVP production until The density provided by the BGA package is still not sufficient to satisfy the foreseen needs of high-density and high-speed packages. Recently, a new type of high-density interposer, called a multiple line grid array (MLGA) interposer was introduced. This is a candidate to replace the BGA package by further reducing the bonding pitch. In addition, the height of the bonding structure can be controlled independently, reducing the parasitic inductance and capacitance at high frequency and enhancing the transmission properties at microwave frequencies [2]. The MLGA interposer has a nonball-type bonding structure, where thin conductor lines of cylindrical shape are used for bonding instead of the spherical shape of conventional ball-type bonding. An MLGA has many multiple line grids (MLGs), as shown in Fig. 1, and each MLG has eight conductor lines with a column type. The cylindrical conductor lines have either a circular or semi-circular cross section, as shown in Fig. 1(a). The space between the conductor lines is filled with either a ceramic or polymer dielectric insulator. A ceramic or polymer insulator can be chosen depending on cost, capacitive loading and the possibility of embedding passive devices inside the MLG. The eight conductor lines of the MLG are made of Sn/Pb/Ag metal alloy. An MLGA interposer is basically designed as a second-level bonding method that connects the bonding pads of a package substrate to the bonding pads of a PCB substrate. Bare dies are mounted on the package substrate either using either wire bonding or flip-chip bonding. An MLGA interposer was assembled containing twenty-five MLGs. Each MLG had eight conductor lines, giving two hundred I/Os in an MLGA package. By increasing the number of MLGs in an MLGA package, many thousands of I/Os can be easily manufactured. As shown in Fig. 1, the pitch between the conductor lines in the MLG was 0.8 mm. An MLGA with a 0.4 mm metal line pitch has already been successfully manufactured; this means it is possible to further decrease the pitch of the metal conductor lines and to enhance the I/O density. Moreover, the controlled height of the MLGA bonding varied from 0.2 mm to 0.5 mm. The height of the MLGA bonding was smaller than the size of the solder ball of conventional BGA bonding, resulting in lower parasitic effects compared to that of conventional ball-type bonding. The most unique and important feature of the MLGA package is the possibility of embedding passive devices inside the MLGA, which is not possible in a conventional bonding structures such as wire bonding, BGA or flip-chip bonding. The MLG is manufactured using either a multi-layer ceramic process or a multi-layer polymer process. When the MLGA interposer is fabricated using a multi-layer ceramic process, multi-layer parallel plate capacitors, termination resistors, /03$ IEEE

2 AHN et al.: OVER GHz ELECTRICAL CIRCUIT MODEL 91 Fig. 1. (a) Structure and dimensions of the MLG used as the basic building block of the MLGA interposer. (b) Three types of MLG used in high-frequency electrical modeling. Conductor shapes and the dielectric insulators are varied. (c) Cross-sectional structure and dimensions of the assembled MLG used in high-frequency electrical modeling. spiral inductors and filters can be embedded in the MLGA interposer. The values of the embedded passives are estimated in [3]. In this research, we have shown that pf of capacitance or nh of inductance can be embedded in an MLG of 1 mm height. For the packaging of high-speed digital devices, integrated passive devices are attracting more interest because devices that are more passive are required and these determine the performance of high-performance systems. The passive devices are used for signal line terminations, power/ground noise decoupling and filtering. The passive devices are required to have minimal unwanted parasitic effects, especially parasitic inductance. A fundamental method for minimizing parasitic inductance is to place the passive devices close to the die. Conventional bonding methods serve only as an electrical connection for the signal lines and power/ground lines. The MLGA interposer provides not only electrical interconnections with low parasitic effects but also an integrated passive device carrier. According to reference [3], the decoupling capacitor in the MLG is expected to improve the noise performance of the package significantly. More than 47% of the power line voltage fluctuation is reduced using an embedded decoupling capacitor in an MLG. In addition, vertical transmission line structures can be realized inside an MLG, enhancing the electrical transmission characteristics at high frequency. Transmission line structures can be implemented inside an MLG, by grounding conductor lines around an active conductor line in an MLG. To apply these high-density bonding techniques to high-performance systems, including the BGA and the MLGA, accurate and reliable electrical models of such bonding structures are required. With precise models, the performance of the system containing the packages can be accurately predicted and evaluated. Electrical models of the BGA package have been reported [4], [5]. In this paper, we investigate the high frequency characteristics of an MLGA interposer and derive equivalent circuit models. First, the basic configuration of the equivalent circuit was developed on the basis of the physical structure of the interposer. The parameters in the configuration-based circuit model were then fitted to the experimentally derived parameters using an optimization option of an Agilent ADS microwave simulator. The experimental parameters were measured using -parameter measurements and microwave network analysis. A similar modeling procedure has been already proven successful in the modeling of flip-chip bond modeling [6], [7], [8]. Test samples containing the MLGA interposer, package substrate, and PCB substrate were carefully designed for microwave testing, and we have followed an accurate optimization process. As a result of the -parameter measurement and model parameter extraction procedure, the self inductance of a conductor line inside the MLG was found to be 203 ph for a 0.4 mm high MLGA with a polymer insulator. By decreasing the height of the MLGA to 0.2 mm, the self inductance was decreased to 120 ph. The mutual inductance between the signal line and the nearest ground line was 49 ph for a 0.4 mm high MLG and 29 ph for 0.2 mm high MLG. The mutual capacitance between the conductor lines in the MLG was 186 ff in a 0.4 mm high MLGA with a circular conductor and a polymer insulator, and 175 ff for an MLGA with a height of 0.2 mm. II. FABRICATION AND ASSEMBLY PROCESS Fig. 1 is a schematic diagram showing the configuration and the dimensions of the MLGA interposer and its bonding structure. Each MLG consisted of a dielectric insulator and eight metal conductor lines inside the dielectric insulator. A number of MLGs construct a complete MLGA. Although eight metal conductor lines were used in each MLG in this study, as shown in Fig. 1, more than a hundred I/O lines can be merged into an MLG by enlarging the size of the MLG and by distributing the conductor holes. Two different types of MLG were fabricated for the modeling study. One consisted of a 2 mm 2 mm MLG with eight conductor lines in a semi-circular cross section, while the other was a 2.45 mm 2.45 mm MLG with eight conductor lines in a circular cross section, as shown in Fig. 1(b). In both cases, the pitch and diameter of the conductor lines were the same. The package substrate shown in Fig. 1(c) is a double-sided board made of polymer BT resin. The height of the MLG was chosen between 0.2 mm and 0.5 mm. The height of the solder that bonded the package substrate pads to the MLG conductor lines, as well as the MLG conductor lines to the PCB pads, was

3 92 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003 Fig. 2. Assembly process of the MLGA interposer. Fig. 3. Photographs of (a) the upper side of the MLGA interposer substrate on which the IC was mounted and bonded, and (b) the lower side of the MLGA interposer substrate after the assembly process of Fig. 2 was finished. The substrate routing was designed using double-sided layers. The assembled MLGA interposer has 25 (five rows 2 5 columns) MLGs and each MLG contains eight conductor lines, resulting in a total of 200 I/O connections. 0.2 mm, as shown in Fig. 1(c). Hence, the total height of the MLGA interposer was controllable from 0.9 mm ( ; height of the MLG, mm) to 0.6 mm ( mm). From previously reported heat sink simulations [2], the heat generated by the chips mounted on the package substrate is transferred to the PCB substrate through the package substrate, the solder pad and the metal conductor lines in the MLG. As the cross section of the circular conductor lines is larger than that of the semi-circular conductor lines, the 2.45 mm 2.45 mm dielectric insulator with a circular cross-sectional metal line has a better performance in terms of heat conductance. In addition, since the reliability of the solder bump sandwiched between the MLG and the package substrate depended on contact size, the MLG that used the circular conductor had a larger contact area and, hence, had a potentially higher yield. Two types of material were used for the dielectric insulator of the MLG. One type of MLG was made using a BT resin polymer insulator, and the other type of MLG was made using an alumina ceramic insulator. The dielectric constants of the BT resin and the alumina were 4.5 and 9.6, respectively. The holes for the conductor lines in the alumina insulator were drilled using a laser beam of 250 m diameter, while the holes in the polymer insulator were punched mechanically with a 200 m diameter punch. Metal Ag/Pt was painted on the walls of the holes, and the holes were then filled with a solder alloy of Sn/Pb/Ag. When BT resin was used for the MLGA package, the parasitic capacitance of the bonding structure was reduced in comparison to that of the alumina insulator. This lower parasitic capacitance decreases the output load of the IC, decreases the propagation delay and increases the impedance of the lines. The MLGA interposer that used the BT resin polymer insulator showed a higher reliability in temperature cycling fatigue tests with a dwell time of 15 minutes and a temperature range between 25 C and 125 C [2]. Conversely, the thermal conductivity of the ceramic insulator was higher, although the embedded passives were more easily accommodated using the ceramic insulator. The assembly process of the second-level packaging using the MLGA package is presented in Fig. 2. Interconnecting methods Fig. 4. Overall schematic of the assembled MLGA interposer. such as wire bonding or flip-chip can be used at the first-level bonding. After the solder bump was made on the pad of the PCB substrate, the MLGs were aligned to the PCB substrate. A solder re-flow process was then employed at about 220 C to 230 C to connect the MLGs to the pad of the PCB substrate. The same process was then repeated on the package substrate; this step was followed by the same re-flow process, which completed the assembly process. Fig. 3(a) is a photograph of the upper side of the package substrate on which bare dies were mounted and bonded. Fig. 3(b) is a photograph of the bottom side of the package substrate on which an array of MLGs were bonded. Twenty-five MLG arrays were bonded to the package substrate, and each MLG had eight semi-circular conductor lines, as shown in the figure. A total of 200 I/O connections were placed in this MLGA package. The size of the package substrate was 16.5 mm 16.5 mm. The pitch of the MLGs was 2.75 mm. Fig. 4 is an overall schematic of the assembled package where the MLGA interposer was used as a second-level package. The signal from the IC chip went through the wire-bonding or

4 AHN et al.: OVER GHz ELECTRICAL CIRCUIT MODEL 93 Fig. 6. Schematic of the test MLGA device for the s-parameter measurements. Fig. 5. Extraction procedure for the equivalent circuit model parameters used in the electrical modeling of the MLG interposer. flip-chip bonding, as well as through the microstrip line and the via on the package substrate, the conductor line inside the MLG and the microstrip lines on the PCB substrate. To reduce the parasitic effects of the MLG bonding and the size of the package, the height of the MLG was reduced from 0.5 mm to 0.2 mm, which resulted in a reduction of height for the total MLGA package, including the solder bump, from 0.9 mm to 0.6 mm. III. TEST DEVICE AND MODEL PARAMETER EXTRACTION The sequence of the model parameter extraction procedure is illustrated in Fig. 5. From step 1 to step 3, we used a vector network analyzer to measure the complex -parameters of the test vehicle, which included a series connection of the coplanar waveguide on the package substrate, an MLG interposer and a coplanar waveguide on the PCB substrate. From the physical configuration of the MLG structure, an equivalent circuit schematic of the MLG was proposed in step 4. In the proposed circuit configuration, the circuit parameters are described using lumped circuit elements such as self inductance, mutual inductance and mutual capacitance. Since the length of the MLG was much less than the wavelength that corresponds to the spectral range, the suggested model is considered acceptable. At this stage, the values of the lumped model parameters are not determined. Next, we calculated the -parameters of the same structure based on equivalent circuit model parameters with consideration of the physical structure and dimensions of MLGA bonding. We measured the -parameters of the coplanar waveguide, and we included those -parameters for a higher accuracy optimization process. From the proposed model configuration, the -parameters were calculated using a microwave simulator in step 6. Finally, the model parameters in the proposed circuit model were fitted to the measured parameters by matching the measurement-based -parameters and configuration-based -parameters using an optimization option of the microwave simulator in step 7. The procedures for extracting the model parameters were applied to the five different MLGA devices used in the test; the conductor lines and dielectric insulators of these devices had different heights and shapes. After the extraction of the equivalent circuit model parameters using the optimization process, we conducted time-domain reflection and transmission measurement. We then compared the waveforms with the reflection and transmission waveforms that were simulated using equivalent circuit model parameters extracted in step 8. The structure of the test device is shown in Fig. 6, which illustrates the package substrate design, the PCB substrate design and the microwave probe positioning. A high-bandwidth coplanar waveguide (CPW) was chosen for the waveguide structure because the CPW is compatible with a G-S-G probe of the -parameter measurement instrument and does not require a multi-layer design. The CPW had a length of 4 mm, a width of 100 m and spacing of 50 m. Twenty-five MLGs were used for the ground connection. In an MLG, only one out of eight conductor lines was used as a signal connection, and the other seven were used as a ground connection. As shown in Fig. 6, we used 25 MLGs as a ground connection for low impedance between the package substrate and the PCB substrate. Because of the multiple through-hole vias on the package substrate and multiple connections to the PCB substrate, negligible ground impedance between the two probes was achieved. The -parameters were measured up to 20 GHz using 150 m pitch probe tips. Both substrates were made using a double-sided BT resin board ( ) that was 0.4 mm thick. By considering the physical structure and dimensions of the MLGA interposer, we proposed a schematic of the equivalent circuit model, as shown in Fig. 7. The numbering of the eight conductor lines inside the MLG is shown in Fig. 7(a), and the proposed model circuit is shown in Fig. 7(b). The self inductance of a conductor line is characterized by inductor, and the self inductance of a via on the package substrate is characterized by inductor. The parameter represents the mutual inductance between the inductances of the conductor lines, and represents the mutual inductance between the vias.

5 94 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003 Fig. 7. (a) Eight conductor lines in a circular conductor MLG used in the circuit model analysis and their number assignment. (b) Suggested configuration-based equivalent circuit model of the MLG. The suggested model is drawn only for two nearby conductor lines, first and nth, for simplicity. This modeling step corresponds to step 6 of Fig. 5. The model includes the self-inductance (L), mutual capacitance between the first conductor line and the nth conductor line (C ) and via inductance of the package substrate (L ). Fig. 8(a) shows the entire schematic of the equivalent circuit model of the eight conductor lines in an MLG. Port 1 is the input port and port 2 is the output port for the -parameter measurement. Both ports are connected to the CPW of the substrates. The remaining seven conductor lines of the MLG are connected to the ground of the substrate. Fig. 8(b) shows the technique for reducing the number of variables in the optimization process. In determining the mutual inductance, we assumed that because mutual inductance depends on the distance between two conductor lines different weight factors must have existed for the conductor lines with different distances. After calculating the mutual inductance of the structure using Equation (1), we used the weight factors to determine the mutual inductance value in the optimization process [9] in nh (1) where the height of the conductor and the distance between conductors. When we calculated the mutual inductance, we used and the weight factors of the other conductor lines in the optimiza- Fig. 8. (a) Suggested equivalent circuit model of the test MLG based on the lumped circuit model L, M, C and R. Port 1 (line 1) is connected to the CPW on the package substrate and port 2 (line 1) is connected to the CPW of the PCB substrate. The remaining conductor lines (2 to 8) were shorted to the low impedance ground providing a current return path. (b) Relation between the mutual inductance M and M and between the mutual capacitance C and C. tion process. The capacitance between the conductors is represented by. The capacitance includes not only the mutual capacitance between conductor lines but also the mutual capacitance of the vias. As shown in Fig. 8(b), the mutual capacitance between the conductors is assumed to be inversely proportional to the distance between them. Since the distances are known, the mutual capacitance parameter is reduced to a single parameter, and the remaining six mutual capacitances,,,, and are consequently determined using the weight factors of the capacitances. Fig. 9 shows the schematics of the circuits for the measurement-based -parameters and configuration-based -parameters that are used in the optimization. The measurement-based -parameters mean the -parameters obtained purely by measurement, whereas the configuration-based -parameters mean the -parameters obtained by simulation using the measured -parameters of the CPWs on the package substrate and PCB substrate. After obtaining the measurement-based -parameters and the configuration-based -parameters, we determined the parameter values using an optimization method. The parameters to be determined were the inductance of the vias, the self induc-

6 AHN et al.: OVER GHz ELECTRICAL CIRCUIT MODEL 95 TABLE I EXTRACTED MODEL PARAMETERS OF THE VARIOUS TYPES OF MLG BONDING Fig. 9. Schematics of the circuits for measurement-based s-parameters and configuration-based s-parameters that were used in the optimization. The measurement-based s-parameters mean the s-parameters obtained purely by measurement, and the configuration-based s-parameters mean the s-parameters obtained by simulation using the measured s-parameters of the CPWs on the package substrate and PCB substrate. rameters and the right graph represents the imaginary parts of the parameters. As shown in the Fig. 10, the parameters were reasonably matched up to 20 GHz. Fig. 10. Comparison of the s-parameters after the parameter fitting process using the optimization method (step 6 of Fig. 5). The solid line represents the s-parameters from the measurement (step 3 of Fig. 5). The dotted line represents the s-parameters extracted on the basis of the suggested circuit model and following optimization (step 7 of Fig. 5). The graphs are for the MLG with an alumina dielectric of 0.3 mm height (h). (a) Comparison of the magnitude and phase of S. (b) Comparison of the magnitude and phase of S. tance and mutual inductance of conductor lines and the total capacitance of the conductor lines and vias. Fig. 10 shows the optimized -parameters of the equivalent circuit of the test vehicle that included two CPW lines and an MLG interposer. The return loss ( ) and the insertion loss ( ), with the magnitude and phase form, are shown in Fig. 10(a) and (b), respectively. The solid lines represent the configuration-based -parameters and the dotted lines represent the measurement-based -parameters. The left graph of the Fig. 10 represents the real parts of the pa- IV. VERIFICATION AND DISCUSSION The extracted equivalent circuit model parameters of the various types of test MLG interposers are summarized in Table I. The parameter means the self inductance of a conductor line, and means the mutual inductance between conductor line 1 and conductor line 2. The parameter means the self inductance of a via, and means the mutual inductance of via 1 and via 2 of the MLG interposer. Since the inductance of the MLG is strongly affected by the height of the MLG, the inductance becomes smaller as the height decreases. For the polymer MLG with a height of 0.2 mm, the self inductance is 120 ph, while for the ceramic MLG with a height of 0.4 mm, the self inductance is 203 ph. As shown in Fig. 11(a), the inductances are strongly dependent on, and proportional to, the height of the MLG for both the polymer and ceramic insulators. By reducing the height of the solder bump, the inductance can be further reduced. The self inductance of the via in the package substrate ranged from 81 ph to 102 ph, which is close to previously reported values [10]. The parasitic inductance in the packages generates a simultaneous switching noise, as well as a signal delay and reflections. Usually, to minimize the effect of the simultaneous switching noise of a high-speed digital system, a large portion of the I/O capability is used for power/ground connections. Since the MLG has very little parasitic inductance, a larger number of the I/Os can be used for other signal connections. The capacitance ( ) is the sum of the mutual capacitances between the reference conductor line 1 and the other seven metal lines (2, 3, 4, 5, 6, 7, and 8). Parasitic capacitances cause an additional delay and reflections in high-speed digital signal transmission. In addition, mutual capacitance produces crosstalk voltages in nearby lines. The capacitance of the MLGA interposer, which has higher values because of the dielectric insulator between the conductor lines, ranged from 175 ff to 312 ff. However, because of the low parasitic inductance, the resonance and cut-off frequencies were

7 96 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003 Fig. 12. Experimental setup for time-domain measurement using TDR. It consists of a time-domain reflectometer, cables, microprobes and a test vehicle that includes a microstrip line and MLGA bonding. Fig. 11. (a) Effect of MLG height on the inductance of the MLG. (b) Effect of MLG height on the capacitance of the MLG. still above the millimeter range in the frequency spectrum. As shown in Table I, the modeled capacitance for the same dielectric insulator becomes smaller as the height of the conductor line decreases. Consequently, reducing the MLG height reduces the parasitic effects of the package and increases the operating bandwidth. Another element that controls the parasitic effects is the dielectric insulator that surrounds the conductor lines. Two types of dielectric insulators were used: alumina ( ) and BT resin ( ). The capacitance of the MLGA interposer with the alumina insulator was larger than the capacitance of the MLGA interposer with the polymer insulator, as shown in Fig. 11(b). When using the alumina insulator and with a height of 0.5 mm, the MLGA interposer with circular conductor MLGs had a higher capacitance than the one with semi-circular conductor MLGs, as shown in Table I. The circular con- ductor lines, which are shown in Fig. 1(b), have a larger surface area in contact with the alumina insulator, resulting in a larger capacitance. In the view of process variation, if there is 50 m of change in distance between the nearest conductor lines, the capacitance will change by 6.7%. In worst case, if there are changes of 50 m for all conductor lines distances due to the process variation, there will be 1.7% of the change in capacitance. In case of inductance, the mutual inductance between the conductor lines will be affected by the change of the distance. As the return current flows through the seven conductor lines and a signal current will flow through a conductor line, the loop size is directly affected by the distance between the lines. According to the Equation (1), the mutual inductance change due to 50 m of the process variation will be result in 5.3% change in. For verification of parameters from the extracted equivalent circuit model, we measured time-domain signals using a time-domain reflectometer, and we compared the measured and simulated TDR/TDT waveforms. Fig. 12 shows the experimental setup for the TDR/TDT measurement. Using a vector network analyzer, we employed the same test vehicle that was used for frequency-domain measurement. We used a HP 54120B digital sampling oscilloscope and a 150 m pitch microprobe for this measurement. In Fig. 13, the simulated and measured TDR/TDT waveforms are shown with an 80 ps rise time for the source. In the TDR waveform, the inductance of the vias, the capacitance of the vias and the MLG bonding as well as the inductance of the MLGs are clearly observed in both results of simulation and measurement. These results show a very good correlation between simulation and measurement waveforms. Using the extracted model of Table I, we conducted some simulations to characterize the effect of an MLG itself. The insertion loss ( ) of the MLG bonding was simulated in the frequency domain. Fig. 14 shows the simulated insertion loss of the MLG bonding for a height of 0.3 mm and an alumina insulator. The insertion loss was 0.6 db at 10 GHz, and 2.2 db

8 AHN et al.: OVER GHz ELECTRICAL CIRCUIT MODEL 97 Fig. 13. TDR and TDT waveforms of simulation and measurement in a time domain. In the TDR waveform, inductance of the vias as well as the capacitance and inductance of the MLGs are clearly observed in both results. The results show a good correlation between simulated and measured waveforms. Fig. 14. Simulated insertion loss (S ) of a single MLG bonding based on the extracted model parameters (Table I) for a polymer MLG with a height (h) of 0.4 mm. The simulated time-domain waveforms through the MLGA bonding are shown in Fig. 15. The simulated MLG bonding type and dimensions are the same as in Fig. 14. In the simulation of the circuit operation, a digital pulse of 2 V peak-to-peak voltage and a 30 ps rise time was applied to port 1 as an input signal. The waveforms included the input pulse at port 1, the transmitted pulse at port 2, the near-end crosstalk at conductor line 2 and the far-end crosstalk at conductor line 2. The output signal had a V overshoot, V near-end crosstalk and V far-end crosstalk noise. This simulation shows that MLG bonding can be used for digital device packages of more than 5 GHz clock frequency and with a 30 ps rise time. V. CONCLUSION We developed a high-frequency equivalent circuit model of an MLGA interposer. The model was derived on the basis of -parameter measurements and subsequent microwave network analysis. To conduct accurate microwave measurements and derive reliable model parameters, the test MLGA devices were carefully designed and tested using a vector network analyzer and TDR. We measured several types of MLG interposers with different dielectric insulators and dimensions. Circuit simulation based on the extracted model reveals that the MLGA interposer can be used for millimeter microwave device packages with operating frequencies of more than 20 GHz and for digital device packages with clock cycles faster than 5 GHz. Although eight conductor lines were embedded in each MLG, more conductor lines could be implemented to enable the MLGs to function as very high density, high-i/o packages. Reducing the height of the MLG has been shown to decrease the effects of parasitic inductance and capacitance. To further reduce the parasitic inductance and capacitance of the MLGA package and, hence, to increase the frequency range of the applications, the height of the solder bump should be reduced. Reducing the height of the MLGA interposer and the solder bump may change the reliability and the thermal heat conduction properties. The electrical performance requires a compromise with the mechanical and thermal requirements. The parasitic capacitance of the MLG bonding between the conductor lines can be reduced by using different insulators with smaller dielectric constants. A unique feature of the MLGA interposer is the implementation of passive devices inside the MLGA substrate. In particular, by using a multilayer process, items such as resistors, embedded capacitors, inductors and filters can be merged into the MLGA structure. Further study on the design of these passive devices and their characterization is necessary to enhance the application of the MLGA interposer. Fig. 15. Time-domain simulated waveforms of the transmitted signal through the MLG and the crosstalk noise at the nearby conductor line inside the MLG. The simulation is based on the extracted equivalent circuit model parameters (Table I) for the polymer MLG with a height (h) of 0.4 mm height. at 20 GHz. Hence, the MLGA package is useful for microwave device packages. Furthermore, the performance of the MLGA package was simulated for high-speed digital device packages. REFERENCES [1] M. P. R. Panicker et al., Ball grid arrays: A DC to 31.5 GHz low cost packaging solution for microwave and MM-wave MMICS, Microwave J., vol. 41, no. 1, pp , Jan [2] Y. S. Kim and C. K. Yoon, Multiple line grid array (MLGA) package, in Proc. Int. Conf. High-Density Interconnect Syst. Packag., May 2000, pp [3] J. Lee, S. Ahn, S. Baek, and J. Kim, Design and estimation of embedded passives in multiple line grid array (MLGA) package, in Proc. Int. Symp. Electron. Mater. Packag., Nov. 2000, pp [4] T. Chang, P. H. Cheng, H. C. Huang, R. S. Lee, and R. Lo, Parasitic characteristics of BGA packages, in Proc. IEEE Symp. IC/Package Design Integr., 1998, pp

9 98 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003 [5] C. Mattei and A. P. Agrawal, Electrical characterization of BGA packages, in Proc. 47th Electron. Comp. Technol. Conf., May 1997, pp [6] W. Ryu, M.-J. Yim, S. Ahn, J. Lee, W. Kim, K.-W. Paik, and J. Kim, High-frequency SPICE model of anistropic conductive film flip-chip interconnections based on a genetic algorithm, IEEE Trans. Comp. Packag. Technol., vol. 23, pp , Sept [7] W. Ryu, M.-J. Yim, J. Lee, Y.-D. Jeon, S. Ahn, W. Kim, K.-W. Paik, and J. Kim, Microwave model of flip-chip interconnects using anisotropic conductive film, in Proc. Int. Conf. High Density Packag. MCM, 1999, pp [8] S. Ahn, W. Ryu, M.-J. Yim, J. Lee, Y.-D. Jeon, W. Kim, K.-W. Paik, and J. Kim, Over 10 GHz equivalent circuit model of ACF flip-chip interconnect using Ni-filled ball and Au-coated polymer balls, in Proc. 24th Int. Electron. Manufact. Technol. Symp., Oct. 1999, pp [9] F. W. Grover, Inductance Calculations Working Formulas and Tables. New York: D.Van Nostrand, [10] H. H. M. Ghouz and EL-Badawy EL-sharawy, An accurate equivalent circuit model of flip chip and via interconnects, IEEE Trans. Microwave Theory Tech., vol. 44, pp , Dec Woonghwan Ryu received the B.S. degree in computer engineering from Kwangwoon University, Seoul, Korea, in 1994, and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), in Daejeon, in 1997 and 2001, respectively. From 2000 to 2001, he was a Visiting Researcher in the Electronics Packaging Group, Gintic Institute of Manufacturing Technology, Singapore. From 1997 to 2001, he was under educational program as an Associate Engineer at Samsung Electronics Co., Ltd. In 2001, he joined the Signal Integrity Engineering Group, Intel Corporation, where he is currently a Staff Signal Integrity Engineer. He is now working on signal/power integrity analysis in Intel Chipset DDR-I/II/III memory interface, high-frequency EM modeling, and broadband device characterization. In addition, he is currently leading the Frequency-Domain (FD) Working Group to develop high-frequency FD methodologies including topology optimization, EM modeling, and GHz VNA characterization. He has been working with GHz system signal integrity analysis, high-speed VLSI interconnection, microwave package modeling, RF circuit design, and over GHz and low-power clock distribution, especially RF clock distribution. He has authored and co-authored more than 50 technical publications including four pending patents, journals, and conference proceeding papers. Seungyoung Ahn received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree. From 2001 to 2002, he was a Visiting Researcher in the Elecronics Packaging Group, Singapore Institute of Manufacturing Technology, Singapore. His current research interests include modeling and design of high-speed interconnection and package for GHz signaling. Byung-Hun Kum received the B.S. and M.S. degrees in material engineering from the University of Myongji, Youngin, Korea. He is a Process Engineer for Glotech, Inc., Seoul, Korea, where he researches multiple line grid array (MLGA) technology for application of the advanced electronic packaging and smart connector. Hyun-Seok Choi received the B.E. and M.E. degrees in ceramic engineering from Yonsei University, Seoul, Korea, in 1996 and 1998, respectively. He was a Student Researcher with the Thin-Film Technology Research Center, Korea Institute of Science and Technology (KIST), taking a university-kist collaborative graduate course from 1996 to He joined the IC Package Team, Glotech, Inc., Seoul, in He is currently a Researcher engaged in the development of the multiple line grid array (MLGA) package and connector. Junho Lee received the B.S. degree in radio science and communication engineering from Hong-ik University, Seoul, Korea, in 1998, and the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Taejon, in 2001, where he is currently pursuing the Ph.D. degree. His current research interests are high speed digital interconnect modeling and high frequency power/ground modeling. Chong K. Yoon received the B.A. and M.A. degrees in metallurgy from Yonsei University, Seoul, Korea, in 1976 and 1979, respectively, and the Ph.D. degree in materials science from the University of Michigan, Ann Arbor, in He is a CEO at Glotech, Inc., Seoul, and working on proliferation of the MLGA technology toward electronic packages and connectors. His professional fields of interest are interconnections in packages and connectors, especially focusing on design, materials selection, and characterization. Dr. Yoon is a member of IMAPS. Junwoo Lee received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1999 and 2001, respectively, where he is currently pursuing the Ph.D. degree. Since April 2002, he has worked at the Institute of Microelectronics, Singapore, as a one-year intern. His current research interest is in the design and modeling of high frequency package interconnections and power distribution systems. Jonghoon Kim (S 97) received the B.S. degree in electronics from Yeungnam University, Daegu, Korea, in 1995 and the M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1998 where he is currently pursuing the Ph.D. degree in the reduction of electromagnetic interference (EMI) from high-speed digital system. Joungho Kim received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, in His doctoral thesis was study on the femtosecond timedomain optical measurement techniques for the testing of high-speed digital devices and millimeter-wave circuits. After receiving the Ph.D. degree, he moved to Picometrix, Inc., Ann Arbor, in 1993, to work as a Research Engineer, where he was responsible for the development of a picosecond sampling system and a 70-GHz photo-receiver. In 1994, he joined the Memory Division, Samsung Electronics, Kiheung, Korea, where he was engaged in a 1-Gb DRAM design. In 1996, He moved to the Korea Advanced Institute of Science and Technology (KAIST), Taejon. He is currently an Associate Professor with the Electrical Engineering and Computer Science Department. Since joining KAIST, his research interest centers on the modeling, the design and the testing of high-speed interconnections, packages, PCB, and connectors over GHz frequency range. Related research topics are signal integrity, crosstalk, SSN, and EMI problems. He was on sabbatical leave during the academic year from 2001 to 2002 at Silicon Image, Inc., Sunnyvale CA, as a Staff Engineer. He has authored or co-authored over 100 technical articles and numerous patents.