Microwave Frequency Interconnection Line Model of a Wafer Level Package

Transcription

1 356 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 25, NO. 3, AUGUST 2002 Microwave Frequency Interconnection Line Model of a Wafer Level Package Junwoo Lee, Woonghwan Ryu, Member, IEEE, Jingook Kim, Junho Lee, Namhoon Kim, Member, IEEE, Junso Pak, Student Member, IEEE, Jae-Myun Kim, and Joungho Kim, Member, IEEE Abstract In this paper, we introduce the microwave transmission characteristics of interconnection lines on a wafer level package (WLP) and also propose a precise microwave-frequency model of the WLP interconnections. The slow wave factor (SWF) and attenuation constant are measured and discussed. High-frequency measurement is described, based on two-port -parameter measurements, using an on-wafer microwave probe with a frequency range of up to 5 GHz. The extracted model is represented in the form of distributed lumped circuit model elements and can be easily merged into SPICE simulations. From the extracted model, it was found that line capacitance and inductance per unit length are pf/mm and nh/mm, respectively. We have successfully applied the extracted model to the design and analysis of a Rambus memory module for time domain simulation and signal integrity simulation. From the simulation, it was found that the WLP has better high-frequency performance, because of its low package inductance, compared with the BGA package, but longer propagation delay, because of the relatively high package capacitance. Index Terms Lumped circuit model, Rambus DRAM, -parameter measurement, wafer level package. I. INTRODUCTION IT IS generally agreed that the design, fabrication and assembly of chip scale packages (CSPs) should move toward wafer level packaging technology to achieve the lowest possible total cost of the package [1]. In this wafer level package (WLP) approach, the package process is applied to an entire wafer and all the dies are packaged at the same time. Prior to dicing, each chip is in a packaged format, ready for the subsequent test and assembly process [2]. The WLP improves the concept of die-size packaging by introducing economies of scale in the manufacturing process. Fabricated packages, while still in wafer form, have clear advantages over traditional packages [3]. First, mass manufacturing of the WLP in wafer form enables low cost manufacturing of the packages. Hence, the cost of the WLP manufacturing is very sensitive to the yield of devices on the wafer. However, if the yield of the die is kept high, the cost Manuscript received January 8, 2002; revised June 21, This work was supported by the Hynix Semiconductor Company, Ltd. J. Lee, J. Kim, J. Lee, N. Kim, J. Pak, and J. Kim are with the Terahertz Interconnection and Package Laboratory, Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Korea ( teralab@ee.kaist.ac.kr; fluxus@eeinfo.kaist.ac.kr). W. Ryu is with the Memory Focus Team and FD Working Group, Intel Corporation, Folsom, CA USA. J.-M. Kim is with the Electrical Package/Module Team, Hynix Semiconductor Company, Ltd., Ichon , Korea. Digital Object Identifier /TADVP of WLP can be significantly reduced compared with that of traditional packages. Furthermore, the cost of WLP manufacturing can be reduced further using die shrink. As the size of the die shrinks on a wafer, the number of dies per wafer increases, and because the cost of processing the packages in the wafer form is essentially fixed, the cost per package decreases. In addition, the WLP provides the smallest form factor since the package is fabricated in wafer form with the die size. Finally, the WLP may be tested and burned-in in the wafer form before dicing. Probe contact on solder bumps or balls is improved compared with that on bare aluminum pads. However, because the WLP is truly chip-size, all the I/O must fit under the chip. This can effectively limit the number of I/O that can be used if the package pitch is to be used on available board technology. In addition to the above-mentioned advantages of the WLP, one of the other most significant advantages of the WLP is the capability of the WLP in very high-speed applications. The WLP can be applied as a package solution for above 1 GHz digital, differential signaling, and microwave devices. WLP will be used more extensively for high-frequency applications including Rambus DRAM [4]. WLP has very short line traces on the package, resulting in very low parasitic inductance and capacitance. The length of the interconnection lines on the WLP should be less than the length of the die. This low interconnection-line inductance further reduces high-frequency delays, improves speed, and suppresses power/ground fluctuations caused by the package parasitics [5]. In particular, when a top-level interconnection on the chip works as a ground plane for the interconnection lines on the WLP, the inductance of the interconnection lines can be reduced further. However, little modeling work has been reported for the interconnection line of the WLP aimed at extracting the high-frequency model of the interconnection lines, which can be merged into SPICE simulations. The previous work has measured the total parasitic capacitive loading effect of the WLP, including the parasitic capacitive loading of the solder balls and the input capacitance of the chip [6], [7]. The measurements were based on one-port -parameter measurements. The parasitic inductive effect of the interconnection lines was not considered in the previous studies. Furthermore, the previous works did not exclude the effect of the multiple reflections during the -parameter measurement and subsequent modeling process. In this paper, we introduce the microwave transmission characteristics of the interconnection lines on the WLP, and also propose a precise microwave frequency model of the WLP interconnection lines. These high-frequency characteristics and the /02$ IEEE

2 LEE et al.: MICROWAVE FREQUENCY INTERCONNECTION LINE MODEL 357 suggested model can provide useful information to the package designers in order to realize the optimal design of the WLP. To describe the transmission characteristics, the Slow Wave Factor (SWF) and attenuation constant of the interconnection line on the WLP were measured and are discussed. The high-frequency measurement was conducted based on two-port -parameter measurements using a on-wafer microwave probe, with a frequency range of up to 5 GHz, and the parasitics associated with the connectors were removed by using on-wafer probing measurements. In addition, by using a de-embedding process after the -parameter measurement, the effect of the multiple reflections, caused by impedance discontinuities, on the test WLP could be avoided. Therefore, we were able to extract pure models of the interconnection lines on the WLP. The model is in the form of a distributed lumped circuit model with elements such as shunt capacitors, series inductors, and series resistors. From the extracted model, it was found that the interconnection line capacitance and inductance per unit length are pf/mm and nh/mm, respectively. The interconnection line resistance varies depending on frequency, because of the frequency dependent skin effect. The extracted model can be easily merged into SPICE simulation, to simulate the delay, reflection, and attenuation of the signals on the WLP. We have successfully applied the extracted model of the WLP to the design and analysis of a Rambus memory module for time domain simulation and signal integrity simulation. From the simulation, using the extracted model, which can be explained physically, we observed that the effective impedance of the Rambus in-line memory module (RIMM) loaded bus rapidly decreases, deviating from the target impedance, as the inductance of the WLP increases. Hence, the WLP shows better performance due to its low package inductance compared with the BGA package. In the time-domain simulation, longer delay but smaller overshoot were shown for the WLP compared with the BGA. II. HIGH-FREQUENCY TRANSMISSION CHARACTERISTICS OF WLP INTERCONNECTION LINES SLOW WAVE FACTOR AND ATTENUATION CONSTANT For the measurement and modeling in our study, we used one form of the WLP called Omega-CSP. The fabrication process of the Omega-CSP was developed by Hynix Semiconductor (formerly Hyundai Electronics Corporation, Ltd.) and is similar to the integrated circuit fabrication process [7]. A spin coating process is used to stack the stress buffer layer (SBL) and bisbenzo cyclo butane (BCB) layer. Fig. 1(a) and (b) show the cross-sectional structure and the re-distribution layer pattern of the Omega-CSP WLP used in this study. Test interconnection line patterns are designed and fabricated on the test WLP for the -parameter measurements and subsequent modeling process. Silicon was used as the wafer substrate of the WLP. The -parameter measurement technique is widely known to be extremely stable, as well as accurate up to very high frequencies. Moreover, it is easily de-embedded to exclude the effect of the probing pad parasitics during the on-wafer characterization. Fig. 2(a) and (b) illustrate the layout of the test pattern and its cross-sectional structure. For the interconnection Fig. 1. Structure of WLP (Omega CSP) developed by Hynix Semiconductor. (a) Cross-sectional structure of the WLP. (b) Layout of interconnection lines and pad distribution on the WLP. line structure, a conductor-backed coplanar waveguide [8] was chosen. This conventional line structure was used in the WLP, on the assumption that the metal layers on the chip work as ground planes. The line width of the pattern was 40 m, and the line lengths varied from 2.44, 3.08, 4.36, 5.21, 8.18, to 10 mm. To investigate the high-frequency transmission characteristics of the interconnection lines on the test WLP, we calculated the SWF and attenuation constant from the -parameter measurements. From the SWF, represented as a function of frequency, we can verify the propagation mode along the interconnection line and are able to calculate the effective dielectric constant of the waveguide, which defines the propagation velocity of the electromagnetic wave through the interconnection line. The attenuation constant derives from the total loss of the interconnection line and is caused by the dielectric loss and skin effect loss. We obtained the SWF from the de-embedded using (1) (4) [9] -parameters (1) (2) (3) (4)

3 358 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 25, NO. 3, AUGUST 2002 Fig. 3. Measured slow wave factor of the interconnection lines on the WLP using a network analyzer and a probe station. The slow wave factor is calculated from the measured S-parameters. Fig. 2. Test WLP (Omega CSP) for the S-parameter measurement. (a) Metal layout pattern including the Coplanar Waveguide (CPW) and G S G probing pads. (b) Cross-sectional structure of the test WLP. The structure is a combination of the CPW and the microstrip line. where and are the de-embedded -parameters from the measured -parameters, and is the free-space phase velocity. and are the wavelengths in free space and in the guiding medium, respectively. Fig. 3 shows the measured SWF of the test WLP interconnection line as a function of frequency up to 5 GHz. The maximum value of the SWF is approximately 2.22 at 80 MHz. It demonstrates that there is no slow wave propagation in the WLP interconnection line. This means that wave propagation along the interconnection line on the WLP is a TEM or Quasi-TEM mode, since slow wave propagation occurs when the waves are not in a TEM or Quasi-TEM mode. In the WLP, the field is mostly confined to the dielectric medium [the SBL layer in Fig. 2(b)], which is a relatively lossless dielectric medium. As illustrated in Fig. 1(b), the SBL layer is the dielectric layer under the metal interconnection line on the test WLP. Above 1 GHz frequency, the SWF is almost invariant and frequency independent. Its value remains at about 1.73, corresponding to an effective dielectric constant of approximately 3 the same as the relative permittivity of the SBL dielectric layer. Therefore, the fields are fully guided within the SBL layer, and the test interconnection line on the WLP can be considered as a conductor-backed coplanar waveguide with the guiding medium of the SBL layer. It was previously reported that the SWF of the on-chip interconnection line on a Si chip is approximately 7, and the attenuation constant approximately 1 db/mm at 5 GHz [10] [12]. The Fig. 4. Measured attenuation constant of the interconnection line on the WLP. The attenuation constant is obtained after the de-embedding procedure on the measured S-parameters. SWF and attenuation constant of the on-chip interconnection line are found to be much higher than those of the interconnection lines on the WLP. This occurs because of the high resistance of the on-chip interconnection line and the high-loss silicon substrate. Even though the propagation mode in the on-chip interconnection is a Quasi-TEM mode, the relative dielectric constant of the silicon is higher, which results in a higher SWF. We obtained the attenuation constant from (3). As shown in Fig. 4, the attenuation constant of the WLP interconnection line is small. The maximum attenuation constant is approximately 0.08 db/mm at 5 GHz. The attenuation constant increases with frequency because the metal conductor loss and the dielectric loss increase as the frequency increases. The low loss of the interconnection line is due to the low dielectric loss of the guiding medium of the SBL layer and the low resistivity of the copper conductor.

4 LEE et al.: MICROWAVE FREQUENCY INTERCONNECTION LINE MODEL 359 Fig. 6. The flow chart of the model parameter extraction procedure from the S-parameter measurement. After the parasitics of the probing pad are de-embedded using a y-parameter-based network analysis technique, the calculated S-parameters from the configuration-based model (Fig. 5) are fitted to the measured S-parameters. A genetic algorithm was used for the data fitting process. Fig. 5. Equivalent circuit representation of the interconnection lines on the WLP. An interconnection line is divided into two -type equivalent circuit models. (a) Configuration-based model of the WLP interconnection line. (b) Two-sectional model of the WLP interconnection line. III. MICROWAVE FREQUENCY MODEL AND EXTRACTED MODEL PARAMETERS The equivalent circuit model of the WLP interconnection line is composed of distributed lumped circuit elements, which is justified by the evidence of the quasi-tem mode propagation given in Section II. The cross-section and the transverse circuit elements of the interconnection line on the WLP are shown in Fig. 5(a). represents transverse capacitance between the signal trace and the coplanar ground on the top layer of the WLP and is the transverse capacitance of the SBL layer. Since the interconnection line length of the test WLP is relatively short compared with the wavelength of the guided wave at 5 GHz, we used a simplified distributed circuit model as shown in Fig. 5(b). It is a two-section -model. The validity of the suggested model is demonstrated by comparison of the simulation, based on the extracted model, and the high-frequency measurements. As shown in Fig. 5(b), the metal conductive loss is introduced as a resistance in series with where is the inductance of the interconnection line. The transverse capacitance is represented by which is the sum of the and the in Fig. 5(a). Dielectric loss in the SBL layer is ignored because it is too small to affect the electrical transmission. The resistance includes the resistance of the return current as well as the resistance of the signal conductor, which is described in (5) (7) [13] [ /m] (6) [ /m] (7) where,, and are the signal conductor width, the Al metal plane thickness, and the height of the signal conductor from the Al metal plane, respectively. In (6), it is assumed that current in the Al metal plane is uniformly distributed because the skin depth of Al metal plane is larger than the thickness. The resistance of the coplanar ground is ignored because most of the return current flows through the Al metal plane. According to the 3-D full wave simulation, almost 70% of return current flows through the on-chip metal plane. The next step was to extract the model parameters, described in Fig. 5(b), from the -parameter measurements. Fig. 6 depicts the modeling procedure. After the probe pad parasitics were de-embedded using -parameter-based techniques [14], the de-embedded -parameters were obtained from the measured -parameters. Then, the calculated -parameters from the suggested equivalent circuit model of Fig. 5(b) were fitted to the de-embedded -parameters using a genetic algorithm [15], [16]. By comparing the two sets of -parameters, the actual model parameters were extracted. The -parameters of the suggested equivalent circuit model of Fig. 5(b) can be calculated by using (8) (11) since the twosection -model is connected in a cascade [17] [ /m] (5) (8)

5 360 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 25, NO. 3, AUGUST 2002 Fig. 7. Comparison of the S-parameters up to 5 GHz. The solid line represents the de-embedded S-parameters from the measurement. The dotted line represents the S-parameters calculated from the extracted model, which was fitted to the measured S-parameters. (a) Magnitude of S. (b) Phase of S. (c) Magnitude of S. (d) Phase of S (9) TABLE I EXTRACTED EQUIVALENT CIRCUIT MODEL PARAMETERS OF THE INTERCONNECTION LINES ON THE WLP. THE CONFIGURATION OF THE CORRESPONDING MODEL IS ILLUSTRATED IN FIG. 5(a) AND (b) (10) (11) In Fig. 7(a) (d), we can compare the two sets of -parameters. One set is derived from measurement and the other set is calculated from the suggested equivalent circuit model by (8) (11). The two sets of -parameters are shown as functions of the frequency up to 5 GHz. As can be seen, the measured -parameters, and the calculated -parameters are in close agreement up to 5 GHz, demonstrating the validity of the extracted model parameters. This excellent agreement guarantees the precision of the extracted circuit model for the WLP interconnection line. The extracted model parameters are tabulated in Table I. Fig. 8(a) shows the total capacitance of the interconnection line on the WLP as a function of interconnection line length. The capacitance per unit line length can be obtained as 0.11 pf/mm from the slope in Fig. 8(a). Fig. 8(b) shows the extracted total inductance as a function of interconnection line length on the WLP. The inductance of the WLP interconnection line per unit length is nh/mm. If we assume that the chip size is 1 cm, and the maximum interconnection line length on the WLP is 4 mm, then the line inductance is approximately 1.14 nh, which is much smaller than that of wire-bond-type and lead-type packaging methods. By using the more than 10 multiple lines and solder balls for the power/ground connection, the power/ground inductance can be significantly reduced below 114 ph. Using these extracted circuit elements, we simulated the insertion loss of the interconnection line on the WLP. From the simulation result, as shown in Fig. 9, the frequency for 1 db insertion loss is 30.3 GHz.

6 LEE et al.: MICROWAVE FREQUENCY INTERCONNECTION LINE MODEL 361 Fig. 9. Calculated insertion loss of the WLP interconnection line from the extracted model parameters for 3 mm line length. The frequency for 01dB insertion loss is 30.3 GHz. Fig. 8. Extracted model parameters as a function of interconnection line length on the WLP. From the slope of the graph, we can obtain the line capacitance and the line inductance per unit length. (a) Capacitance versus line length. (b) Inductance versus line length. IV. LOADING EFFECT OF WLP ON A RAMBUS IN-LINE MEMORY MODULE By using the extracted model of the WLP, we have investigated the loading effect of the WLP on a high-speed board. Since the parasitic loading effect of the WLP is very small, it is believed that the WLP is well suited for high-speed applications. We chose a Rambus in-line memory module (RIMM) board as the high-speed board in our study. The Rambus channel on the RIMM is designed for a 28 nominal impedance. The entire signal path in the RIMM can be divided into three distinct sections. The first section of the trace on the RIMM is the unloaded trace section from the left connector contact pads of the RIMM to the first device, where the WLP of the Rambus chip is not attached on the trace. The second trace section is the loaded trace section, where the WLP is attached with a regular spacing. The third section is the unloaded trace section from the last device to the right connector contact pads on the RIMM. Total length of the trace is 15.9 cm. The trace of the unloaded section has a 28 characteristic impedance [18]. However, due to the loading effect of the WLP with the device input impedance, the effective line impedance of the trace in the loaded section is not aligned to the target impedance. In addition, due to the frequency-dependent nature of the package loading impedance, the on the RIMM is also affected by the frequency change. Hence, the characteristic line impedance of the second loaded line section must be tuned so that stays within the range allowed by the specification. The deviation of produces problems of signal distortion and additional signal delay due to signal reflection and impedance mismatch. With the given parasitic model of the WLP, can be adjusted by changing the original line impedance before the loading of the WLP on the RIMM. Fig. 10 shows the circuit model of the RIMM loaded channel section used in this study. The model of the loaded line section on the RIMM consists of the transmission line model of the line trace on the RIMM PCB and the input loaded circuit elements,, and by the WLP or the BGA package. A total of eight packages were attached to the trace at mm intervals. Fig. 11 shows the simulated of the loaded line section on the RIMM as a function of the frequency. The simulation was executed up to a frequency of 1.6 GHz, which is the 3 db frequency of a recently released 533 MHz clock RDRAM. The target impedance is 28 and the allowed range of is between 25.2 and 30.8 [18]. For the simulation, the model parameters of the WLP loading, such as,, and, are required. Table II shows the model parameters used in the simulation for the WLP and the BGA. The interconnection line length of the WLP and the BGA were assumed to be 3 mm. The loading capacitor and inductance of the WLP interconnection line were obtained from Fig. 8(a) and (b). The loading package model of the BGA was obtained from the previous work and from measurement data using the one-port -parameter measurement method [6], [19].

7 362 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 25, NO. 3, AUGUST 2002 TABLE II TYPICAL VALUES OF LOADED CIRCUIT ELEMENTS IN THE PACKAGE TYPES OF THE WLP AND THE BGA, WHERE THE CHIP INPUT LOADINGS ARE ALSO INCLUDED. (a) WLP (b) BGA Fig. 10. Model of the loaded channel in a Rambus In-line Memory Module (RIMM). The loaded line on the RIMM consists of the transmission line model (distributed RLGC model) of the line trace on the RIMM PCB and the input loaded circuit elements (R, L, and C ) by the WLP or the BGA package. Fig. 11. Effective line impedance (Z ) of the loaded line section on the RIMM after the package loading for the case of the WLP, depending on the different line impedance of the RIMM PCB before the package loading. By choosing the line impedance on the RIMM PCB before the package loading, the effect of the increased loading capacitance by the WLP can be compensated. As can be seen from Fig. 11, the is strongly dependent on the line impedance without package loading on the RIMM. A lower line impedance without the package loading produces a lower. Moreover, we also noted that the decreases as the frequency increases. At higher frequency, the shunt conductance of the loaded package impedance increases and results in lower. The resonance LC frequency of the package loading is approximately GHz. Hence, in the frequency range below the resonance frequency the effect of the capacitive package loading is dominant. On the other hand, in the case of the package of the lead-type or wire-type bonding, inductive loading effects of the package may prevail. By choosing the appropriate line impedance, can be obtained in the target range. In Fig. 11, the unloaded line impedance of 44 is the best choice, which produces minimum variation of. Fig. 12 shows the simulated for the WLP and the BGA, for comparison, when the line impedance is 41 before the package loading, where 41 is the recommended line impedance from the RIMM design specification. In the Fig. 12. Effective line impedance of the loaded line section trace on the RIMM. The loaded circuit elements in Table II are used to calculate the effective line impedance. simulation of Fig. 12, the BGA shows better performance, in terms of the impedance, because the of the BGA stays close to the target impedance of 28. The capacitive loading of the BGA is smaller than that of the WLP as shown in Table II. The higher capacitive loading of the WLP is caused by the thin dielectric thickness (SBL) of the WLP compared with that of the BGA. The dielectric thickness of the test WLP is 20 m, by the spin coating process of the WLP. On the other hand, the dielectric thickness of the conventional BGA is approximately 175 m. The higher capacitive loading of the WLP produces a lower when the package is loaded on the trace of the RIMM. When the frequency is increased above the resonance frequency, the inductive loading effect becomes dominant and the WLP has a smaller change in due to the package loading. Fig. 13 shows the step-input responses of the RIMM for the package types WLP and BGA. The time-domain simulation is conducted using the circuit schematic of Fig. 10 and

8 LEE et al.: MICROWAVE FREQUENCY INTERCONNECTION LINE MODEL 363 impedance mismatching when applied to conventional RIMM design. However, the increased capacitive loading can be successfully compensated for by adjusting the line impedance of the RIMM PCB. Moreover, the lower inductance of the WLP compared with the BGA guarantees better performance in the above 1.5 GHz frequency region. However the RIMM has a longer ZC delay when WLP is used. Therefore, with careful consideration to the propagation delay, the WLP can be a strong candidate for the RDRAM package or other high-frequency devices with low manufacturing cost. ACKNOWLEDGMENT The authors wish to thank Y. T. Kwon and J. K. Hong, Package/Module Team, Hynix Semiconductor (formerly Hyundai Electronic Corporation, Ltd.), for their support. Fig. 13. Step responses of the RIMM for the package types WLP and BGA. The input pulse has a 0.2-ns rise time. Table II. The input pulse has a rise time of 0.2 ns. Eight devices were mounted and bonded on the signal trace from the left connector contact pads on the RIMM to the right connector contact pads on the RIMM. The higher input capacitance of the WLP generates the additional propagation delay of 39 ps compared with the BGA. However, the voltage overshoot of the RIMM is smaller with WLP by 35 mv because of its lower package loading inductance. When a 44 line impedance before package loading is chosen to compensate for the higher input capacitance of the WLP as shown in Fig. 11, the propagation delay is increased by 24 ps because the increased line impedance makes the ZC delay longer. Consequently, although the WLP does not meet the Rambus package specification, because of the higher package loading capacitance, the increased loading capacitance of the WLP can be compensated for by choosing the line impedance on the RIMM PCB correctly. In this case, the propagation delay has to be taken into account. V. CONCLUSION The measured SWF and the attenuation constant confirm the propagation mode of a quasi-tem mode in the WLP interconnection line with low loss. It was also shown that the WLP interconnection line can be considered to be a conductor-backed coplanar waveguide. The model of the WLP interconnection line is represented in the form of distributed lumped circuit model elements such as shunt capacitor, series inductor, and series resistor. Excellent agreement was demonstrated between the extracted model parameters and the theoretical calculation from the suggested model. From the extracted model parameters, the inductance and the capacitance per unit length of the WLP interconnection line are nh/mm and 0.11 pf/mm, respectively. Based on these parameters, we simulated the effective line impedance, propagation delay, and voltage overshoot of the RIMM using the WLP. The increased capacitance of the WLP may cause REFERENCES [1] Integrated Circuit Engineering Corporation, IC Packaging Update, 1999, ch. 5. [2] R. R. Tummala, Fundamentals of Microsystems Packaging. New York: McGraw-Hill, 2001, pp [3] P. Elenius, S. Barrett, and T. Goodman, Ultra CSP A wafer level package, IEEE Trans. Adv. Packag., vol. 23, May [4] P. Garrou, Wafer level chip scale packaging (WL-CSP): An overview, IEEE Trans. Adv. Packag., vol. 23, May [5] N. Pulsford, M. de Samber, and M. VanDelden, Integrated passive components and chip scale packaging, in Proc. IEEE Workshop VLSI, Brugge, Belgium, May [6] M. H. Ahn, D. H. Lee, and S. Y. Kang, Optimal structure of wafer level package for the electrical performance, in Proc. IEEE Electron. Comp. Technol. Conf., Las Vegas, NV, May [7] S. W. Park, J. M. Kim, H. G. Baik, S. H. Kim, J. K. Hong, and H. S. Chun, Thermal and electrical performance for wafer level package, in Proc. IEEE Electron. Comp. Technol. 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9 364 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 25, NO. 3, AUGUST 2002 Junwoo Lee received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1999 and 2001, respectively, where he is currently pursuing the Ph.D. degree. Since April 2002, he has been with the Institute of Microelectronics, Singapore, as a one-year intern. His current research interest is in the design and modeling of high frequency package interconnections and power distribution systems. Woonghwan Ryu (M 01) received the B.S. degree in computer engineering from Kwangwoon University, Seoul, Korea, in 1994, and the M.S. degree and the Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1997 and 2001, respectively. From 2000 to 2001, he was a Visiting Researcher in the Electronics Packaging Group, Gintic Institute of Manufacturing Technology, Singapore. He is now a Staff Analog Engineer at Intel Corporation. He is a key member of Memory Forcus Team and FD Working Group. He has been working with GHz system signal integrity design, GHz SSO simulation, highspeed VLSI interconnection characterization, microwave package modeling, RF circuit design, and over GHz and low-power clock distribution, especially RF clock distribution. He is currently working on high-speed DDR interface design and high-frequency stack-up characterization. He has authored or co-authored more than 50 technical articles and three pending or submitted patents. Junso Pak (S 02) was born in Seoul, Korea, in May He received the B.S. degree in electronic communication engineering from Hanyang University, Seoul, Korea, in 1998, the M.S. degree from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2000, where he is currently pursuing the Ph.D. degree. Since 1998, he has been with Terahertz Interconnection and Package Laboratory, Electrical Engineering Department, KAIST. He has been involved with development of RF coil for magnetic resonance of imaging. His current research interests are via analysis on printed circuit board (PCB), package, and silicon IC for the signal integrity, and electromagnetic interference (EMI). Jae-Myun Kim received the B.S. degree in semiconductor engineering from Chung Ju University, Korea, in He joined the Packaging Research Team, Hynix Semiconductor Industry Company, Korea, in He has been involved in development of memory device packaging. He is now a Research Engineer working on contract manufacturing of electronic packaging. Jingook Kim received the B.S. and M.S. degrees in electrical engineering from the the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2000 and 2002, respectively, where he is currently pursuing the Ph.D. degree. He has been working on GHz systems signal integrity design, package modeling, and minimizing EMI radiation. His current research interest is the establishing the design methodology of power/ground network for high-speed packages and PCB s. Junho Lee received the B.S. degree in radio science and communication engineering from Hong-ik University, Seoul, Korea, in 1998, and the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2001, where he is currently pursuing the Ph.D. degree. His current research interests are high speed digital interconnect modeling and high frequency power/ground modeling. Namhoon Kim (M 01) received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1999 and 2001, respectively. He has been working on GHz systems signal integrity design, package modeling, and crosstalk modeling on PCB, package, and chip. He is currently on Silicon Image, Inc., Sunnyvale, CA, as a Signal Integrity Engineer. His work has included microwave device measurement, testing, modeling, and characterization. Joungho Kim (M 87) received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, in His doctoral thesis was the study of femtosecond time-domain optical measurement techniques for the testing of high-speed digital devices and millimeter-wave circuits. After receiving the Ph.D. degree, he moved to Picometrix, Inc., Ann Arbor, MI, in 1993, as a Research Engineer, where he was responsible for the development of a picosecond sampling system and a 70-GHz photo-receiver. In 1994, he joined the Memory Division, Samsung Electronics, Kiheung, Korea, where he was engaged in a 1-Gbit DRAM design. In 1996, he moved to the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, where he is currently an Associate Professor with the Electrical Engineering and Computer Science Department. Since joining KAIST, his research interest centers on the modeling, the design and the testing of high-speed interconnections, packages, and connectors over GHz frequency range. Related research topics are signal integrity, crosstalk, SSN, and EMI problems. He also has developed a novel picosecond/thz near-field imaging system by using ultrafast optoelectronic technique for the high-frequency characterization of the interconnections. He has been on sabbatical leave during the academic year from 2001 to 2002 at Silicon Image Inc., Sunnyvale, CA, as a Staff Engineer. He has authored or co-authored over 100 technical articles and numerous patents.