HIGH-SPEED integrated circuits require accurate widebandwidth

Transcription

1 526 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 Characterization of Co-Planar Silicon Transmission Lines With and Without Slow-Wave Effect Woopoung Kim, Member, IEEE, and Madhavan Swaminathan, Fellow, IEEE Abstract Co-planar lines on silicon substrates with and without slow-wave effect are characterized using time-domain reflectometry (TDR) and vector network analyzer (VNA) measurements, and simulated using a proposed nonphysical resistance inductance conductance capacitance (RLGC) model. The silicon co-planar lines are characterized based on comparison to package transmission lines. Co-planar silicon lines without slow-wave mode are modeled in the same way as package transmission lines, but co-planar lines with slow-wave mode are modeled in a different way from package transmission lines. Hence, a nonphysical RLGC model including slow-wave mode is proposed along with the extraction method from VNA measurements. Simulation results correlate well with time- and frequency-domain measurements for the co-planar silicon lines. Index Terms Co-planar line, silicon transmission line, slowwave, TDR, VNA. I. INTRODUCTION HIGH-SPEED integrated circuits require accurate widebandwidth characterization of on-chip wires. As the speed of integrated circuits goes beyond gigahertz (GHz), the inductance of on-chip wires becomes important since the inductance explains the delay of long on-chip signal or clock lines and the simultaneous switching noise of on-chip power grids. The delay of on-chip signal lines can be represented as resistance capacitance ( ) delay at low operating frequencies, but is represented as inductance capacitance ( ) delay at high operating frequencies above GHz. For on-chip power and ground interconnections, the inductance of on-chip power grids can induce voltage drops which can cause malfunction of circuits [1]. In addition, for high-speed on-chip wires, wide-bandwidth characterization is needed. Since digital signals are trapezoidal pulses, the frequency spectrum of the signals is much wider in bandwidth than the corresponding sinusoidal signals. The frequency bandwidth of a digital signal is from dc to around, which is around the third harmonic of the digital signal, where is the risetime of the signal. The wide-bandwidth characterization results can be verified by time-domain correlation between their simulations and measurements. Hence, in this paper, silicon transmission lines are characterized using vector network Manuscript received August 23, 2005; revised October 3, W. Kim is with Rambus Inc., Los Altos, CA USA ( yousu@ieee.org). M. Swaminathan is with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA USA ( madhavan. swaminathan@ece.gatech.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TADVP analyzer (VNA) measurements, and their time-domain simulations are compared to time-domain measurements. In previous work [2] [4], characterization methods for package transmission lines are applied to silicon transmission lines under the assumption that the silicon transmission lines can be represented using the same characteristics as package transmission lines, without consideration of slow-wave effect of silicon substrate. However, it is shown in this paper that the slow-wave effect cannot be explained by the same characteristics of package transmission lines. As an example, time-domain reflectometry (TDR) characterization techniques are used for characterization of package transmission lines [5] [9], but cannot be applied for silicon transmission lines with slow-wave mode. On the other hand, VNA characterization techniques for transmission lines [10] can be applied to both package and silicon transmission lines. However, VNA characterization techniques should be carefully applied to silicon transmission lines. If VNA characterization techniques are applied for silicon transmission lines with slow-wave mode in the same way as package transmission lines, significantly frequency-variant characteristic impedance and propagation constant are extracted which are difficult to model [3], [4]. The main reason for the significant frequency-variant characteristic impedance and propagation constant can be due to the slow-wave mode of silicon substrate. In this paper, a new nonphysical resistance inductance conductance capacitance (RLGC) model is proposed to characterize silicon lines with slow-wave mode, and characterizes them with less frequency-variant parameters like package transmission lines. The slow-wave mode, characteristic impedance, and propagation constant are extracted from VNA measurements based on the nonphysical RLGC model [11]. For verifying the accuracy of the technique, co-planar lines on two silicon substrates are manufactured and characterized. The two silicon substrates are chosen based on the resistivity versus frequency chart in [12]: a wafer with resistivity cm and a wafer with resistivity cm. While the silicon substrate with a resistivity of 100 cm includes slow-wave mode, the silicon substrate with a resistivity of 2000 cm does not include slow-wave mode. Since most of the current ICs are fabricated on silicon wafers with a silicon resistivity of between and 60 cm, today s on-chip wires on the silicon wafers are affected by the slow-wave mode of silicon wafers, according to [12]. This paper is organized as follows. In Section II, the characteristic behavior of package transmission lines is discussed on the Smith chart. In Section III, TDR and VNA measurements of silicon transmission lines are discussed to explain why on-chip lines with slow-wave mode cannot be represented as package /$ IEEE

2 KIM AND SWAMINATHAN: CHARACTERIZATION OF CO-PLANAR SILICON TRANSMISSION LINES 527 Fig. 1. Transmission line represented by characteristic impedance (Z ), propagation constant (), and length (l). transmission lines. In Section IV, co-planar silicon lines without slow-wave mode are characterized using a TDR characterization technique. In Section V, the slow-wave mode, characteristic impedance and propagation constant of co-planar silicon lines with slow-wave mode are extracted using VNA measurements. Some discussion on the results follows in Section VI. II. CHARACTERISTIC BEHAVIOR OF PACKAGE TRANSMISSION LINES Package transmission lines are represented by characteristic impedance and propagation constant, as shown in Fig. 1. Then, the -parameter of the transmission line in Fig. 1 can be represented as [13]: (1) where is the length of the transmission line,, and 50 is the reference impedance of VNA measurements. For easier understanding, in (1) can be changed to Then, for real characteristic impedance, can be approximated as a circle whose center and radius are, which is especially a good approximation for. For complex characteristic impedance of a magnitude, can be still approximated as a circle on the Smith chart, but the circle is shifted along the imaginary axis. Then, two characteristic behaviors of can be observed from (2): i) as frequency increases, always rotates clockwise around from the dc point and ii) the dc point should be located between 0 and on the Smith chart, where is the reflection coefficient of at dc. The reason why rotates clockwise for both real and complex characteristic impedance is because of the exponential term in (2). The dc starting point can be calculated from the input impedance of the transmission line. Assuming that the far end in Fig. 1 is terminated with 50, the input impedance at the near end of the transmission line can be expressed as The input impedance in (3) is the impedance of in (1). From (3), the input impedance at dc,, can be expressed as (2) (3) (4) Fig. 2. Smith chart behavior of S of package transmission lines. where is the low-frequency characteristic impedance and is the attenuation constant at dc. Then, from (4), the following condition can be derived: if, ;if,. Then, based on the two characteristics of, package transmission lines show the characteristic behavior on the Smith chart in Fig. 2: If is larger than 50, should rotate clockwise around with the dc starting point between 50 and.if is smaller than 50, should also rotate clockwise around with the dc starting point between and 50.If is equal to 50, the dc starting point should be 50, which is the center of the Smith chart for a reference impedance of 50. Since package transmission lines use good conductor and dielectric material, they may have small static loss. In addition, the length of transmission lines for VNA measurement is usually a few millimeters long. Then, the loss term in (4) is negligible at dc, and then the starting point at dc is located around 50. In addition to the above two observations on for package transmission lines, observations on for package transmission lines are also possible. However, since both and in (1) are functions of the characteristic impedance and propagation constant for board transmission lines, the observations on for package transmission lines provide enough information on the characteristic behavior of package transmission lines. III. MEASUREMENT OF CO-PLANAR SILICON TRANSMISSION LINES Co-planar lines on two types of silicon substrate are manufactured and measured in this section. The cross section of the fabricated co-planar lines on silicon substrates with cm and 2000 cm resistivity is shown in Fig. 3. The silicon substrate with a resistivity of 100 cm includes slow-wave mode, but the silicon substrate with a resistivity of 2000 cm does not include slow-wave mode [12]. The thickness of metal and SiO is slightly different. The cross section of the fabricated co-planar line with cm consists of 0.2 m thickness Au, 2 m thickness Cu, 0.2 thickness Ti and 10 nm thickness

3 528 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 Fig. 5. TDR measurement of the fabricated co-planar silicon lines. Fig. 3. Cross section of the fabricated Co-planar silicon lines. (a) High-resistivity silicon lines ( = cm) (b) low-resistivity silicon lines ( = cm). Fig. 4. VNA measurement of the fabricated co-planar silicon lines. SiO on a 100 cm silicon wafer, as shown in Fig. 3. The cross section of the fabricated co-planar line with cm consists of 0.2 m thickness Au, 3 m thickness Cu, 0.2 m thickness Ti and 1 m thickness SiO on a 2000 cm silicon wafer. The co-planar lines with a length of 60 mils are measured using a VNA from 50 MHz to 10 GHz, as shown in Fig. 4. The co-planar lines with a length of 960 mils and open termination are measured using a TDR with 30 ps risetime and 250 mv amplitude, as shown in Fig. 5. From the measurements, the effect of slow-wave mode can be explained. As shown in Fig. 4, while the co-planar line on cm silicon substrate satisfies the Smith chart behavior in Fig. 2 of package transmission lines, the co-planar line on cm does not follow the Smith-chart behavior. This implies that the co-planar line on cm cannot be represented by using the same characteristics of package transmission lines due to slow-wave mode. Although rotates clockwise, the starting point at low frequency is not located between 50 and for the 100 cm resistivity silicon line. Slow-wave mode causes the shift. On the other hand, the co-planar line on the 2000 cm resistivity silicon substrate in Fig. 4 does not have the shift because it does not include slow-wave mode. Hence, the slow-wave effect can be extracted from the shift of the dc starting point. The extraction method will be explained in Section V. The effect of slow-wave mode in silicon substrate on propagating signals can be explained as a loss in the time domain. When the step pulse of a TDR equipment propagates along the co-planar silicon lines, the electric field can penetrate the silicon substrate, which causes loss by generating an electric current inside the silicon substrate. It is important to note that the direction of the induced current is in the orthogonal direction to the wave propagation direction. Since the loss caused by the electric field is in the orthogonal direction, the induced loss is not included in the attenuation constant of the transmission line. It is because the attenuation constant represents the loss of TEM waves in the wave propagation direction. In other words, it means that silicon transmission lines with slow-wave mode are different from package transmission lines with a high loss. Therefore, a new loss parameter, different from attenuation constant, is introduced for modeling the loss induced by the electric field, which will be explained in Section V. For the 2000 cm resistivity silicon line, the electric current induced by the electric field is so small that the orthogonal loss component is negligible inside the silicon substrate. For low-resistivity silicon substrates with slow-wave mode, metal planes and metal grids on silicon substrate can reduce the orthogonal loss due to the silicon substrate by preventing the electric field from penetrating the silicon substrate [14], [15]. IV. SILICON TRANSMISSION LINES WITHOUT SLOW-WAVE MODE Since the co-planar line without slow-wave mode in Fig. 3(a) follows the same behavior as package transmission lines as explained above, the co-planar silicon line can be characterized using the methods in [2] [8], [10] that can be applied to

4 KIM AND SWAMINATHAN: CHARACTERIZATION OF CO-PLANAR SILICON TRANSMISSION LINES 529 package transmission lines. In this paper, the frequency-dependent characteristic impedance and propagation constant are extracted using the TDR characterization method in [8]. From the TDR waveform of the high-resistivity silicon line in Fig. 5, the characteristic impedance and propagation constant can be extracted as Fig. 6. RLGC model for package transmission lines. where, is the frequency in Hz, is the error function, is the characteristic impedance, and is the propagation constant. The per-unit-length RLGC parameters have the following relationship with the characteristic impedance and propagation constant [2], [8]: (5) where is the real part, is the imaginary part, and is the angular frequency. Then, using (6), the RLGC model for the co-planar silicon line can be extracted as (6) (7) The RLGC model in (7) can be simulated using the W-element tabular model in Hspice. As shown in Fig. 7, the simulation results show good correlation with time- and frequency-domain measurements. The RLGC model in (7) is called nonphysical RLGC models since it shows the dependency on the attenuation constant between and [11]. On the other hand, in physical RLGC models, is defined as the resistance due to conductors, and as the conductance due to dielectrics. Therefore, and are independent parameters in physical RLGC models, having different frequency response [13]. V. SILICON TRANSMISSION LINES WITH SLOW-WAVE MODE In this section, the 100 cm resistivity silicon line in Fig. 3(b) is characterized. As shown in Figs. 4 and 5, the 100 cm resistivity silicon line shows different behavior from the 2000 cm resistivity silicon line and package transmission lines, which is due to slow-wave mode. The basic idea of the characterization is based on the claim that without the slow-wave effect, the characteristic impedance and propagation constant of the co-planar silicon line should Fig. 7. Correlation for the ( = cm) silicon line to (a) VNA measurement and (b) TDR measurement. follow the same behavior as the 2000 cm resistivity silicon line and package transmission lines. Hence, the slow-wave effect is extracted first. Then, the characteristic impedance and propagation constant are extracted from the data excluding the slow-wave mode. In this paper, a nonphysical RLGC model for silicon transmission lines which include slow-wave mode is proposed to extract the slow-wave effect, as shown in Fig. 8. Since the slow-wave mode can be explained by the orthogonal loss inside silicon substrate as explained in Section III, it can be modeled as an additional admittance, as shown in Fig. 8. In the figure, represents the orthogonal ohmic loss due to silicon substrate. In Fig. 8, and represent the behavior of package transmission lines as in Fig. 6, where and. Then, per-unit-length nonphysical

5 530 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 Fig. 8. Proposed nonphysical RLGC model for silicon lines with slow-wave mode. G(f ) represents slow-wave mode. RLGC parameters for silicon substrate with slow-wave mode can be expressed as where is the per-unit-length admittance attributed to the slow-wave effect of the high-loss silicon substrate. For package transmission lines, is negligible because of the dielectric material. For co-planar lines on 2000 cm resistivity silicon substrate, is also negligible since the silicon substrate is close to a good dielectric material. However for co-planar lines on 100 cm resistivity silicon substrate, is not negligible. Based on the nonphysical RLGC model for silicon transmission lines with slow-wave mode in Fig. 8, the slow-wave effect can be extracted from VNA measurements. Although the slow-wave effect can be frequencydependent, is assumed to be constant and realvalued in this paper. It is because it is extremely difficult to extract frequency-dependent. Since the conductor and dielectric loss of package transmission lines increases with frequency, the loss is negligible at dc. Then, the loss is dominant at dc so that the model in Fig. 8 can be reduced to a parallel resistor of and 50 termination of the other port at dc for two-port VNA measurements. Then, can be derived from at dc as (8) Fig. 9. S-parameter of the ( = cm) silicon line with and without its slow-wave mode. Then, the transmission-line parameters and in Fig. 8 can be found from the ABCD parameters using the following equations: (11) From (11), the characteristic impedance and propagation constant can be found as,. The -parameters of the coplanar line without slow-wave mode can be found with the, and (1), as shown in Fig. 9. The compensated -parameter follows the behavior of package transmission lines in Fig. 2. For simulating the co-planar silicon line, the characteristic impedance, propagation constant, and slow-wave mode are finally extracted as (9) where is the length of the measured co-planar silicon line, is at dc, and 50 is the VNA port impedance. Since the VNA measurements in Fig. 4 are performed from 50 MHz, is obtained by extrapolating the low-frequency response on the Smith chart. Then, the co-planar line on the 100 cm resistivity silicon substrate in Fig. 3(b) has S/m. Next, the characteristic impedance and propagation constant are extracted after removing the slow-wave mode from the VNA measurement data. Let the ABCD-parameter of the -parameter of silicon lines with slow-wave mode such as in Fig. 4 be written as [13] [ABCD] (10) (12) The parameters in (12) are used for the nonphysical RLGC model in (8) as follows: (13) The RLGC model in (13) can be simulated using the W-element tabular model in Hspice. As shown in Fig. 10, the simulation results correlate well with time and frequency-domain measure-

6 KIM AND SWAMINATHAN: CHARACTERIZATION OF CO-PLANAR SILICON TRANSMISSION LINES 531 Then, the characterization technique for package transmission lines in Section IV can be used for characterizing silicon lines with slow-wave mode like [2] [4]. However, characterizing silicon lines with slow-wave mode using the conventional model in Fig. 6 can produce significantly frequency-variant parameters which are difficult to model. The advantage of the proposed model in Fig. 8 is that significantly frequency-variant behaviors of silicon transmission line can be modeled using simple values such as those of package transmission lines. Another advantage of the proposed model in Fig. 8 is that the slow-wave mode is expressed explicitly, which is useful to understand the effect of silicon substrate. The other advantage of the model in Fig. 8 is that when it is needed to terminate silicon lines, the model in Fig. 8 gives the characteristic impedance for impedance matching. Fig. 10. Correlation for the ( = cm) silicon line to (a) VNA measurement and (b) TDR measurement. VII. CONCLUSION In this paper, co-planar silicon transmission lines with and without slow-wave mode have been characterized using TDR and VNA measurements. The difference between silicon and package transmission lines is explained. Silicon transmission lines without sow-wave mode can be considered as package transmission lines with a high loss, but silicon transmission lines with slow-wave mode cannot. For characterizing and simulating co-planar silicon lines with slow-wave mode, a nonphysical RLGC model is proposed. Based on the nonphysical RLGC model, the slow-wave mode, characteristic impedance and propagation constant are extracted from VNA measurements; and simulated using the W-element tabular model in Hspice. The simulation results correlate well with time and frequency domain measurements. The correlations verify the accuracy of the nonphysical RLGC model. ments. The correlations verify the accuracy of the nonphysical RLGC model for silicon lines with slow-wave mode. Comparing to the RLGC parameters for the high-resistivity co-planar line in (7), the RLGC parameters in (13) have higher and values because of the thinner SiO thickness and slowwave mode. In addition, the effective dielectric constant is increased from 4.9 to 8.2, as the name slow-wave effect implies. VI. DISCUSSION In Sections IV and V, the co-planar silicon lines on cm and cm silicon substrate have been characterized. The co-planar line on cm silicon substrate has been characterized based on the RLGC model in Fig. 6, which is represented by characteristic impedance and propagation constant. On the other hand, the co-planar line on cm silicon substrate has been characterized based on the proposed model in Fig. 8, which is represented by slow-wave effect, characteristic impedance and propagation constant. The proposed model in Fig. 8 can be transformed to the conventional RLGC model in Fig. 6 using the following relationship: (14) REFERENCES [1] Y.-S. Chang, S. K. Gupta, and M. A. Breuer, Analysis of ground bounce in deep sub-micron circuits, in Proc. IEEE VLSI Test Symp., Apr. 1997, pp [2] W. R. Eisenstadt and Y. Eo, S-parameter-based IC interconnect transmission line characterization, IEEE Trans. Compon., Hybrids Manuf. Technol., vol. 15, no. 4, pp , Aug [3] D. F. Williams, U. Arz, and H. Grabinski, Accurate characteristic impedance measurement on silicon, in Proc. IEEE MTT-S Int. Microwave Symp., Jun. 1998, pp [4] G. Carchon and B. Nauwelaers, Accurate transmission line characterization on high and low-resistivity substrates, Inst. Elect. Eng. Proc.- Microw., Antennas Propag., vol. 148, pp , Oct [5] L. A. Hayden and V. K. Tripathi, Calibration methods for time domain network analysis, IEEE Trans. Microw. Theory Tech., vol. 41, no. 3, pp , Mar [6] J. M. Jong, V. K. Tripathi, L. A. Hayden, and B. Janko, Lossy interconnect modeling from TDR/T measurements, in Proc. IEEE EPEP-94, Nov. 1994, pp [7] S. Pannala and M. Swaminathan, Extraction of S-parameters from TDR/TDT measurements using rational functions, in Proc. 54th ARFTG Conf., Fall, 1999, pp [8] W. Kim and M. Swaminathan, Simulation of lossy package transmission lines using extracted data from one-port TDR measurements and non-physical RLGC models, IEEE Trans. Adv. Packag., vol. 28, no. 4, pp , Nov [9] W. Kim and M. Swaminathan, Characterization of co-planar silicon transmission lines with and without slow-wave effect, in Proc. IEEE EPEP-04, Oct. 2004, pp [10] J. Kim and D. H. Han, Hybrid method for frequency-dependent lossy coupled transmission line characterization and modeling, in Proc. IEEE EPEP-03, Oct. 2003, pp

7 532 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 [11] W. Kim, Development of measurement-based time-domain models and its application to wafer level packaging, Ph.D. thesis, School of Electrical and Computer Engineering, Georgia Inst. Technol., Atlanta, [12] H. Hasegawa, M. Furukawa, and H. Yanai, Properties of microstrip line on Si-SiO2 system, IEEE Trans. Microw. Theory Tech., vol. MTT-19, no. 11, pp , Nov [13] D. M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, [14] B. Kleveland et al., Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design, IEEE J. Solid-State Circuits, vol. 36, no. 10, pp , Oct [15] R. D. Lutz, V. K. Tripathi, and A. Weisshaar, Enhanced transmission characteristics of on-chip interconnects with orthogonal gridded shield, IEEE Trans. Adv. Packag., vol. 24, no. 3, pp , Aug Woopoung Kim (M 96) received the B.S. and M.S. degrees in electrical engineering from KAIST, South Korea, in 1997 and 1999, respectively, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology, Atlanta, in He joined Rambus, Los Altos, CA, in 2004 and is a Senior Member of Technical Staff. He is also a Senior Signal-Integrity and Power-Integrity Engineer at Rambus. He creates channel models for packages, printed circuit boards, connectors using electromagnetic solvers and correlates with measurements in a running system as well as by using instruments such as vector network analyzers (VNAs) and time-domain reflectometry (TDR). He also performs feasibility studies for advanced signaling schemes and tradeoff analysis to make design recommendations for packages, printed circuit boards, and on-chip components. He works with the circuit team to optimize channel performance with equalization, coding, and calibrations. Prior to joining Rambus, he studied highspeed packages at the Packaging Research Center of Georgia Institute of Technology. He developed a new model and characterization technique for transmission lines. His background includes electromagnetism, optics, RF/microwave circuits, analog/digital circuits, computer architecture, communications theory, and statistics. He has about 50 publications in refereed journals and conferences. His research interests are in high-speed systems design. Madhavan Swaminathan (M 95 SM 98 F 06) received the M.S. and Ph.D. degrees in electrical engineering from Syracuse University, Syracuse, NY. He is currently the Joseph M. Petit Professor of Electronics in the School of Electrical and Computer Engineering, Georgia Tech, Atlanta, and the Deputy Director of the Microsystems Packaging Research Center, Georgia Tech. He is the co-founder of Jacket Micro Devices, a company specializing in integrated devices and modules for wireless applications where he serves as the Chief Scientist. Prior to joining Georgia Tech, he was with the Advanced Packaging Laboratory at IBM working on packaging for super computers. He has over 250 publications in refereed journals and conferences, has co-authored three book chapters, has 12 issued patents, and has 10 patents pending. While at IBM, he reached the second invention plateau. He served as the Co-Chair for the 1998 and 1999 IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), served as the Technical and General Chair for the IMAPS Next Generation IC & Package Design Workshop, serves as the Chair of TC-12, the Technical Committee on Electrical Design, Modeling and Simulation within the IEEE CPMT society and was the Co-Chair for the 2001 IEEE Future Directions in IC and Package Design Workshop. He is the co-founder of the IMAPS Next Generation IC & Package Design Workshop and the IEEE Future Directions in IC and Package Design Workshop. He also serves on the technical program committees of EPEP, Signal Propagation on Interconnects workshop, Solid State Devices and Materials Conference (SSDM), Electronic Components and Technology Conference (ECTC), and International Symposium on Quality Electronic Design (ISQED). His research interests are in mixed signal system integration. Dr. Swaminathan has been a guest editor for the IEEE TRANSACTIONS ON ADVANCED PACKAGING and IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He was the Associate Editor of the IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES. He is the recipient of the 2002 Outstanding Graduate Research Advisor Award from the School of Electrical and Computer Engineering, Georgia Tech and the 2003 Outstanding Faculty Leadership Award for the mentoring of graduate research assistants from Georgia Tech. He is also the recipient of the 2003 Presidential Special Recognition Award from IEEE CPMT Society for his leadership of TC-12 and the IBM Faculty Award in 2004 and He has also served as the co-author and advisor for a number of outstanding student paper awards at EPEP 00, EPEP 02, EPEP 03, EPEP 04, APMC 05, ECTC 08, and the 1997 IMAPS Education Award. He is the recipient of the Shri. Mukhopadyay best paper award at the International Conference on Electromagnetic Interference and Compatibility (INCEMIC), Chennai, India, 2003, the 2004 best paper award in the IEEE TRANSACTIONS ON ADVANCED PACKAGING, the 2004 commendable paper award in the IEEE TRANSACTIONS ON ADVANCED PACKAGING, and the best poster paper award at ECTC 04.