Analysis of Via Capacitance in Arbitrary Multilayer PCBs

Transcription

1 722 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 49, NO. 3, AUGUST 2007 value for a reverberation chamber with an electrically large stirrer. The method proposed in this paper suggests that the chamber can be successfully operated below this frequency, providing some careful decisions are made regarding the stirrer design and the size of the working volume. Additional work to address the application of this approach to chambers loaded with an EUT would be potentially helpful in further assessing this approach. REFERENCES [1] M. O. Hatfield, M. B. Slocum, E. A. Godfrey, and G. J. Freyer, Investigations to extend the lower frequency limit of reverberation chambers, in Proc. IEEE int. Symp. Electromagn.Compat , 1998, vol. 1, pp [2] M. L. Crawford and G. H. Koepke, Design, evaluation and use of a reverberation chamber for performing electromagnetics susceptibility/vulnerability measurements, Nat. Bur. Tech. Note, vol. 1092, Apr [3] L. R. Arnaut, Operation of electromagnetic reverberation chambers with wave diffractors at relatively low frequencies, IEEE Trans. Electromagn. Compat., vol. 43, no. 4, pp , Nov [4] H.-J. Asander, G. Eriksson, L. Jansson, and H. Akermark, Field uniformity analysis of a mode stirred reverberation chamber using high resolution computational modeling, in Proc. IEEE Int. Symp. Electromagn. Compat., 2002, pp [5] IEC , Electromagnetic Compatibility (EMC) Part 4-21: Testing and measurement techniques Reverberation chamber test methods, [6] J. Clegg, A. C. Marvin, J. F. Dawson, and S. J. Porter, Optimization of stirrer designs in a reverberation chamber, IEEE Trans. Electromagn. Compat., vol. 47, no. 4, pp , Nov [7] D. A. Hill, Boundary fields in reverberation chambers, IEEE Trans. Electromagn. Compat., vol. 47, no. 2, pp , May [8] L. R. Arnaut and P. D. West, Electromagnetic reverberation near a perfectly conducting boundary, IEEE Trans. Electromagn. Compat.,vol.48, no. 2, pp , May [9] D. I. Wu and D. C. Chang, The effect of an electrically large stirrer in a mode stirred chamber, IEEE Trans. Electromagn. Compat., vol. 31, no. 2, pp , May Analysis of Via Capacitance in Arbitrary Multilayer PCBs Miroslav Pajovic, Jinghan Yu, and Dragan Milojkovic Abstract The signal layer transitions at regions of multilayer printed circuit boards, where high-speed signal lines switch between two signal layers, may affect the board circuit s signal integrity and electromagnetic compatibility. This study has been focused on the analysis and extraction of values of parasitic capacitance of various designs of through-hole and micro vias as signal layer-changing devices, which are common in practice. The via capacitance is analyzed conceptually by using lumped circuit models for electrically short vias, numerically by the computational calculations based on the transmission line modeling method, and experimentally by laboratory measurements using a vector network analyzer and an LCR meter. Index Terms Lumped circuit models for vias, signal layer transitions in multilayer printed circuit boards (PCBs), signal line discontinuities, via parasitics. Manuscript received February 3, 2006; revised December 12, This work was supported by the EMC Compliance Engineering Group of DSSTG of Cisco Systems, Inc. The authors are with Cisco Systems, Inc., San Jose, CA USA ( mpajovic@cisco.com; jinyu@cisco.com; dmilojko@cisco.com). Digital Object Identifier /TEMC I. INTRODUCTION Signal integrity and electromagnetic interference (EMI) investigations of modern high-speed digital circuits present serious challenges for multilayer printed circuit board (PCB) designs. With everincreasing clock frequencies, data rates, and integrated circuit densities and decreasing signal rise/fall times, signal integrity of PCB circuits require careful considerations. The signal lines need to be well impedance-matched to their drivers, loads, or to other signal lines in order to have minimal effects from discontinuities. One of the typical line discontinuities in high-density PCBs are signal layer transitions or interlayer connections, made by the vias. Intrinsic to all vias are their parasitic capacitances and inductances that create discontinuities in the signal lines. These discontinuities with presence of the PCB resonance effects may lead to additional signal delay, signal reflections, parasitic electromagnetic propagation, and resonance effects in PCBs that consequently lead to signal distortions, crosstalk, and EMI problems as discussed in [1] [6]. In addition to the via inductance and PCB resonances, the via capacitance may have negative impact on signal integrity of high-speed digital signals in multilayer PCBs, especially when transmission lines have more signal vias, as explained in [1, Ch. 5]. Other useful analyses of via capacitance are given in [7] [9]. In this paper, we have shown the via capacitance models for various physical via designs, which are common in industry, with variety of via radius, via lengths, via clearance to the board planes, and number of stacks per via length. Furthermore, we have used the method for the extraction of the via capacitance values that is based on a concept of the lumped circuit models for the signal via. These via models and via capacitance extraction methods are confirmed by the transmission line modeling (TLM) and simulation method, and by laboratory measurements using a vector network analyzer (VNA) and LCR meter. II. PHYSICAL AND CIRCUIT MODELS FOR VIAS For typical multilayer PCB structures with a signal line transition, the equivalent hybrid circuit is shown in Fig. 1(a). Here, C svt is the total via capacitance that includes the capacitances of the signal via body, via pads, and parts of the signal line located on the signal layers next to the signal via. L svt is the inductance of the signal via including the inductances of the signal line parts next to the signal via in the antipad via area. The [Z pcb ] represents the distributed network associated to the PCB, which acts as a parallel-plane resonator. The plot of the magnitude of the impedance Ẑ11 of the circuit in Fig. 1(a), obtained by the TLM method (a dashed curve) and by the VNA measurements (a solid curve), is shown in Fig. 1(b). The simulations and laboratory measurements are performed on the test PCB with the dimensions a b H =50mm 50 mm 2.7 mm. The signal via is one of the typical industry samples that has the following parameters: the number of signal via pads is 3, the via length is H =2.7mm, the via body radius is r =0.15 mm, the via pads radius is R p =0.29 mm, and the via antipad radius is R ap =0.42 mm. The relative dielectric constant and the loss tangent of the PCB substrate at 10 GHz are 3.9 and 0.016, respectively. The physical via model, which is formed by a signal via and a ground via spaced by 25 mm, and the VNA setup for measuring the S 21 parameters of the open-ended signal via, are shown in Fig. 2. The actual plot of the impedance Ẑ11 was obtained by measuring the S 21 parameter, and by converting this parameter to the impedance Ẑ11 using (1) as Ẑ 11 Ŝ jωl p. (1) 2 1 Ŝ /$ IEEE

2 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 49, NO. 3, AUGUST Fig. 2. Setup for measuring the via impedance Z11 (the ground pins of the probes P1 and P2 are shorted together, and are connected to the PCB top ground plane). Fig. 3. (a) (c) Evolution of the quasi-static via capacitance model. Fig. 1. (a) Hybrid via circuit model. (b) TLM-simulated (dashed curve) and VNA-measured (solid curve) impedance magnitude of the open-ended signal via. L p is the inductance of the VNA probes that is assumed to be zero after the VNA calibration. The measurement method of the impedance Ẑ 11 of parallel plane structures is given in [10]. Propagation and cavity effects inside of the parallel-plane PCB structure produce multiple resonances inside the PCB that are shown in the plot of Fig. 1(b). Starting from 3 GHz and going to 9.5 GHz, the resonance peaks belong to the even resonance modes: (2, 0)/(0, 2), (2, 2),..., (6, 2)/(2, 6). Analysis of the PCB cavity effects on signal lines performance will be the topic of our future work. For low frequencies, below the PCB resonances, the PCB exhibits the quasi-static behavior and behaves as a parallel-plane capacitor C p. The typical value of ground via inductance is in the order of nanohenry or less. Consequently, the circuit model in Fig. 1(a) will look as in Fig. 3(a). At low frequencies for common industrial PCBs, where the via inductance and the interplane PCB capacitance dominate the via capacitance (i.e., ωl v << 1/(ωC svt ) and 1/(ωC p ) 1/(ωC svt ), the equivalent circuit in Fig. 3(a) leads to the total via capacitance C svt, as shown in Fig. 3(c). A. Extraction of Via Capacitance At low frequencies, we can neglect the influence of PCB dielectric losses on the via impedance. Therefore, below 1 GHz in the plot of Fig. 1(b), the impedance of the signal via relates mostly to the total signal via capacitance C svt, and the magnitude of this impedance may be expressed by Ẑ = 1. (2) 2πfC svt We used this equation for extracting the total via capacitance values from the impedance Ẑ below 1 GHz obtained by TLM calculations. III. PRACTICAL VIA MODELS, VIA CAPACITANCE COMPUTATIONS, AND LABORATORY MEASUREMENTS To obtain the values of via capacitance from practical via models, an experimental platform was designed specifically for this research work. We made laboratory measurements on the platform by VNA and LCR meter. Also, we have performed the computational calculations of the impedance Ẑ by the TLM software, and using (2), we have extracted the signal via capacitance values. A. Measurement of Via Capacitance We have obtained measurement of the via capacitance by the VNA, Agilent N5230A PNA, and by the LCR meter, Protek Z9218. The via capacitance is directly read out by the VNA, in Smith-chart-impedance mode at 100 MHz and by the LCR meter at 100 khz. The measurements are performed at the experimental platform with 17 test vehicles with dimensions 50 mm 50 mm, and the corresponded measurement results are given in Tables I IV. B. Initial Model for Signal Via For cases of signal lines with a signal layer transition, the different via physical models will be derived from the initial via model shown in

3 724 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 49, NO. 3, AUGUST 2007 TABLE I VARIATION OF THE NUMBER OF VIA PADS AND THE VIA LENGTH TABLE II INDUSTRIAL VIA SAMPLES WITH THREE PADS FOR STRIPLINELAYER TRANSITIONS Fig. 4. PCB with the 14-pad signal via. TABLE III VARIATION OF THE RADIUS OF THE VIA ANTIPAD R ap Fig. 5. PCB with the three-pad signal via. TABLE IV VARIATION OF THE NUMBER OF REFERENCE PLANES ALONG THE VIA PCB stackup, and the resulting average relative dielectric constant is ε avr 4, and the average loss tangent is 0.02 at 500 MHz. We used material vendor numbers to estimate the average values of relative dielectric constant and loss tangent for PCB models. Fig. 4, by varying the number of pads n on the via, radiuses r, R p,r ap, the via height H, and the number of reference planes N. The signal via model, which is implemented in the PCB with dimensions 50 mm 50 mm 2.7 mm, is one of the typical industry samples, and has the following parameters: r =0.15 mm (6 mils), R p =0.29 mm (11.5 mils), R ap =0.42 mm (16.5 mils), H =2.7 mm (105 mils), n =14,and N =12. The PCB dielectric thicknesses h and h1, are mm ( 10 mils) and 0.13 mm ( 5 mils), respectively. The thickness of the reference planes, signal lines, and via pads is mm (0.65 mils or 0.5 ounce). The parts of the signal line next to the signal via are mm ( 5 mils) wide and (R ap R p )=0.13 mm long. In our test models, relative dielectric constants and loss tangent of the PCB substrates between reference planes differ through the C. Effects of Via Physical Parameters on Via Capacitance and Computational and Measurement Results The effect of the via pad on via s capacitance was analyzed by reducing the number of pads in the via model, shown in Fig. 4, from a total of 14 to 2 via pads, as shown in Fig. 2. All other via parameters such as r, R p,r ap,h,and N stayed unchanged. TLM method calculation results and VNA and LCR measurement results of the via capacitance for 14, 4, and 2 pads are shown in Table I. The effect of via height on via capacitance was analyzed by reducing the height of the through-hole via in Fig. 5, while the other via parameters stayed unchanged. After reducing the height from H = 2.7 mm (105 mil) to H 1 =0.3 mm (12 mil), the corresponding micro via is shown in Fig. 6. TLM method calculation results and VNA and LCR measurement results of the micro-via capacitance are presented in Table I. The effect of via body radius r, via pads radius R p, and via antipad radius, R ap, was analyzed on the via model shown in Fig. 5, with several typically industrial via sizes for the three-pad via, by changing the parameters r, R p,andr ap while other model parameters stayed unchanged. The corresponding TLM method calculation results and VNA and LCR measurement results of via capacitance are shown in Table II.

4 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 49, NO. 3, AUGUST Fig. 6. PCB with the micro signal via. and the radius of via body. The coax-form (3a) is used when the capacitance of via pads dominates the capacitance of via body the case when via has a maximized number of pads. The coax-form (3b) is used when the capacitance of via body dominates the capacitance of via pads the case when via has a minimized number of pads. Also, in the last row of Table I, we added values of via capacitance calculated by [1, Eq. (5.1), Ch. 5]. We may see that for the long via with the maximized number of via pads (14), when the capacitance of via pads dominates the capacitance of via body, then (5.1) in [1] gives solid results from practical engineering standpoints. But, for the long via with the minimized number of via pads (2 to 4), the coax-form equation gives pretty more accurate results than (5.1) in [1]. This is because the capacitance of via body dominates the via pad capacitance for vias with the minimized number of via pads. For short (micro) vias, both the equations give solid results. In this case, we used (3a) because the capacitance of via pads dominates the capacitance of via body. Fig. 7. Two-layer PCB with the three-pad signal via. The effect of via antipad radius R ap, on via s capacitance was analyzed by changing the R ap of the 3-pad-via also in Fig. 5, with standard parameters r =0.15 mm (6 mils) and R p =0.29 mm (11.5 mils). The corresponding TLM method calculation results and VNA and LCR measurement results are shown in Table III. The effect of the density of reference planes, which the via passes in the PCB, on the via capacitance was analyzed by gradually reducing the number of reference planes from 12 to 2 on the three-pad-via model. After the removal of 10 reference planes, the last via model, with only two reference planes, is shown in Fig. 7. The corresponding TLM method calculation results and VNA and LCR measurement results for via capacitances are shown in Table IV. D. Analytical Estimation of Via Capacitance In general, by increasing the number of reference planes along a via, the via structure approaches a coaxial form. Practically, the via structure will reach the coaxial form when the spacing between the adjacent PCB reference planes is small and comparable to the spacing between via and the reference planes, i.e., (R ap r). For a numerical comparison, the capacitance of the related coaxial structure, calculated approximately by the coax-form (3a) and (3b), are added in Tables I IV H C coax =2πε r ε 0 ln ( R ap ) (3a) R p H C coax =2πε r ε 0 ln ( R ap ) (3b) r where ε r and ε 0 are the relative dielectric constant of PCB substrate and the dielectric constant in air, respectively. H, R ap,r p, and r are the via length, the radius of via antipad, the radius of via pad, IV. CONCLUSION In addition to the via inductance and PCB resonant cavity effects, the signal via parasitic capacitance in high-speed signal lines may cause signal integrity problems at high-speed PCB circuitries. This work analyzed vias and signal layer transitions in arbitrary multilayer PCB structures with emphases on the via capacitance that can not be ignored in high-speed PCB design. As it was shown in this paper, many physical and electrical parameters of the PCB and signal vias have considerable influence on the via parasitic capacitances. The negative effect of via capacitance cannot be neglected, but it can be minimized by controlling relevant via and PCB parameters. We analyzed a variety of via designs and their contribution to the via capacitance. The right approach to minimize the capacitance of the through-hole via is first to reduce the number of via pads (i.e., to eliminate the unused via pads). Minimization of the via capacitance by increasing clearance between the via and PCB reference planes is not always an effective solution due to the requirement that the reference planes should be solid planes for the associated high-speed signal lines, which are passing between the vias. However, the most effective solution to minimize the via capacitance is using micro via constructions (short vias), but this solution is sometimes limited by other factors such as higher PCB production cost. ACKNOWLEDGMENT The authors would like to thank J. Fisher, Engineering Manager from Cisco Systems, Inc., San Jose, CA, for supporting successful laboratory measurements; and F. Centola, EMC Application Engineer from Flomerics, Inc., Santa Clara, CA, for great help on the TLM computational modeling and simulations. REFERENCES [1] S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed System Digital Design. New York: Wiley, [2] C. Schuster and W. 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5 726 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 49, NO. 3, AUGUST 2007 balanced TLM and via coupling model, in Proc. IEEE 12th Top. Meet. Electr. Perform. Electron. Packag , Oct. 2003, pp [6] J. S. Pak, M. Aoyagi, K. Kikuchi, and J. Kim, Band-stop effect of power/ground plane on through-hole signal via in multilayer PCB, IEICE Trans. Electron., vol. 89-C, no. 4, pp , Apr [7] J. S. Kasten et al., Enhanced through-reflect-line characterization of twoport measuring systems using free-space capacitance calculation, IEEE Trans. Microw. Theory Tech., vol. 38, no. 2, pp , Feb [8] T. Wang et al., The excess capacitance of a microstrip via in a dielectric substrate, IEEE Trans. Comput.-Aided Des., vol. 9, no. 1, pp , Jan [9] T. Wang et al., Quasi-static analysis of a microstrip via through a hole in a ground plane, IEEE Trans. Microw. Theory Tech., vol. 36, no. 6, pp , Jun [10] I. Novak, Measuring milliohms and pico-henrys in power-distribution networks, presented at the DesignCon2000, Santa Clara, CA.