Zuowei Shen, Jian Tong Avago Technologies 350 West Trimble, San Jose, CA, USA, 95131

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1 Signal Integrity Analysis of High-Speed Single-Ended and Differential Vias Zuowei Shen, Jian Tong Avago Technologies 350 West Trimble, San Jose, CA, USA, Abstract "Coaxial-like" single ended vias As data communication speed increases beyond 10 Gbps, In the printed circuit board, high speed signals are usually designing for optimal signal integrity becomes critical to carried by 50 ohm transmission lines. The most popular ensure reliable data. In the high speed board/package design, transmission lines are microstrip line and stripline, which designers are trying to eliminate or minimize all the carries quasi-tem or TEM wave between the two conductors, impedance mismatches along the high speed signal path. which are the trace and reference plane. When the signal trace When multilayer board is used to increase the signal density, need to go to another layer, via is usually used as the layer via structures are unavoidable to connect the signal, ground interconnect. The signal vias, whose impedance is usually 25- and power supply traces on different layers. High speed via 35 ohm, can result in a significant impedance discontinuity. transitions usually bring impedance discontinuities with them The discontinuity comes from the field discontinuity at the which will cause signal reflections and distortions transition from the two conductor transmission lines to the compromising signal integrity. The deterioration of signal single radial transmission lines. There is no signal return path integrity will generate additional jitter and decrease the data at the via except at the power and ground plane. If we use eye opening ultimately jeopardizing the reliability of the data. inductance and capacitance to characterize transmission lines, This paper addresses designing for signal integrity at 10 Gbps the impedance mismatch comes from the dramatic capacitance by comparing the signal integrity of single ended and changes at the via transition. differential through-hole vias for the designer. In each case, the impedance mismatch at the via transition can be minimized by optimizing a few parameters such as pitch size, via diameter, via height, excess via stub, antipad size and ground via locations. The impacts of these parameters are investigated with the help for a full-wave electromagnetic simulation and verified by measurements. Introduction Given the increasing data rate and increasing operating frequency of the high speed digital systems, rules of thumb are no longer valid for designers, especially for 3-D structures like vias. A thorough understanding of the impacts of the via parameters and valid modeling is the key to minimize the impedance mismatch caused by the vertical vias. In modem PCB design, there are several types of vias structures which include through-hole via, blind via, buried via and microvias [1]-[ 11]. This paper focuses on the most common and inexpensive via structure, which is through-hole via. The critical mechanical parameters are via diameter (drill size), pad diameter, via height, pitch size, antipad on ground/power plane, ground via configurations, ground via locations and the Fig. 1. coaxial-like" via composed of one signal via and four excess via stub. Additionally, signal integrity performance round vias optimization is limited by design rules such as stack up, g minimal pitch size, minimal drill size and room available on the PCB boards. Some analysis has been done on designing coaxial like via In this paper, the via performance is evaluated to by control the via impedance and minimize the impedance comparing the scattering parameters. and S22 in frequency mismatch in [12]. This new structure creates vertical coaxial domain and TDR in time domain. A 3D EM SOLVER is used transmission line and its impedance is controlled by the via to moeh relcin ineto los an copln ofthoser diameter and the distance from ground vias to center signal vias. Fis the ',,,., vias. The surrounding vias provide the Frtnesingle end via is investigated by varying theg signal g return path. An nubro gron via aron th sina via Diffrenia via inductance loop is formed between signal vias and the ground ar sdmre freunl tha sigl ene via in optical vias. The capacitance is also homogeneous vertically because communication~~~~ cicis so intescn eso,th.mat the antipad is connected with the ground vias, so that there is of th mehnia paaetr on th difeenia vi reur loss no dramatic capacitance change at the ground/power plane. an ineto los ar describe.othe poeta sina Vias designed with this technique can control the impedance integrity issues caused by vias are described in the. third,., mismatch ineconcwithin sinfcaty 400, which reduce the reflections at the via session /08/$25.00 )2008 IEEE 65

2 But unfortunately, due to the increasing component density 0.16 mm wide. The drill hole size is 0.2 mm. The distances on the printed boards, the 5-via coaxial-like structure can not between the ground vias and the signal vias are all 0.8mm in always be applied due to the space limitation. For example, the test board shown in Fig.2. One through trace on the left when 0.2mm diameter through hole via is used as the signal without via is measured as a reference to demonstrate the via, the distance between the signal and ground vias need to be performance deterioration caused by vias. 0.8 mm to match 50 ohm microstrip line. And this coaxial Fig.3 shows the insertion loss S21 for the above 5 fixtures. structure will need 1.8mm x 1.8mm room on PCB, which is We can see clearly that the more ground vias used, the more not favored in the modem high density board design. One transparent the via transaction is. The four via coaxial like via trade off can be done is to keep the vertical channels, but structure introduces less signal attenuation than other reduce the surrounding ground via numbers. structures. And when there is only one ground via, we can see there are obvious resonances and reflections when the high speed signal goes through vias. The four vias performs like an electrical wall, which both provides signal return path and I I+ i : electrical shielding which reduces vertical couplings between es ~~~~ m sl_14 S11_3 S(1,1) indb Fig.2. Test board, (a) through trace (b) 4 ground vias (c) 3 70 ground vias (d) 2 ground vias (e) 1 ground via O.OE+00 5.OE E E+10 IS (2,)1 in db Frequency /Hz 0 (a) Measured return loss at SMA connector for different via -0.5 configurations -1 S-Parameter Magnitude in db m -2 t Xll l ,I.,,, S12_3 S ndi S12_ s I 1 t l O.OE+00 5.OE+09 1.OE E+10 SI O Frequency / Hz t Fig.3. Measured insertion loss (S21) when different number of Frequency I GH2 ground vias are used (b) Simulated return loss for different via configurations Fig.2 shows the test board for the four via configurations with different numbers of ground vias surrounding the signal Fig.4. Return loss (S1l) when different number of ground vias via. They are used to connect the traces on the top and bottom are used layers. The board is 1mm thick, and the high speed trace is 66

3 also the antipad for signal vias. [13] A lot of simulations have been done to demonstrate how those parameters affect the impedance with the help of a full-wave 3-D electromagnetic solver. Fig. 6 shows the differential via structure and the parameter definitions. The G-S-S-G configuration via transition is assumed to use 0.2mm diameter drill vias and 0.45 mm via pad. The 6-layer board is 1.5mm thick, and the differential trace has 0.3 mm trace width and 0.5 mm spacing. First the common mode and differential mode return loss and insertion loss at the via transition with and without the ground vias are compared in Fig.7 and Fig.8. Both gap and via pitch is 0.8 mm in this model. In the simulation, mode 1 is differential mode and mode 2 is common mode. By adding the two ground vias, the attenuation for both common mode IS2(2),1(2)1 and differential mode signals JS2(1),1(1)J are reduced, and less reflection occur at the transition too. Fig.4 shows the return loss S1l. Fig.4 (a) is the measured results for the above test fixture, and the return loss measures the reflection and impedance mismatch at the SMA connectors. It includes both the reflection at the vias and the cavity resonance between the SMA pair. Even though, it is easy to observe that the impedance discontinuity is smaller for the 36mm signal path where more ground via is used. Fig.4 (b) is the simulation results of the return loss of the via transitions. The 3-D EM model includes the via transition and 6mm high speed trace at each side. The simulation can compare the via structure return loss better by eliminating the impedance discontinuity at the SMA connectors. When more ground vias are applied, the return loss is better. For example, at 5 GHz, the return loss is db for one ground via structure, and db for four ground vias structure. Besides the S-parameter in frequency domain, the TDR are simulated and measured too. Fig. 5 presents the impedances of the via transitions with different numbers of ground vias. As the number of ground vias increases, the measured impedance drop from 60 ohm to 52 ohm. The simulated impedances show TDR #70ogo d i 65 lgdidmeasurementspme Simuia tion ~60 E o~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fig. 6. Differential via structure and parameter definition #of ground vias S-Parameter Magnituide in d Differential vias. Differential traces are widely used in high speed circuit designs. They are very attractive because of their inherent noise and common mode signal rejection feature and good EMI performance with the field canceling at far field. Smiliar to single ended vias, when differential traces need to route from one layer to another one, differential vias are needed as the interconnect. Different from single ended via, the differential signal on one of the differential via pair will actually return at the other via. The impedance discontinuity here actually is better than the case for single via transition. But when the common mode signal is considered, again, we will find that the return path is missing. One realistic way to improve this discontinuity is to add two ground vias close to the differential signal vias. In this configuration as shown in Fig.6, the impedance of the via transition is determined by several parameters, which include the via drill size, via pad size, pitch, distance between ground via and signal vias, and / -f v s, 5 10 S 2_2_//2 Frequency / GHz Fig.7. Comparison of the return loss Si1 at the via transition with and without ground vias The gap between the signal vias and ground vias are then varied from 1.2 mm to 0.6 mm to optimize the via impedance. By comparing the scattering parameters, it is found that when the ground vias are closer to the signal vias, the insertion loss 67

4 1~~~~~~~~~~~~~~~~~~~~~~ S2, 1I in db is smaller, and so is the reflection. The ground vias help both -0 differential and common mode impedance matching. But gap between ground and signal vias is limited by the via pad \pitch 1.2 diameter and the clearance requirement, so 0.6mm is the r r smallest value we can use. If smaller via pads are available, some optimal distance between signal via and ground via will be found, and when the gap is smaller than this distance, the differential return loss will become worse. So in packaging design allowing micro-vias, trade off need to be made between differential and common mode impedance matching when design the gap between signal vias and ground vias. S-Parameter Magnitlde in db o 15 S2(2,1(2_) Frequency J GHz Fig. 10. Comparison of the differential mode insertion loss S21 at the via transition with pitch variations - (t S 2 ) I(1) -0' > 1 After the gap is fixed, the pitch size is varied to optimize '2(2>,1(2): -1 3:09 Ithe differential impedance, which is very critical in the high S2t','1'') t(2''1') nognd speed circuit design. From Fig.9 and Fig.10, a clear trend is 3 X- found that smaller pitch size results in better impedance match. The differential return loss is smaller than -20dB up to 18GHz when pitch is 0.6mm and 8 GHz when the pitch size is Frequency / GHz 1.2mm. The insertion loss also doubles when the pitch size change from 0.6 mm to 1.2 mm. But even the pitch is decreased to the minimum allowed pitch 0.6mm, the Fig.8. Comparison of the insertion loss S21 at the via differential impedance is still smaller than 100 ohm with this transition with and without ground vias stackup. The 100 ohm differential impedance should be ISi,11 in db achieved when the pitch size is smaller than the differential _5 trace spacing, we can not use that smaller pitch size due to the _ ~~~~~~~~~~~~~~~~~~~~~~~pitch h-r C, =06 pitch 1.2 S (2)t(2) in -5 pit_h _L ~-~~[T ~~ ~~-~ ~-~~-~ -1o~~~~~~~~~~~~~~~~--~~~~~ ptc -65 ~~~~~~~~~~~~~~~-20 / -- O tie-25 Frequency I GHz Fig.9. Comparison of the differential mode return loss Si1 at C the via transition with pitch variations Frequency / GHz Fig Comparison of the differential mode return loss 511 at the via transition with pitch variations 68

5 132(2)1(2) IS differential vias pairs. Ground vias can be used to separate pitch T, l differential vias pairs to reduce the vertical coupling. pitch =9 Conclusion 0.95 In this paper, approaches to optimize the single ended and differential via transitions are described. When two or more vias are placed around the signal via, the impedance 0o discontinuity at the single ended via transition can be improved significantly. For differential vias, to make its differential impedance 100 ohm, parameters like pitch size, 0.85 gap between ground vias and signal vias, via diameter, and antipad need to be optimized carefully through modeling. Usually, limited by the printed circuit fabrication design rules, o 8 smaller gap and pitch size and larger antipad bring better impedance match. 75 cknow ledgm ent The authors would like to thank A. Engel, C. Cummings, and S. Hart from Avago Technologies, Inc., San Jose, CA, for Frequency I GHz valuable discussions and great support on this research; and M. Teman from Avago Technologies for laying out PCBs with Fig.12. Comparison of the common mode insertion loss S21 at the via designs presented in this paper. the via transition with pitch variations Reference 1. Richard, Weng Yew Chang; See, Kye Yak; Chua, Eng Fig. 1ad f ows ho the via pitch Ffet the Kee, "Comprehensive Analysis of the Impact of via common mode performance at thertion Fromp the Design on High-Speed Signal Integrity," Electronics common mode return loss and insertion loss comparison, Packaging Technology Conference, 2007, pp , 10- differential via with smaller pitch can provide us better 12 Dec differential impedance matching but will have worse common 2. T. Wang, R. F. Harrington, and J. R. Mautz, "Quasistatic mode performance. analysis of a microstrip via through a hole in a ground Based on the above investigation on how those geometric plane," IEEE Trans. Microwave Theory Tech., vol. 36, pp. parameters affect the via impedance, we get the conclusion , June that usually on PCB, smaller pitch gives better differential 3. S H. Hall, G. W. Hall, and J. A. McCall, High-Speed performance and worse common mode performance. We need System Digital Design. New York: Wiley, to do trade off when we optimize the differential via 4. C. Schuster and W. Fichtner, "Parasitic modes on PCBs impedance and also need to meet common mode return loss and their effects on EMC and signal integrity," IEEE specification. On package design, vias are much shorter, and Trans. Electromagn. Compat., vol.43, no. 4, pp , their hole size and pad size are smaller too. The discontinuity Nov at the via transition on package is not as significant as those on PCB, but the circuit density brings other potential issues at 5 J S. Pak and J. Kim, "3 GHz through-hole signal via vias. model considering power/ground plane resonance coupling and via neck effect," in Proc. Electron. Compon. Technol. Other possible high speed via issues Conf., 2003, pp There are also other parameters that can affect the 6. J. Kim, J. Kim, M. D. Rotaru, K. C. Chong, and M. K. reflection and attenuation at the via transition. For example, Iyer, "Via and reference discontinunity impact on highlonger via on multilayer PCB board will introduce more speed signal integrity," in Proc. IEEE Int. Symp. discontinuity with larger insertion loss and reflection. Smaller Electromagn. Compat., Aug. 2004, vol. 2, pp drill size and via pad can match the narrow differential trace 7. J. S. Pak, J. Lee, H. Kim, and J. Kim, "Prediction and better but costs more. The via antipad, also called clearance verifcation of power/ground edge radiation excited by hole, is another key parameter designers need to optimize through-hole signal via through balanced TLM and via during the design phase. Appropriate antipad usually results in coupling model," in Proc. IEEE 12th Top. Meet. Electr. better impedance matching for both single ended and Perform. Electron. Packag , Oct. 2003, pp differential vias by reducing the capacitance. Also, we need to 8. J. S. Pak, M. Aoyagi, K. Kikuchi, and J. Kim, "Band-stop pay attention to the via stub, and try to eliminate it or keep it effect of power/ground plane on through-hole signal via in short. The via transition stub usually looks capacitive when it multilayer PCB," JEICE Trans. Electron., vol. 89-C, no. 4, is short. The worst case is when the stub is quarter wavelength pp , Apr at an important frequency, and the stub performs like a short 9M.PjvcJẎu'.Mljoi,"nlsso i circuit at that frequency, then the reflected signal will cancel Capacitance in Arbitrary Multilayer PCBs", IEEE Trans. OUt the original signals. In this way, a resonance shows up at Elcrmg.Cma. o.4,n.3 p 2-2,Ag this critical frequency. [14] In package design where vias are 20 close, crosstalk may come from the vertical coupling between

6 10. T. Wang et al., "The excess capcitance of a microstrip via in a dielectric substrate," IEEE Trans. Comput.-Aided Des., vol. 9, no. 1, pp , Jan T. Wang et al., "Quasi-static analysis of a microstrip via through a hole in a ground plane," IEEE Trans. Microw. Theory Tech., vol. 36, no. 6, pp , Jun Thomas Neu, "Designing controlled-impedance vias", pp , EDN, Oct 2, Lawrence Williams, Steve Rouselle, Bryan Boots, "Circuit-board design for 10-Gbit XFP optical module", pp.63-70, EDN, May 29, Zaw Zaw Oo; Liu Enxiao; Wei Xing Chang; Li Erping; Chua Eng Kee; Li Le-Wei, "Novel Co-Simulation Method for Analysis of Power Integrity and EMI in Electronic Packages with Large Number of Power/ground Vias," Electronics Packaging Technology Conference, 2007, pp , Dec