544 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 3, AUGUST /$ IEEE

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1 544 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 3, AUGUST 2008 Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model Jaemin Kim, Youchul Jeong, Jingook Kim, Junho Lee, Chunghyun Ryu, Jongjoo Shim, Minchul Shin, and Joungho Kim Abstract A hierarchical power distribution network (PDN) consists of chip, package, and printed circuit board (PCB) level PDNs, as well as various structures such as via, ball, and wire bond interconnections, which connect the different level PDNs. When estimating the simultaneous switching noise (SSN) generation and evaluating PDN designs, PDN impedance calculation is an efficient criterion. In this paper, we introduce two new kinds of modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation, especially for hierarchical PDN. First, we propose a modeling procedure to add an interlevel electromagnetic coupling effect between PDNs of different levels, based on the resonant cavity model and segmentation method. In order to effectively consider the interlevel electromagnetic coupling effect, we introduce a new concept of interlevel PDN, which is, for example, composed of a metal plate in the package-level PDN and a metal plate in the PCB-level PDN. Next, we present a modeling procedure to include the fringing field effect at the edge of small-size PDN structure, which causes a considerable shift of cavity resonance frequencies in the PDN impedance profile. In order to verify the proposed modeling approaches, we have fabricated a series of test vehicles by combining two package-level PDN designs with a PCB-level PDN design. Finally, we have successfully validated the proposed modeling approaches with a series of frequency-domain measurements in a frequency range up to 5 GHz. Index Terms Fringing effect, hierarchical power distribution network (PDN), interlevel electromagnetic coupling, interlevel PDN, PDN impedance, resonant cavity model, segmentation method, simultaneous switching noise (SSN). I. INTRODUCTION T HESE days, hundreds of millions of transistors are integrated into a single chip, and they consume a large amount of instantaneous switching current [1]. Consequently, this sudden switching current can induce a significant amount of simultaneous switching noise (SSN) at the chip, package, Manuscript received March 7, 2007; revised October 1, 2007; January 22, Published August 6, 2008 (projected). This work was supported by the IT Research and Development program of MIC/IITA (2005-S , Development of High-Performance and Smallest SiP Technology). This work was recommended for publication by Associate Editor L.-T. Hwang upon evaluation of the reviewers comments. The authors are with the Terahertz Interconnection and Package Laboratory, Korea Advanced Institute of Science and Technology (KAIST), Daejeon , Korea. Digital Object Identifier /TADVP Fig. 1. (a) Side view of the hierarchical PDN. (b) Block diagram of the hierarchical PDN studied in the paper. and printed circuit board (PCB)-level power distribution networks (PDNs). This SSN has become a major source of timing jitter and skew problems at high-speed serial input output (I/O) channels and clock distribution networks, and electromagnetic interference (EMI) and noise coupling problems in high-density mixed signal integrated systems [2] [6]. When estimating the SSN generation and evaluating the PDN designs in high-speed semiconductor system designs, PDN impedance calculations at locations in the multilevel PDN are found to be an efficient criterion. Therefore, precise estimation of the PDN impedance at locations of each level in a system is a critical prerequisite for a secure and dependable design of semiconductor systems. Usually, the PDN of a system is formed by a combination of multiple level networks forming a hierarchical interconnection structure, as illustrated in Fig. 1. The hierarchical PDN consists of a chip, a package, and PCB-level PDNs (as shown in Fig. 1), as well as various interconnection structures (via, ball, and wire bond) that connect the different level PDNs to form a single hierarchical PDN. Therefore, when estimating the hierarchical PDN impedance, it is necessary to obtain the impedance profile of each level PDN and to add electrical models of the interconnection structures to connect the PDNs. In addition, high-frequency electromagnetic coupling between the different level PDNs must be considered to guarantee accurate estimation of the hierarchical PDN impedance level and profile, including /$ IEEE

2 KIM et al.: MODELING AND MEASUREMENT OF INTERLEVEL ELECTROMAGNETIC COUPLING AND FRINGING EFFECT 545 position or shift of resonance frequencies. The interlevel electromagnetic coupling occurs through conductive paths of via, ball, and wire bond, and through parasitic electromagnetic coupling paths between metal plates at different levels PDNs. The most commonly used approach to calculate the impedance of the hierarchical PDN is a full-wave simulation method such as the finite difference time domain method (FDTD), finite element method (FEM), and method of moments (MOM). This approach can offer impedance calculations through the flexible manipulation of the simulation conditions and can provide accurate simulation results. However, it requires excessive time and a large amount of computational resources to analyze the hierarchical PDN. In particular, it is extremely difficult, perhaps even impossible, for the multilevel hierarchical PDN to apply the full-wave simulation method, as the multilevel hierarchical PDN has a large dimensional variation between the different levels PDNs. In order to overcome these difficulties of the full-wave simulation methods, the use of analytic modeling methods based on a resonant cavity model, or a segmentation method have been actively suggested. A notable superiority of the resonant cavity model is based on the fact that it can offer very fast and accurate calculation results in the PDN impedance calculation, especially in the case of large dimensional, rectangular shaped PDNs [7] [9]. Meanwhile, the segmentation method can analyze complicated structures, such as arbitrary shapes or structures, by combining various shapes. These complicated structures cannot be analyzed using only the resonant cavity model [10] [13]. By taking advantages of both the resonant cavity model and the segmentation methods, there have been several proposed approaches to analyze the PDN impedance profile of a two-layer PCB [14], power bus noise isolation structures in multilayered PCBs [15] [17], and estimating the design of ball grid array (BGA) footprints [18]. However, previous research combining the resonant cavity model and the segmentation method does not offer sufficient accuracy. It is lacking in accuracy not only in the estimation of the PDN impedance levels, but also in the prediction of the PDN resonance frequencies, especially in the case of the hierarchical PDN analysis. These limitations are caused by the fact that they induce noticeable modeling errors since they cannot include electromagnetic coupling effects between the different levels PDNs and do not consider the fringing field effect at the edge of small-size PDN like package or on-chip level PDN. In this paper, we introduce two kinds of new modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation for the hierarchical PDN. First, based on the resonant cavity model and the segmentation method, we propose a modeling procedure to add the effect of the interlevel electromagnetic coupling between the different levels PDNs. In order to effectively consider the interlevel electromagnetic coupling effect, we introduce a new concept of interlevel PDN, which is, for example, composed of a metal plate in the package-level PDN and a metal plate in the PCB-level PDN when they are facing each other with a short distance. We have applied the concept of the interlevel PDN to the modeling of the hierarchical PDN through a simple modification of the resonant cavity model. Using the suggested modeling analysis, Fig. 2. PDN plane cavity structure with two parallel metal plates of a rectangular shape with an inserted dielectric material. Each port is located at a position on the plane, and two ports are located at (x ;y ) and (x ;y ), respectively. it has been well proven that a significant difference can be observed in the impedance profile of the hierarchical PDN when we consider the high-frequency interlevel electromagnetic coupling effect. Additionally, we have thoroughly investigated the source of unexpected resonances due to the interlevel coupling effect. Next, we present a modeling procedure to include the fringing field effect at the edge of the small-size PDN structure such as the package-level PDN structure and the interlevel PDN structure, which causes considerable shift of the cavity resonance frequencies in the PDN impedance profile. The negligence of the fringing field at the PDN impedance analysis is an inherent restriction of the conventional resonant cavity model when assuming that all boundaries are magnetic walls. This shortcoming can hardly be neglected because the dimensions of the packagelevel and the interlevel PDN are small enough to affect the PDN impedance profile significantly. In order to improve the accuracy of the estimation impedance-level and resonance frequencies in the small sized PDN, we have properly compensated for the fringing field effect by modifying the resonant cavity model and the segmentation method. In order to verify the proposed modeling approaches, we have fabricated a series of test vehicles by combining two packagelevel PDN designs with a PCB-level PDN design. We have successfully verified the proposed simulation results by comparing them with frequency domain PDN impedance measurements in a frequency range up to 5 GHz. As a result, we have convincingly demonstrated good agreement between the model and the measurement, as well as a short calculation time and modest computational resources. It can be said that we have successfully validated the proposed modeling approaches, which are especially crucial for the hierarchical PDN impedance analysis. II. PROPOSED MODELING METHOD OF HIERARCHICAL POWER DISTRIBUTION NETWORK FOR PACKAGE-PCB CODESIGN A. Resonant Cavity Model and Segmentation Method One of the most common modeling approaches to estimate the PDN impedance of rectangular-shaped PDN structures is the resonant cavity model, as shown in Fig. 2. It omits the field variation in the direction because the dimension along the direction is small enough to neglect the electromagnetic field variation between the two plates. The impedance equation using the

3 546 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 3, AUGUST 2008 resonant cavity model is presented in [8] and [9], as described in Fig. 3. Port assignment used in the segmentation method to merge independent PDNs of different dimensions and shapes into a single PDN of an arbitrary shape. where mode number represents the th mode associated with direction; mode number represents the th mode associated with direction; and represent the metal plane widths in the and directions, respectively;, and are the coordinates of the center of the th and th ports in the and directions, respectively;, and are much less than the wavelengths of interest and represent the th and th port widths in the and directions, respectively; represents the real wave-number for the lossless case, and ; is dielectric thickness in the direction; is the permeability of dielectric; is the permittivity of dielectric; is radian frequency and. The constant if if if, and if. When assuming a low-loss dielectric insulator,, and, when is the loss tangent of the dielectric insulator, and and are the skin depth of the metal plane and thickness of the dielectric insulator, respectively [8]. For, term in (1) represents the transfer impedance between the two ports, while for, term represents the self impedance at the port. Even though the resonant cavity model is a fast and efficient modeling method to estimate the PDN impedance of rectangular plane structures, it has difficulty analyzing PDN structures of arbitrary shapes such as an arbitrarily partitioned planar PDN structure at the package-level and PCB-level PDNs or the hierarchical PDN combining the chip-level, package-level, and PCBlevel PDNs. In order to overcome this difficulty of the resonant cavity model and allow for the analysis of PDN impedance of the arbitrary shapes, especially of the hierarchical PDN, we have combined the resonant cavity model with the segmentation method. (The segmentation method alone was suggested in [12] and [13]). Fig. 3 shows the basic modeling concept of the segmentation method which is to combine two independent PDNs to form a single PDN of an arbitrary shape. Two independent structures called structure 1 and structure 2 have rectangular-shaped PDNs with arbitrary dimensions. Ports such as port and port are used for the PDN impedance observations (1) at locations and, and are called external ports. Meanwhile, ports such as port at structure 1, and port at structure 2 are used for assigning interconnections between the two independent PDNs, and are referred to as internal ports. As shown in Fig. 3, the total PDN structure is composed of the two independent, rectangular-shaped structures. Then, PDN impedance of each independent structure (structure 1 and structure 2 of Fig. 3) can be derived by using the resonant cavity model of (1) with a matrix form as presented in Then, the impedance matrix of the total structure of Fig. 3 can be calculated, as shown in (4) at the bottom of the page. As a consequence of using the segmentation method, the impedance matrix of the total structure of the hierarchical PDN can be calculated by using (4), while the impedance matrices of each independent structure such as the impedance matrix of the chip-level, package-level, PCB-level PDN, can be obtained using the resonant cavity model [14] [18]. B. Modeling of Electromagnetic Interlevel Coupling Effect When two different levels PDNs of planar shapes are merged together to form a single hierarchical PDN, a new formerly unseen parallel plate cavity is generated due to the electromagnetic coupling effect between the two planar PDNs, as explained in Fig. 4(b). When the package-level PDN is bonded to the PCB-level PDN using soldering balls and vias, a new parallel plate cavity is formed by the bottom metal plate (power plane) of the package and the top metal plate (ground plane) of the PCB as depicted in Fig. 4(b). In order to interpret this cavity effect, we introduce a concept of interlevel PDN to describe the newly formed cavity. We found that we cannot precisely predict the shift of resonance frequencies and the generation of new resonance frequencies in the PDN impedance curves of the hierarchical PDN unless we accurately consider the interlevel PDN effect, in other words, the interlevel electromagnetic coupling effect. As a result, it should be pointed out that the interlevel electromagnetic coupling effect must be considered as a major (2) (3) (4)

4 KIM et al.: MODELING AND MEASUREMENT OF INTERLEVEL ELECTROMAGNETIC COUPLING AND FRINGING EFFECT 547 Fig. 5. Calculated impedance of the hierarchical PDN based on the resonant cavity model and the segmentation method without the consideration of the interlevel PDN. Fig. 4. (a) Cross-sectional view of the hierarchical PDN without consideration of the interlevel electromagnetic coupling effect between the package-level PDN and the PCB-level PDN. (b) Cross-sectional view of the hierarchical PDN taking into consideration the interlevel electromagnetic coupling effect between the package-level PDN and the PCB-level PDN. We introduce a concept of the interlevel PDN to consider the coupling effect between the different levels PDNs. modeling subject for the accurate analysis of the hierarchical PDN. The impedance profile of the interlevel PDN can be calculated by using the resonant cavity model, but the dielectric insulator between the top metal plate and the bottom metal plate of the interlevel PDN is composed of three different kinds of materials, which are the dielectric material of the package, the dielectric material of the PCB, and air, as shown in Fig. 4. Therefore, we can adopt the concept of effective permittivity, and can calculate the effective permittivity of the dielectric insulator in the interlevel PDN using previously described equations [19]. Then we can find the impedance profile of the interlevel PDN by using the effective permittivity and the resonant cavity model. Finally, we can connect each level PDN by defining internal ports in the segmentation method and then calculate the impedance profile of the total hierarchical PDN, as presented in Figs. 5 and 6. In order to focus on the effect of the interlevel PDN in this session, effects of vias and balls for connecting each level PDNs are neglected, as shown in Figs. 5 and 6. Additionally, the effect of the fringing field at the cavity edge, which will be discussed in the next session, is not considered, either. The impedance profile of a target structure, which includes the effects of via, balls, and the fringing field, will be described in the next section. The impedance profiles of the hierarchical PDN in Figs. 5 and 6 are mainly obtained to demonstrate the effect of the interlevel PDN. Fig. 6. Calculated impedance of the hierarchical PDN based on the resonant cavity model and the segmentation method with the consideration of the interlevel PDN. The impedance profile of the hierarchical PDN which does not consider the interlevel coupling effect is shown in Fig. 5. The graph is divided into four regions (I, II, III, IV) depending on the dominant electrical parameter of the PDN impedance curve in each region. For example, in region I, the PDN impedance is determined by. Also, we can observe resonance peaks of and. The series resonance at position comes from a series interaction between and, while the total capacitances are formed by an electric field between the two planar structures at the PCB and the package. The total inductance for position comes from the magnetic field in the PCB-level and the package-level planar structures. Meanwhile, the high impedance peak at position is a parallel resonance between the capacitance of the package-level PDN and the total inductance of the PCB-level PDN and the package-level PDN. Additionally, a series resonance at position is generated by the capacitance of the package-level PDN and the inductance of the package-level PDN. Finally, a cavity mode resonance of the PCB-level PDN, whose mode number is (2, 0) and (0, 2), is observed at approximately 3 GHz. Cavity mode resonance (1,0), (0,1), and (1,1) of the PCB-level PDN does not appear since the location of the internal port to

5 548 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 3, AUGUST 2008 connect the package-level PDN to the PCB-level PDN in the segmentation method is located at the center of the PCB. The peak level of this PCB mode resonance is considerably suppressed compared to other resonances by a parallel connection of the package-level PDN lowering the total impedance. Fig. 6 describes the calculated impedance curve of the hierarchical PDN with the consideration of the interlevel PDN, which is obtained using the resonant cavity model, and the segmentation method as suggested in the previous session. The graph is divided into six regions (I, II, III, IV, V, VI) depending on the dominant electrical parameter of the PDN impedance curve. Also, we can observe resonance peaks of, and. When we consider the interlevel electromagnetic coupling effect between the package-level PDN and the PCB level PDN, the impedance profile of the hierarchical PDN is considerably changed, as demonstrated in Fig. 6, compared to the graph in Fig. 5, especially in regions III V. The series resonance at position in Fig. 6 comes from the total capacitance and the total inductance of the hierarchical PDN. It should be noted that the interlevel and start to slightly affect the slope of the PDN impedance curve in regions I and II. The high impedance resonance peak at position originates from a parallel resonance between the total capacitance of the package-level PDN and the interlevel PDN and the total inductance at the hierarchical PDN. This resonance peak in Fig. 6 is slightly shifted to a lower frequency compared to the resonance peak in Fig. 5, due to added capacitance and inductance from the interlevel PDN, even though the capacitance and the inductance are relatively small compared to and, respectively. In Fig. 6, another series resonance at position is produced by the series interaction between the total capacitance of the package-level PDN and the interlevel PDN and the total inductance of the package-level PDN and the interlevel PDN. It should be emphasized that this resonance peak is a new feature of the PDN impedance curve (Fig. 6), which appears only when considering the interlevel PDN effect, while it is not exhibited in Fig. 5. Furthermore, we can additionally observe new parallel resonance at position in Fig. 6, which shows a substantially different shape compared to Fig. 5. This resonance is generated by a parallel resonance between the capacitance of the package-level PDN and the total inductance of the package-level PDN and the interlevel PDN. It should be noted that this resonance can be only be observed when considering the interlevel PDN effect. We also notice a series resonance at position, which is generated by the capacitance of the package-level PDN and the inductance of the package-level PDN, which is the identical resonance as the peak in Fig. 5. Finally, we can observe a cavity mode resonance of the PCB-level PDN at position, whose mode number is (2, 0) and (0, 2). The impedance level at the peak is suppressed by the parallel loading effect of the package-level PDN and the interlevel PDN lowering the impedance level. Consequently, it can be stated that significantly different PDN impedance profiles are obtained when we consider the interlevel Fig. 7. (a) Fringing fields are formed at the edge of the rectangular cavity. (b) Fringing field effect at the cavity edge can be equivalently modeled as a uniform field in the z direction by introducing the concept of AWFF. coupling effect in the hierarchical PDN model. It is crucial to add the model of the interlevel PDN when estimating the design quality of the PDN, especially for the hierarchical PDN with chip, package, and PCB. The proposed model approach including the interlevel PDN will be verified using a series of measurements in the next chapter. C. Modeling of the Fringing Field Effect at the Cavity Edge The resonant cavity model assumes that all boundaries at the cavity edges are magnetic walls. This means that no electric field is present outside of the cavity structure. However, in a practical package-pcb hierarchical PDN of a small size with a high-frequency operation, fringing fields are formed at the cavity edge as shown in Fig. 7(a), and the fringing field effect cannot be neglected during precise modeling of the PDN. Thus, we need to add modeling of the fringing electromagnetic field effect to calculate accurate resonance frequencies of the multilevel cavities. Additional fringing fields at the cavity edge increase the total capacitance and the inductance of the PDN, changing the PDN impedance profiles. In the package-level PDN, the fringing fields are formed as an elliptical shape and the fields have two directional components ( and directions), as shown in Fig. 7(a). When we divide the fringing field into these two directions, the integration of the field across the edge leaves the directional components only, because the field component in the direction is cancelled out. After the integration, the remaining directional component becomes a uniform field component in the direction. The condition of the uniform field in the direction is sufficient to employ the same resonant cavity model. As a consequence, we can include the fringing fields in the cavity model by introducing a new parameter called added width by fringing field (AWFF), as described in Fig. 7(b). In order to account for the fringing field effect at the cavity edge, we simply increase the cavity size by an amount of AWFF when calculating the PDN impedance. We have applied the parameter AWFF for the PDN impedance calculations not only for the package-level PDN, but also for the interlevel PDN. The contribution of the proposed modeling procedure with AWFF will be experimentally validated in the next chapter through a series of measurements.

6 KIM et al.: MODELING AND MEASUREMENT OF INTERLEVEL ELECTROMAGNETIC COUPLING AND FRINGING EFFECT 549 Fig. 8. (a) Half-elliptical shape of the fringing field at the interlevel cavity edge for the case of the different size of the top metal plane and the bottom metal plane. (b) Conversion to full-elliptical shape of the fringing field at the interlevel cavity edge of the structure using the image field theory. Fig. 9. (a) Parameters of the package-level cavity. (b) AWFF p depending on the relative permittivity of the dielectric material ("r), and on the thickness of the dielectric material (h). In order to induce AWFF for the interlevel PDN calculation, we have applied an image field theory, as described in Fig. 8. It is difficult to directly apply the AWFF for the interlevel cavity, since we have asymmetry due to the size difference of the top metal plane (power plane in package) and the bottom metal plane (ground plane in PCB). As shown in Fig. 8(a), the field shape of the fringing fields at the interlevel cavity edge is half-elliptical due to the size difference between the top metal plane and the bottom metal plane. In order to represent the fringing fields in the interlevel PDN using the AWFF parameter, we use image field theory, which assumes that an image plane is located at a symmetrical position below the bottom metal plane. Then, the field shape is converted to a full ellipse, as shown in Fig. 8(b). After converting the shape of the fringing field from the half-elliptic shape to the full-elliptic shape at the interlevel PDN, we can use the resonant cavity model as we used it for modeling the fringing field at the package-level PDN. Now, the top metal and the bottom metal are the same size. Finally, we reduce the distance between the top metal plane and the image bottom metal plane in the interlevel PDN, which is denoted as in Fig. 8, by half, and calculate the impedance profile of the interlevel PDN. This approach is valid because the impedance is directly proportional to the distance between the top metal plane and the bottom metal plane as described in (1). On the other hand, for the case of the PCB-level PDN, it is not necessary to consider the effect of the fringing field at the cavity edge because the size of the PCB cavity is much larger than the thickness of the dielectric insulator of the PCB. In order to consider the fringing field using the cavity model and the segmentation method, we need to obtain the values of the AWFF parameters. We swept physical parameters based on a 3-D full-wave simulation (measures fringing capacitance and fringing inductance) to obtain the AWFF parameter value for the package-level PDN and the interlevel PDN of Fig. 7. In the case of a package-level PDN, the swept physical parameters are the relative permittivity of the dielectric material and the thickness of the dielectric material ( ). These physical parameters and sweeping ranges are illustrated in Fig. 9(a), and acquired AWFF of the package-level cavity is shown in Fig. 9(b). From the acquired value of AWFF, we obtained the associated fringing capacitance, fringing inductance, and resulting Fig. 10. (a) Parameters of the interlevel cavity. (b) AWFF i depending on the relative permittivity of the dielectric material ("r), and on the solder ball height (h). PDN impedance profiles, considering the fringing field effect at the cavity edge. AWFF of the package-level PDN, which is defined as AWFF in Fig. 9(b) and (5), increases with both the increased thickness of the dielectric material ( ) and the increased dielectric permittivity of the dielectric material.we can derive an empirical equation of AWFF associated with the sweeping parameters as where is the dielectric constant of the package insulator material and is the thickness of the dielectric insulator of the package substrate. In a similar manner, we have induced AWFF of the interlevel PDN. In the case of interlevel PDN, the swept physical parameters are the relative permittivity of the dielectric material, the thickness of the dielectric material ( ), and the height of the solder ball ( ). These physical parameters and sweeping ranges are illustrated in Fig. 10(a), and the acquired AWFF of the interlevel cavity (AWFF ) is shown in Fig. 10(b). Using the simulation sweep, we can calculate an empirical equation relating the sweeping physical parameters to AWFF, as suggested in where is the height of the solder ball. This calculated AWFF i is added to the width of the top metal plane of the interlevel PDN when calculating the resonant cavity impedance. AWFF increases only with the increased solder ball height ( ) as can be seen in Fig. 10(b) and in (6). This (5) (6)

7 550 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 3, AUGUST 2008 Fig. 12. (a) Detailed 3-D structure and proposed equivalent circuit model of via at the package-level PDN and PCB-level PDN. (b) Detailed 3-D structure and proposed equivalent circuit model of solder ball connecting the package-level PDN to PCB-level PDN. demonstrated that we can achieve precise PDN modeling only when we add the fringing field effects at the package-level cavity and at the interlevel cavity. The impedance profiles simulated by an FEM based commercial full-wave simulator (HFSS from Ansoft) and the impedance profiles of the proposed model with the consideration of fringing effects are in excellent agreement in both the package-level PDN and the interlevel PDN. Fig. 11. (a) Impedance profile of the package-level PDN and (b) impedance profile of the interlevel PDN. Solid line is the calculated impedance profile with the consideration of the fringing fields. Dashed line is the calculated impedance profile without the consideration of fringing fields, and the dotted line is the simulated impedance profile by a commercial full-wave simulator (HFSS from Ansoft). is because the solder ball height ( ) is much thicker than the dielectric thickness ( ) at the package surface and at the PCB surface. The effect of the dielectric constant is negligible since the space between the two metal planes is mostly filled with air, meaning that is much larger than in Fig. 10(a). The difference between the PDN impedance profiles in the package-level PDN with and without the consideration of the fringing fields is well depicted in Fig. 11(a) and the interlevel PDN is in Fig. 11(b). In the case of package-level PDN, graphs are obtained under the following conditions: the relative permittivity of the dielectric is 4.4 and the thickness of the dielectric material ( ) is 1 mm. In case of interlevel PDN, graphs are obtained under the following conditions: the relative permittivity of the dielectric is 4.4, thickness of the dielectric material ( ) is 0.1 mm, and height of the solder ball ( ) is 0.4 mm. Top metal plane width of the interlevel PDN in and directions is 12.7 mm, and bottom metal plane width of the interlevel PDN in and directions is 80 mm in both cases. As a consequence, the value of AWFF is induced as 1.34 mm and the value of AWFF is induced as mm. It is found that the series resonance peaks are shifted to a slightly lower frequency due to the AWFF and AWFF i by the fringing fields. Then, both inductances and capacitances of the cavity are increased by AWFF and AWFF. In Fig. 11, it is well III. EXPERIMENTAL VERIFICATION OF THE PROPOSED MODEL A. Via and Solder Ball Model In order to electrically connect the power planes and the ground planes in the hierarchical PDN, vertical interconnection structures such as via and solder ball are used. The presence of the 3-D vertical interconnection structures causes the impedance profile of the hierarchical PDN to be changed slightly since the contribution of the vertical interconnection structure to the PDN impedance profile is no longer negligible, especially at high frequencies. Therefore, the effect of the vertical interconnection structures such as via and solder ball must be included in the proposed hierarchical PDN model. Fig. 12(a) describes the detailed 3-D structure and the proposed equivalent circuit model of the via used at the packagelevel PDN and at the PCB-level PDN. Meanwhile, Fig. 12(b) shows the detailed 3-D structure and the proposed equivalent circuit model of the solder ball connecting the package-level PDN to the PCB-level PDN. We suggest a -type equivalent circuit model to represent the impedance behavior of the via and the solder ball at a frequency range up to 5 GHz. In Fig. 12(a), represents the inductance of the via, while indicates the capacitance of the via, which is formed between the via and the clearance at the metal planes. Equations (7) and (8) from [20] and [21] present the equivalent circuit model values of and (7) (8)

8 KIM et al.: MODELING AND MEASUREMENT OF INTERLEVEL ELECTROMAGNETIC COUPLING AND FRINGING EFFECT 551 Fig. 13. (a) Cross-sectional structure and dimensions of the test vehicles to verify the proposed model. (b) Top view of the test vehicle including the PCBlevel PDN and the package-level PDN. where is height of the via/solder ball (millimeters); is radius of the via or the solder ball (millimeters); is diameter of pad surrounding the via or the solder ball (millimeters) is diameter of the clearance (millimeters); is distance between the via or the solder ball from center to center (millimeters); is distance from the pad to the power or ground plane (millimeters); and is relative permittivity of insulator. When we heated the solder ball to electrically connect the package-level PDN to the board-level PDN, the shape of the heated solder ball changed to a cylindrical form because the top and the bottom parts of the solder ball melted. Therefore, we can apply the same equations (7) and (8) to suggest the equivalent circuit model of the solder ball. We assume that the height of the melted solder ball is approximately two-thirds of the diameter of the original solder ball height. In Fig. 12(b), represents the inductance which is formed for the connection of the solder ball pads, indicates the capacitance formed by the clearance at the planes, and describes the inductance of the melted solder ball. We have neglected the parasitic effect of the connection line between the via and the solder ball. B. Fabricated Test Vehicles In order to verify the proposed modeling approach, we designed and fabricated a series of test vehicles to compare the Fig. 14. Two kinds of the fabricated test vehicles. (a) Type I test vehicle has a pair of power and ground balls to connect the package-level PDN to the PCBlevel PDN. (b) Type II test vehicle has four pairs of power and ground balls to connect the package-level PDN to the PCB-level PDN. simulation obtained from the suggested model with the measurement results. Fig. 13(a) shows the cross-sectional structure and dimensions of the test vehicles. Two of the package-level PDNs are mounted on a PCB-level PDN to measure the self impedance of the hierarchical PDN at probing position 1 (port 1) or at probing position 2 (port 2) as well as the transfer impedance of the hierarchical PDN between the probing position 1 (port 1) and the probing position 2 (port 2). Fig. 13(b) describes the top view of the test vehicle in which two package-level PDNs are mounted on the PCB-level PDN using the solder balls. We have fabricated two kinds of test vehicles to verify the proposed modeling approach. The type I test vehicle is shown in Fig. 14(a). It has a pair of power and ground balls to connect the package-level PDN to the PCB-level PDN. On the other hand, all of the solder balls except the pair of power and ground balls remain floating. In the type II test vehicle, four pairs of power and ground balls are used to connect the package-level PDN to the PCB-level PDN, as shown in Fig. 14(b). Hence, the two test vehicles have different amounts of electrical parasitic contribution from the power/ground solder ball interconnections. All of the solder balls except the four pairs of power and ground balls are floated in the type II test vehicle. In both cases, the ground planes of package-level PDN and PCB-level PDN are located on the second layer of structures, and the power planes of package-level PDN and PCB-level PDN are located on the third layer of structures. The shapes of power and ground planes in package-level PDN and PCB-level PDN are regular

9 552 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 3, AUGUST 2008 Fig. 16. Experimental setup to measure the PDN self impedance (Z11) and the PDN transfer impedance (Z21) of the test vehicles in Fig. 14. posed model for the type II test vehicle than for the type I test vehicle. We used two external ports and 252 internal ports for the model of the type I test vehicle and two external ports and 324 internal ports for the model of the type II test vehicle. Fig. 15. Proposed hierarchical PDN model. Number at each connection line describes the number of internal ports and external ports for the type I test vehicle and number in parentheses at each connection line tells the number of internal ports and external ports for the type II test vehicle. squares whose sizes are as large as the package-level PDN and the PCB-level PDN, as shown in Fig. 14(b). On top of each package-level PDN in the test vehicles, a pair of power and ground pads were designed for the high-frequency probing at the center of the package surface. The probing pads on the left package-level PDN are defined as port 1 and the probing pads on the right package-level PDN are defined as port 2, as illustrated in Fig. 14. Fig. 15 shows the structure of the proposed model to represent the impedance profile of the hierarchical PDN as suggested in Fig. 13. The total hierarchical PDN model consists of two package-level PDNs, two interlevel PDNs and one PCB-level PDN. The package-level PDN contains the plane cavity model, fringing field effect model, and via model. The via model on the upper side of the package-level PDN is used for probing pads of the port 1 and port 2, while the via model on the lower side of the package-level PDN is for pads of the solder ball connections. The interlevel PDN model is composed of the interlevel plane cavity model, fringing field effect model, and solder ball model, which have parallel connections, as shown in Fig. 15. The package-level PDN and the PCB-level PDN are mainly connected by the solder ball, and the cavity effect of the interlevel PDN is added in parallel to describe the coupling effect between the two PDNs. The PCB-level PDN model consists of plane cavity model and via model. In Fig. 15, the number at each connection line describes the number of internal ports or external ports in the segmentation modeling method to complete the proposed model of the type I test vehicle, while numbers in parentheses describe the number of internal ports or external ports for the type II test vehicle. For the type I test vehicle, we used a pair of the via models for pads of the solder ball connections in the package-level PDN. We used a pair of the solder ball models for the interconnections between the package-level PDN and the PCB level PDN and a pair of the via models for pads of the solder ball connections in the PCB-level PDN. For the type II test vehicle, we used four pairs of the via models, and four pairs of the solder ball models. Therefore, we needed more internal ports to complete the pro- C. Experimental Verification We measured the PDN self impedance ( 11) and the PDN transfer impedance ( 21) of the test vehicles in Fig. 14 so as to verify the proposed hierarchical PDN model. Fig. 16 shows the experimental setup for measurement. We used a vector network analyzer N5230A from Agilent and a microprobe of FPC-series GS type with a 0.25-mm pitch from Cascade Microtech to measure the S-parameters of the test vehicles in a frequency range from 100 MHz to 5 GHz. We also simulated the impedance profiles of the test vehicles by using an FEM based commercial full-wave simulator (HFSS from Ansoft) in order to verify the accuracy of the impedance profiles as well as the superior computation speed of the proposed hierarchical PDN model. Fig. 17 shows the simulated and the measured PDN self impedance ( 11) of the type I test vehicle in Fig. 14(a), probed at port 1 on the package surface. Fig. 18 presents the PDN transfer impedance ( 21) of the type I test vehicle of Fig. 14(a), probed between ports 1 and 2 on the package surface. The solid line represents the PDN impedance obtained from the proposed model by using MATLAB. The dotted line describes the PDN impedance obtained from the measurement, and the dashed line tells the PDN impedance simulated by HFSS. From Figs. 17 and 18, it is clearly demonstrated that the impedance profiles of the self impedance and the transfer impedance obtained from the proposed model and from the measurement exhibit strongly consistent and well matched resonant peaks up to about 3 GHz. It shows that the cavity resonances from the package-level PDN, the interlevel PDN, and the PCB-level PDN are precisely predicted from the proposed model. From the comparison between Figs. 17 and 18, it should be noted that the via and the solder ball models in Fig. 12 are correctly designed. The impedance profiles of the self impedance and the transfer impedance simulated by HFSS are also in excellent agreement with the impedance profiles from the proposed model. However, it takes 11 min and 47 s to compute the PDN self impedance and the PDN transfer impedance of the type I test vehicle based on the proposed model by using MATLAB. Whereas it takes 1 h 51 min and 6 s to simulate the type I test vehicle by using HFSS. It should be noted that the proposed model can calculate the impedance profiles of test vehicle as accurately as commercial tools and is computationally superior. In the self impedance profile ( 11) of the type I test vehicle, as shown in Fig. 17, the series resonance at position comes

10 KIM et al.: MODELING AND MEASUREMENT OF INTERLEVEL ELECTROMAGNETIC COUPLING AND FRINGING EFFECT 553 Fig. 17. PDN impedance (Z11) of the type I test vehicle in Fig. 14(a), probed at the probing pad position 1 on the package surface, as shown in Fig. 14(a). Solid line represents the PDN impedance obtained from the proposed model. Dotted line represents the PDN impedance obtained from the measurement. Dashed line represents the PDN impedance obtained from full-wave simulation. Fig. 18. PDN impedance (Z21) of the type I test vehicle in Fig. 14(a), probed between the probing pad position 1 and the probing pad position 2 on the package surface as shown in Fig. 14(a). Solid line represents the PDN impedance obtained from the proposed model. Dotted line represents the PDN impedance obtained from the measurement, and the dashed line represents the PDN impedance obtained from full-wave simulation. from a series interaction between the capacitance and the inductance formed by the type I test vehicle. The equations of capacitance and inductance are represented in (9) (10) where and represent the capacitance and the inductance formed by the package-level PDN; and are the capacitance and the inductance generated by the interlevel PDN; and and are the capacitance and the inductance produced by the PCB-level PDN. Additionally, and indicate the capacitance and the inductance formed by the via model and and represent the capacitance and the inductance generated by the solder ball model, as introduced in Fig. 12(a). The test vehicle introduced in Fig. 13 contains two packagelevel PDNs, two interlevel PDNs, and one PCB-level PDN. The number of each levels PDNs is well represented in (9) and (10). Additionally, the type I test vehicle includes two via models for the probing pad connection used in the S-parameter measurement, two via models for the solder ball pad connection in the package-level PDN, and two via models for solder ball pad connection in the PCB-level PDN. This is why capacitance and inductance in the equations are six times larger than the capacitance and inductance of the via model. Furthermore, the interlevel PDN and the solder ball model have a parallel connection, so the capacitance of the interlevel PDN and the capacitance of the solder ball model are added as represented in (9). The inductance of the interlevel PDN and the inductance of the solder ball model have a parallel connection, which is represented in (10). The high impedance peak at position is a cavity mode resonance at the PCB-level PDN, whose mode number is. Meanwhile, the high impedance peak at position is a parallel resonance between the capacitance from the package-level PDN to the PCB-level PDN and the total inductance from package-level PDN to the adjacent interlevel PDN. Additionally, the high impedance peak at position is generated by a parallel resonance between the capacitance from the package-level PDN to the interlevel PDN and the inductance from the package-level PDN to the PCB-level PDN. Furthermore, we can observe cavity mode resonances of the PCB-level PDN at positions and, whose mode numbers are, and, respectively. Finally, a parallel resonance at position occurs because of the interaction between the capacitance of the package-level PDN and the inductances of the package-level PDN and the interlevel PDN. Fig. 19 represents various impedance profiles of type I test vehicle based on segmentation method when the interlevel PDN and the fringing effects are considered or not taken into consideration. In Fig. 19(a), the dashed line is the impedance profile

11 554 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 3, AUGUST 2008 Fig. 19. (a) Dashed line is the impedance profile without the consideration of both the interlevel PDN effect and the fringing effect in package-level PDN. Solid line is the impedance profile without the consideration of the interlevel PDN effect but with the consideration of the fringing effect in package-level PDN. Dotted line is the impedance profile from the measurement. (b) Dashed line is the impedance profile with the consideration of the interlevel PDN but without the consideration of fringing effects in the interlevel PDN and the package-level PDN. Solid line is the impedance profile with the consideration of both the interlevel PDN and fringing effects in the interlevel PDN and the package-level PDN. Dotted line is also the impedance profile from measurement. without considering the interlevel PDN effect and the fringing effect in package-level PDN. The solid line is the impedance profile without the consideration of the interlevel PDN effect but with the consideration of the fringing effect in package-level PDN, and the dotted line is the impedance profile from the measurement. The significant difference between impedance profile from the measurement and the proposed model without consideration of interlevel PDN is that the resonant peak in region disappeared. Even though we consider the fringing effect in the package-level PDN as the solid line in Fig. 19(a), the impedance resonance at region is not generated. Additionally, the overall shapes of impedance profiles without the consideration of the interlevel PDN are totally different when comparing with the impedance profile from measurement. In Fig. 19(b), the dashed line is the impedance profile with the consideration of the interlevel PDN and without the consideration of fringing effects in the interlevel PDN and the packagelevel PDN. The solid line is the impedance profile with the consideration of both the interlevel PDN and fringing effects in the interlevel PDN and the package-level PDN, and the dotted line is also the impedance profile from measurement. The resonant peak at region is generated because of the effect of the interlevel PDN. Additionally, the capacitive impedance in region and the inductive impedance in region are more consistent with the impedance profile from measurement when we consider the fringing effects in package-level PDN and interlevel PDN. The similarity between the measured and the modeled profiles comes from the increases of capacitance and inductance due to fringing effects. As a result, it is proved that the interlevel PDN effect and the fringing effects in package-level PDN and interlevel PDN make the impedance profile of hierarchical PDN (type I test vehicle) more precise. Especially, it is well proven that the consideration of the interlevel PDN in hierarchical PDN is essential to represent the resonant peak generated by interaction between package-level PDN and PCB-level PDN. Additionally, it should be also noted that the correct anticipation of the resonance peaks and peak levels could be obtained only by properly including the effect of the fringing fields at each cavity model and by adequately including the interlevel cavity effect between the package-level PDN and the PCB-level PDN. Fig. 20 shows the simulated and the measured PDN self impedance ( 11) of the type II test vehicle of Fig. 14(b), probed at the port 1 on the package surface. Meanwhile, Fig. 21 exhibits the PDN transfer impedance ( 21) of the type II

12 KIM et al.: MODELING AND MEASUREMENT OF INTERLEVEL ELECTROMAGNETIC COUPLING AND FRINGING EFFECT 555 Fig. 20. PDN impedance (Z11) of the type II test vehicle in Fig. 14(b), probed at the probing pad position 1 on the package surface, as shown in Fig. 14(b). Solid line represents the PDN impedance obtained from the proposed model. Dotted line represents the PDN impedance obtained from the measurement. Dashed line represents the PDN impedance obtained from full-wave simulation. Fig. 21. PDN impedance (Z21) of the type II test vehicle in Fig. 14(b), probed between the probing pad position 1 and the probing pad position 2 on the package surface, as shown in Fig. 14(b). Solid line represents the PDN impedance obtained from the proposed model. Dotted line represents the PDN impedance obtained from the measurement. Dashed line represents the PDN impedance obtained from full-wave simulation. test vehicle of Fig. 14(b), probed between port 1 and port 2 on the package surface. The solid line represents the PDN impedance obtained from the proposed model. The dotted line describes the PDN impedance obtained from the measurement, and the dashed line tells the PDN impedance simulated by HFSS. The graph profiles of the self impedance and the transfer impedance obtained from the proposed model and the full-wave simulator also proved to be in excellent agreement with the PDN impedance graph profiles acquired from measurements. In the case of the type II test vehicle, it takes 17 min and 22 s to compute the PDN self impedance and the PDN transfer impedance based on the proposed modeling method, while we need 20 h 59 min and 35 s to simulate the type II test vehicle by using HFSS. As a result, it can be said that the proposed model is tremendously useful and can considerably reduce the calculation time for the analysis of the hierarchical PDN, especially for the package-pcb-level codesign and cosimulation. The difference in the PDN impedances ( 11 and 21) between the type I and the type II test vehicles are illustrated in Figs. 22 and 23, respectively. First, from Fig. 22, we can observe considerable differences in the inductance of 11 between the two test vehicles. It is found that the total inductance of the type II test vehicle is much smaller than the total inductance of the type I test vehicle. As can be observed in Fig. 22, a series resonance at 150 MHz is generated in the type I test vehicle by the inductance line as represented by Fig. 22. Comparison of the PDN impedances (Z11) of the type I (solid line) and the type II (dotted line) test vehicles in Fig. 14(a) and (b), probed at the probing pad position 1 on the package surface. line. Meanwhile, the inductance of the type I test vehicle represented by line and by line produces two parallel resonances at approximately 1 GHz. The inductance of the type II test vehicle represented by line forms a series resonance at 250 MHz. The inductance of the type II test vehicle represented by line and by line

13 556 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 3, AUGUST 2008 Fig. 23. Comparison of the PDN impedances (Z21) of the type I (solid line) and the type II (dotted line) test vehicles in Fig. 14(a) and (b), probed between the probing pad position 1 and the probing pad position 2 on the package surface. form two parallel resonances at approximately 1.5 GHz. This is primarily a result of the fact that the type II test vehicle has lower inductance since it uses four pairs of the solder balls to connect the package-level PDN to the PCB-level PDN. As a consequence, the contribution of the solder balls and the vias to the total inductance are considerably reduced in the type II test vehicle. The positions of the series resonance peak and the positions of the high impedance peaks are shifted to higher frequency positions because of the lowered total inductance of the type II test vehicle. The high impedance peaks of the transfer impedance at the type II test vehicle are also shifted to higher frequency positions due to the lowered total inductance of the type II test vehicle, as shown in Fig. 23. Overall, the PDN impedance of the type II test vehicle has lower impedance levels resulting in lower SSN generation and coupling, and has higher resonance frequencies. IV. CONCLUSION In this paper, we proposed an efficient hierarchical PDN modeling method which is suitable for the analysis of package-pcb codesign and simulation by combining the resonant cavity model and segmentation method. In particular, we included a modeling procedure to add the effect of the interlevel electromagnetic coupling between the different levels PDNs in order to improve modeling accuracy in the proposed hierarchical PDN. To effectively represent the interlevel electromagnetic coupling effect, we have introduced a new concept of interlevel PDN, which occurs between a metal plate in the package-level PDN and a metal plate in the PCB-level PDN when they are facing each other within a short distance. The modeling of the interlevel PDN is enabled by a simple modification of the resonant cavity model. We proved that significant improvement of the calculation accuracy in the hierarchical PDN modeling can be achieved only when we consider the high-frequency interlevel electromagnetic coupling effect. Additionally, we demonstrated that the prediction of new resonance peaks and the shifts of the resonance frequencies have been accurately modeled using the proposed method. Next, we included an additional modeling procedure in the proposed hierarchical PDN analysis to take into account the fringing field effect at the edge of the small-sized cavity structures (package-level PDN structure and the interlevel PDN structure). Here, we proved that the fringing field effect causes a considerable shift of the cavity resonance frequencies in the PDN impedance profile. We showed that in order to improve the accuracy of the estimation impedance level and the resonance frequencies in the small-sized PDN, we need to properly estimate the fringing field effect by modifying the resonant cavity model. In order to verify the proposed modeling approach, we fabricated a series of test vehicles which are composed of two package-level PDNs with a PCB-level PDN. We demonstrated good agreements and notable correlations between the model and the measurement in a frequency range from 100 MHz to 5 GHz, as well as a short calculation time and modest computational resource. Consequently, it can be said that we successfully validated the proposed modeling approaches, which are especially crucial for efficient hierarchical PDN impedance analysis. REFERENCES [1] International technology roadmap for semiconductors Semiconductor Industry Assoc., [2] T. Sudo, H. Sasaki, N. Masuda, and J. L. Drewniak, Electromagnetic interference (EMI) of system-on-package (SOP), IEEE Trans. Adv. Packag., vol. 27, no. 2, pp , May [3] H. Kim, Y. Jeong, J. Park, S. Lee, J. Hong, Y. Hong, and J. Kim, Significant reduction of power/ground inductive impedance and simultaneous switching noise by using embedded film capacitor, Electron. Perform. Electron. Packag., pp , Oct [4] J. Kim, Analysis of noise coupling from a power distribution network to signal traces in high-speed multilayer printed circuit boards, IEEE Trans. Electromagn. Compat., vol. 48, no. 2, pp , May [5] J. Park, H. Kim, Y. Jeong, J. Kim, J. S. Pak, D. G. Kam, and J. Kim, Modeling and measurement of simultaneous switching noise coupling through signal via transition, IEEE Trans. Adv. Packag., vol. 29, no. 3, pp , Aug [6] J. S. Pak, H. Kim, H. Lee, and J. Kim, PCB power/ground plane edge radiation excited by high-frequency clock, in Proc IEEE Int. Symp. Electromagn. Compatibil., 2004, vol. 1, pp [7] M. Xu and T. H. Hubing, Estimating the power bus impedance of printed circuit boards with embedded capacitance, IEEE Trans. Adv. Packag., vol. 25, no. 3, pp , Aug [8] G.-T. Lei, R. W. Techentin, and B. K. Gilbert, High frequency characterization of power/ground-plane structures, IEEE Trans. Microw. Theory Tech., vol. 47, no. 5, pp , May [9] Z. L. Wang, O. Wada, Y. Toyota, and R. Koga, Convergence acceleration and accuracy improvement in power bus impedance calculation with a fast algorithm using cavity modes, IEEE Trans. Electromagn. Compat., vol. 47, no. 1, pp. 2 9, Feb [10] T. Okoshi, Y. Uehara, and T. Takeuchi, The segmentation method: An approach to the analysis of microwave planar circuits, IEEE Trans. Microw. Theory Tech., vol. MTT-24, no. 10, pp , Oct [11] R. Chadha and K. C. Gupta, Segmentation method using impedance matrices for analysis of planar microwave circuits, IEEE Trans. Microw. Theory Tech., vol. MTT-29, no. 1, pp , Jan [12] R. Sorrentino, Planar circuits, waveguide models and segmentation method, IEEE Trans. Microw. Theory Tech., vol. MTT-33, no. 10, pp , Oct [13] T. Okoshi, Planar Circuits For Microwaves and Lightwaves. Munich, Germany: Springer-Verlag, 1985, ch. 2. [14] L. Zhang, B. Archambeault, S. Conner, J. L. Knighten, J. Fan, N. W. Smith, R. Alexander, R. E. DuBroff, and J. L. Drewniak, A circuit approach to model narrow slot structures in a power bus, in Proc. IEEE Int. Symp. Electromagn. Compatibil., 2004, vol. 2, pp [15] Y. Jeong, J. Kim, and J. Kim, Matrix substitution method for power bus analysis with isolated power island in high-speed packages and pcbs, IEEE Microw. Wireless Compon. Lett., vol. 16, no. 1, pp , Jan

14 KIM et al.: MODELING AND MEASUREMENT OF INTERLEVEL ELECTROMAGNETIC COUPLING AND FRINGING EFFECT 557 [16] Z. L. Wang, O. Wada, Y. Toyota, and R. Koga, Modeling of gapped power bus structures for isolation using cavity modes and segmentation, IEEE Trans. Electromagn. Compat., vol. 47, no. 2, pp , May [17] Y. Jeong, Hybrid analytical modeling method for split power bus in multi-layered package, IEEE Trans. Electromagn. Compat., vol. 48, no. 1, pp , Feb [18] G. Selli, J. L. Drewniak, R. E. Dubroff, J. Fan, J. L. Knighten, N. W. Smith, D. McCoy, and B. Archambeault, Power integrity investigation of BGA footprints by means of the segmentation method, in Proc. Int. Symp. Electromagn. Compatibil., 2005, vol. 2, pp [19] D. M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, 1998, pp [20] H. W. Johnson and M. Graham, High-Speed Digital Design A Hand Book of Back Magic. Englewood Cliffs, NJ: Prentice Hall, 1993, p [21] H. W. Johnson and M. Graham, High-Speed Signal Propagation-Advanced Black Magic. Englewood Cliffs, NJ: Prentice Hall, 2003, p Jaemin Kim received the B.S. degree in electrical and electronic engineering from Yonsei University, Seoul, Korea, in 2003, and the M.S. degree in electrical engineering, in 2006, from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently working toward the Ph.D. degree. His current research interests include RF mixed-mode system-in-package design and chip-package-pcb power distribution network codesign and cosimulation methodology. Youchul Jeong received the B.S., M.S., and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1999, 2001, and 2006, respectively. His Ph.D. dissertation focused on power bus design for high-speed mixed mode system on package using embedded capacitor. In 2005, he joined Memory Division of Samsung Electronics, Hwasung, Korea. He is currently a Senior Engineer at DRAM Design Team. Since joining Samsung Electronics, his research interest centers on the design of I/O circuits considering signal integrity, power integrity, and electromagnetic compatibility. In particular, he works on interconnect modeling, analytical power bus modeling, and I/O circuit design with low switching noise. Jingook Kim received the B.S., M.S., and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2000, 2002, and 2006, respectively. He has worked on power/signal integrity design, package modeling in gigahertz systems, and minimizing EMI/EMC. Currently, he is with the DRAM Design Team, Memory Division of Samsung Electronics, where he designs many high-speed I/O circuits such as DLL/PLL. Junho Lee received the B.S. degree in radio science and communication engineering from Hong-ik University, Seoul, Korea, in 1998, and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejon, Korea, in 2001 and 2006, respectively. After receiving the Ph.D. degree, he joined Hynix Semiconductor Inc., Icheon, Korea, in 2006, where he was responsible for power integrity and EMI of high-speed memories. monitoring circuit. Chunghyun Ryu received the B.S. degree in radio science engineering from Chung-Nam National University, Daejeon, Korea, in 2002, and the M.S. and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2004 and 2008, respectively. His research interests include clock distribution scheme, chip package codesign, and power/signal integrity of chip and package level for high-speed system-in-package. Jongjoo Shim received the B.S. degree in electrical engineering from the Kyungpook National University, Daegu, Korea, in 2003, and the M.S. degree in electrical engineering, in 2005, from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently working toward the Ph.D. degree. He has been working on circuit modeling of shielding enclosures and chip-package codesign. His current research interest is the adaptive on-chip power management system using on-chip SSN Minchul Shin received the B.S. and M.S. degrees in electrical and electronic engineering, in 2005 and 2007, respectively, from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently working toward the Ph.D. degree. His current research interests include design of on-chip eye opening monitoring circuit and package-pcb channel design considered signal integrity at high-speed digital communication. Joungho Kim received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, in In 1994, he joined Memory Division of Samsung Electronics, where he was engaged in Gbit-scale DRAM design. In 1996, he moved to Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea. He is currently a Professor at Electrical Engineering and Computer Science Department. Since joining KAIST, his research centers on modeling, design, and measurement methodologies of hierarchical semiconductor systems including high-speed chip, package, interconnection, and multilayer PCB. Especially, his major research topic is focused on chip-package codesign and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3-D semiconductor packages, system-in-package (SiP), and system-on-package (SoP). He has successfully demonstrated low-noise and high-performance designs of more than 10 SiPs for wireless communication applications such as ZigBee, T-DMB, NFC, and UWB. He was on a sabbatical leave during an academic year from 2001 to 2002 at Silicon Image Inc., Sunnyvale, CA. He was responsible for low-noise package designs for SATA, FC, HDMI, and Panel Link SerDes devices. Currently, he is the Director of Satellite Research Laboratory of Hyundai Motors Inc., for EMI/EMC modeling of automotive RF, power electronic, and cabling systems. He has authored and coauthored over 230 technical papers published in refereed journals and conference proceedings. Also, he has given more than 105 invited talks and tutorials at the academia and the related industries. Dr. Kim has received an annual faculty outstanding academic achievement award of KAIST in He has been the Chair or the Co-Chair of the EDAPS workshop since Currently, he is an Associated Editor of the IEEE TRANSACTIONS OF ELECTROMAGNETIC COMPATIBILITY.