Modeling, Design, and Demonstration of 2.5D Glass Interposers for 16-Channel 28 Gbps Signaling Applications

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1 Modeling, Design, and Demonstration of 2.5D Glass Interposers for 16-Channel 28 Gbps Signaling Applications Brett Sawyer, Bruce C. Chou, Saumya Gandhi, Jack Mateosky, Venky Sundaram, and Rao Tummala 3D Systems Packaging Research Center, Georgia Institute of Technology, 813 Ferst Dr N.W., Atlanta, GA Ciena Corporation, Hanover, MD Abstract This paper describes the modeling, design, and demonstration of high-speed differential transmission lines on a 130μm thin glass interposer with two re-distribution layers (RDL), line lengths of 1-50mm, and turn radii of mm for 16-channel signal transmission at 28 Gbps per channel. Next generation photonic systems such as 400 Gigabit Ethernet (400 GbE) require low power and low loss channels between photodetectors and trans-impedance amplifiers (TIA) or between laser arrays and driver ICs. Glass, with low dielectric constant and loss tangent, has higher electrical performance and channel power efficiency compared to silicon interposers. Furthermore, low surface roughness and high-dimensional stability of glass enable finer lithographic dimensions and higher interconnection density during large panel processing compared to organic interposers. Interconnection of optical and electrical ICs on 2.5D glass interposers provides the best combination of electrical and optical signal performance. For 400 GbE modules, a 16-channel bus at 28 Gbps per channel is required for communication to the backplane. Electrical modeling and simulation was performed to arrive at an appropriate design for the 16x28 Gbps I/O interface on a two-metal layer glass interposer. An ultra-thin 130μm glass interposer was fabricated using low-cost, double-side panel processing providing for a lower cost, higher performance solution compared to silicon interposers. Introduction Next generation systems such as 400 GbE and cloud servers require low loss electrical channels between electronic and photonic ICs. Optical and electrical chips assembled at close proximity with 2.5D interposers can be thought of as one way to achieve ultra-high bandwidth channels with lower power consumption compared to conventional packages, assembled on boards [1]. Glass interposers offer compelling advantages over silicon and organic interposers to achieve high-speed and wide I/O channels. Signal speeds up to 11.5 Gb/s at 2cm interconnect length have been demonstrated with a four-metal layer 2.5D silicon interposers, fabricated using back end of line (BEOL) processes [2]. The high electrical loss of silicon, however, combined with the high resistivity of ultra-thin metallization layers using 65nm node BEOL, requires high driver power consumption. Silicon interposers have also been used to implement a 28 Gbps SerDes transceiver in a fieldprogrammable gate (FPGA) package [3], where high-speed channels required through-silicon-vias (TSV). Using TSV for performance-critical nets increases capacitive loading and crosstalk due to the poor electrical properties of silicon. Through-package-vias (TPVs) in glass, however, result in significantly lower channel losses compared to TSVs [4]. Organic interposers are being developed for 2.5D integration of logic and memory ICs at 40μm bump pitch with 2μm line widths [5]. There are several challenges, however, associated with organic interposers for 2.5D photonic applications including: high precision photonic IC assembly, fiber alignment, and high-speed channel performance due to low dimensional stability, warpage, and surface roughness [3]. This paper describes a 2.5D glass interposer with electronic and photonic ICs as shown in Fig. 1. The low dielectric constant and low loss tangent of glass results in high performance die-to-die interconnections, while the high modulus and high thermal and dimensional stability leads to high precision optical fiber and photonic die assembly. Exploiting these electrical and optical advantages of 2.5D glass interposers, however, requires the design of high-speed differential traces supporting 16x28 Gbps I/O from the interposer to the backplane. 400 μm 150 μm TIA/Driver PD/VCSEL Array Glass Interposer Organic Substrate TIA/Driver 28G Differential Lines Low Loss Interconnects PD/VCSEL Array Substrate Interposer Fig D glass interposer architecture with electronic and photonic ICs. This paper, for the first time, demonstrates high-speed differential transmission lines using an ultra-thin 130μm glass substrate with TPV to achieve 16-channel, 28 Gbps per channel signaling. Since the I/O density for 2.5D photonic interposers is relatively low compared to wide I/O logicmemory applications, a glass interposer with only two RDLs, fabricated using double-side processes, was used to reduce the /15/$ IEEE Electronic Components & Technology Conference

2 Design spec. not included in design rule Differential Impedance Zdiff [Ω] interposer cost critical for the success of glass photonic modules. The following section describes the 3D electromagnetic (EM) modeling and simulations used to develop an optimized design for differential traces on 130μm thin glass. The next section describes the materials used to fabricate the test vehicle, using a double-side, panel-scalable semi-additive metallization scheme. The last section presents the analysis and correlation between measurements of the fabricated test samples and design parameters. Modeling of Differential Traces on Glass Interposers The main purpose for modeling and simulating differential traces was to establish a design space from which design rules can be established in order to fabricate a glass test vehicle at high yield using panel-level processes. The method followed to create this design space is summarized in Fig. 2 below. The first step was determining the line width (W) of an isolated microstrip line (MSL) such that Z 0 = Ω on a 130μm thick glass substrate (ε r = 5.0, tanδ = at f = 10.26GHz). The width of the MSL transmission lines was set to greater than 10μm to ensure the yield of the test structures. Determine MSL line width W for Z0 = Ω MSL yieldable using standard SAP? Y Determine line spacing S for Zdiff = 100 Ω Set design rule for 28G lines on 2.5D glass interposer 3DEM modeling of differential line performance at line length L = 1 50 mm 3DEM modeling of differential line turning structure at turn radius R = 0.15 mm 8.0 mm choosing design variations with line pitch closest to chiplevel pitch, the fan-out distance was minimized, and, as a result, Z diff can be maintained at 100Ω Z0 Z0 = 50Ω (W = 205 μm) Z0 = 60Ω (W = 155 μm) Z0 = 70Ω (W = 100 μm) Z0 = 80Ω (W = 70 μm) Z0 = 90Ω (W = 55 μm) Z0 = 100Ω (W = 40 μm) Line Spacing S [μm] Fig. 3. 2D EM extraction results of differential line impedance. Following the 2D EM analysis previously described, two differential designs were down selected: (1) W = 155μm, S = 120μm (Z 0 = 60Ω) and (2) W = 100μm, S = 54μm (Z 0 = 70Ω). The performance of these two differential trace designs was analyzed with respect to return loss S d11 and insertion loss S d21 using 3D EM analysis. Parametric models developed for this analysis are shown in the cut out of Fig. 4a (Z 0 = 60Ω) and Fig. 4b (Z 0 = 70Ω). Port de-embedding was used to extract S d11 and S d21 at line lengths L = 1, 5, 10, 15, 30, and 50mm. Results of this analysis are summarized for S d11 in Fig. 4. The return loss for both design variations was less than -25 db for all line lengths indicating good matching required to minimize chip I/O power loss. Z0 Differential line pitch similar to chip bump pitch? Y Glass test vehicle design Fig. 2. Modeling approach to develop design rules for high yield and high performance differential traces on low-cost glass interposers. After determining the line widths to achieve characteristic MSL impedances (Z 0 = 50, 60, 70, 80, 90, and 100Ω), a 2D EM analysis was used to determine appropriate line spacing S between two microstrip transmission lines to achieve a differential impedance (Z diff ) of 100Ω. The results of this analysis are shown in Fig. 3. For each MSL variation, the line spacing was swept from 200μm down to 20μm and Z diff was extracted. After the line width and space were determined to achieve a Z diff of 100 Ω, the designs were further refined such that those design variations at line pitch closest to 150μm (Z 0 = 70Ω) and 300μm (Z 0 = 60Ω) were chosen. This choice in pitch was made to match the on-chip bump pitch of commercial-off-the-shelf (COTS) TIAs and drivers. By 2189

3 Sd21 Normalized [db/mm] Signal Length L [mm] Z0 = 60 Ω Sd11 [db] Z0 = 70 Ω Sd11 [db] Fig. 4. Differential return loss Sd11at line lengths L = 1mm up to 50mm for variations Z 0 = 60Ω, Z 0 = 70Ω from f = 0.1GHz 100GHz, and Sd11 at f = 14GHz for all line lengths analyzed. Similar parametric analysis was performed to assess S d21 for both designs, and, in general, differential insertion losses were higher for Z 0 = 70Ω as shown in Fig. 5 for L = 10mm. At f = 14GHz, the normalized insertion loss was db/mm and db/mm, for Z 0 = 60Ω and Z 0 = 70Ω, respectively. This performance difference is due to the increased conductor losses at smaller line widths, which is exaggerated at increased frequencies due to skin effect db (f = 14 GHz) db (f = 14 GHz) Fig. 5. Differential insertion loss Sd21 at L = 10mm for variations Z 0 = 60Ω and Z 0 = 70Ω Zdiff = 100Ω for both design variations. The effect of turning radius on line loss was studied in addition to S d11 and S d21 performance at various line lengths. Establishing a minimum turning radius in the design is critical to chip fan-out and integration density. The following analysis assumes that line turning is achieved with rounded features, and therefore, a sharp 90 turn is not considered. A general turning test structure is shown in the cutout of Fig. 6. Differential design variations were compared at turning radii R = 0.3, 0.4, 0.8, 1, 2, 4, and 8mm where the straight line distance between turning structures is maintained to be λ/4 = 5.35mm (f = 14GHz). An s-turn type test structure is used to maintain symmetry of the differential trace. The results of this analysis are summarized in Fig. 6. As previously noted, S d21 increased with decreasing line width. Additionally, line losses increased with decreasing turn radius from 8mm to 2mm for both the differential design variations considered. In general, however, the effect of turn radius on line loss was minimal and S d21 did not vary significantly from those results obtained for the straight-line test structures shown in Fig λ/8 λ/4 λ/8 Turn Radius [mm] Z0 = 70-OHM Z0 = 60-OHM Fig. 6. Normalized insertion loss Sd21 (db/mm) at turning radii R = 0.3mm up to 8mm and f = 14GHz for variations Z 0 = 60Ω and Z 0 = 70Ω Zdiff = 100 Ω for both design variations. Design of Glass Test Vehicle Design rules for the two variations of differential transmission line structures on a 76.2x76.2x0.13mm 3 glass test vehicle were developed based on modeling and simulation results described above and are summarized in Fig. 7 below. The test vehicle was fabricated on 130μm thin glass provided by Corning Inc. with through vias formed in the glass at 60μm diameter and 120μm pitch. Throughpackage-via diameter is not a critical design parameter for the structures included in the test vehicle design shown in Fig. 8. Each test structure used an array of vias to provide a signal return path and signal via transitions were not considered for characterization. Parameter Glass thickness (hglass) Via diameter (D) Via pitch (P) Copper thickness (hcu) Titanium seed thickness (hti) Line width 1 (W1) Line space 1 (S1) Line width 2 (W2) Line space 2 (S2) Design Specification 130μm 60μm 120μm 8.0μm (nominal) 0.1μm (nominal) 155μm 120μm 100μm 54μm Fig. 7. Glass panel design rules, where W1 and S1 describe line and space requirement for Z 0 = 60Ω and W2 and S2 describe line and space requirement for Z 0 = 70Ω. 2190

4 B titanium seed layer and nm thick copper seed layer. After seed layer deposition, 15μm thick dry film photoresist (DFR) was roll laminated at T = 115 C on both sides of the glass. An exposure time of t = 5.0s was used for DFR patterning. Electrolytic plating with I = 5.7A for t = 18min was used to deposit approximately 8μm of copper to form the signal and ground layers, after which the DFR was removed and seed layers were etched. To prevent degradation of copper structures, a hydrofluoric acid (HF) flash etch (t = 10-20s) was used to remove the titanium seed/adhesion layer. Due to the short processing time, this flash etch step did not affect the quality of the copper traces on glass in terms of surface roughness. C Glass Panel Fabrication Process Flow Via drill Ti/Cu seed layer sputter Dry film resist roll lamination E-lytic plating Fig x76.2 mm 2 glass panel layout of differential transmission line test structures at various line length (L = 1-50mm) and turn radius (R = mm). - Detail of differential transmission line test structures with RF probe pads at 250μm pitch. Structures included in the test vehicle were: straightline differential traces at L = 1, 5, 10, 15, 30, and 50mm, turning differential traces at R = 0.3, 0.4, 0.8, 1, 2, 4, and 8mm, and fan-out structure for a COTS TIA with 150μm chip-level bump pitch. These test structures included both the Z 0 = 60Ω and Z 0 = 70Ω variations. Note that the fan-out structure was not designed for high-frequency characterization using RF probes, and was used to verify the fabrication process capability for a system architecture similar to the schematic shown in Fig. 1. Glass Panel Fabrication and Results The glass test vehicle fabrication process flow is summarized in Fig. 9 and is based on a low-cost, panel-scale, double-side process to form two-metal layers on bare glass. A titanium-copper seed layer was sputtered on glass samples with pre-drilled TPVs. The titanium was used as an adhesion layer between the bare glass and copper metallization, while the copper seed layer thickness was optimized for uniform conductivity during subsequent electrolytic plating. The total sputtering time for titanium and copper was t = 20min and t = 40min respectively, resulting in a 100nm thick Dry film resist strip Cu seed layer etch Ti seed layer HF etch Fig. 9. Test vehicle fabrication process using SAP metallization. The fabrication results using the above processes are summarized in Fig. 10. Fan-out structures for Z 0 = 60Ω and Z 0 = 70Ω are shown in Fig. 10a and Fig 10b, respectively. The fabricated line widths and spaces for the Z 0 = 60Ω design variation were 161μm and 116μm respectively, a difference of < 4.0% compared to the designed dimensions. The fabricated line widths and spaces for the Z 0 = 70Ω variation were 102μm and 55μm respectively, a difference of 2.0% compared to the designed dimensions. This variation may be attributed to several possible sources of error including: mask fabrication tolerance, mylar mask expansion during UV exposure, or incorrect exposure dosage. Therefore, it is expected that such variations in fabrication can be addressed by using a glass mask and further process optimization. The cross-section micrographs for these structures are shown in Fig. 10c and Fig. 10d. In the cutout of Fig. 10d, the copper thickness was measured to be near the design target of 8μm. There was some variation of copper thickness across the 76.2x76.2 mm 2 panel, with a minimum measured copper thickness of approximately 5.6μm. 2191

5 54.7 um um References 1. Knickerbocker, J.U. et al., "2.5D and 3D technology challenges and test vehicle demonstrations," Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd 5x um um 5x 2. Xiaoxiong Gu et al., "High-density silicon carrier transmission line design for chip-to-chip interconnects," Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on 250 um 10x 100 um 10x (cutout 50x) (d) Fig Fan-in test structures for Z 0 = 60Ω and Z 0 = 70Ω respectively; Cross section of Z 0 = 60Ω differential transmission line structure; and (d) Cross section of Z 0 = 70Ω differential transmission line structure (cutout showing copper metal thickness). Conclusions This paper presents for the first time the modeling, design, and demonstration of high-speed differential transmission lines using an ultra-thin 130μm glass substrate with TPV to achieve 16-channel, 28 Gbps per channel signaling. The low loss and ultra-smooth surface of glass, combined with the low resistive, thick copper metallization, is expected to provide for a higher-performance solution compared to silicon interposers fabricated using BEOL processes. Furthermore, the high modulus and dimensional stability of glass can be leveraged to improve optical fiber alignment to photonic dies, required for 2.5D photonicelectronic interposers. This paper presented the electrical modeling and simulation used to develop an optimized design for a 16x28 Gbps I/O interface with a two-metal layer glass interposer. Using this design, an ultra-thin 130μm glass test vehicle was fabricated using low-cost, double-side panel processes. The measured structures in the glass interposer showed excellent correlation with the modeling and design. Glass interposers combining electrical and optical signal transmission between chips assembled at close proximity, offer a great potential for high-speed electronic and photonic system integration. Acknowledgments Research results described above are part of the Low-cost 3D Glass Interposers and Packages (LGIP) program at Georgia Tech Packaging Research Center (GT-PRC). The authors acknowledge those LGIP member companies and supply chain partners in supporting this research effort. 3. Namhoon Kim et al., "Channel design methodology for 28Gb/s SerDes FPGA applications with stacked silicon interconnect technology," Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd 4. Sawyer, B. et al., "Modeling, design, fabrication and characterization of first large 2.5D glass interposer as a superior alternative to silicon and organic interposers at 50 micron bump pitch," Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th 5. Oi, K. et al., "Development of new 2.5D package with novel integrated organic interposer substrate with ultrafine wiring and high density bumps," Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th 2192