Fraunhofer IZM - ASSID

Transcription

1 FRAUNHOFER-INSTITUT FÜR Zuverlässigkeit und Mikrointegration IZM Fraunhofer IZM - ASSID All Silicon System Integration Dresden

2 Heterogeneous 3D Wafer Level System Integration 3D system integration is one of the most important strategic key technologies in microelectronic packaging and system integration worldwide. With 3D wafer level system integration technologies, multiple electronic devices such as sensors, processors, memories, transceivers, can be integrated heterogeneously into one wafer level system-in-package (WL-SiP). The heterogeneous wafer level integration approach has specific advantages in terms of electrical performance, form factor and manufacturing cost. Therefore current scientific and industrial research is focusing on developing 3D integration technologies, particularly for manufacturing process integration. Our main technologies include: 3D wafer-level system integration (300 mm wafer) Through silicon via technology Silicon interposer technology with high-density wiring Wafer thinning and handling technology Temporary wafer bonding and debonding technology Wafer bumping technology Die-to-wafer and wafer-to-wafer bonding Wafer-level assembly and 3D stacking Roadmap 3D Wafer-Level System Integration 3D TCI / TSV 3D Interconnect Complexity WLP WITH TSV Controller / Memory Stacks ewlp 3d Image Sensor ewlp WITH TMV Stacked Memory on TSV Interposer HDI TSV Interposer HETERO INTEGRATION 3D Interposer with Cooling 3D CPUs FUNCTIONAL LAYER STACK µ egrain CIS DRAM Logic IPD & RDL Organic Interposer Fraunhofer IZM

3 Through silicon via (TSV) formation Through silicon vias (TSVs) are a key element in 3D wafer-level system integration. Fraunhofer IZM-ASSID develops copper TSV processes specifically for customized applications. All processes are carried out using latest state-of-the-art industrial equipment for 300 mm wafers. In TSV technology our focus is on: High-density TSV technology for advanced system performance (TSV diameter: 2 20 µm; aspect ratio: 5 to 30) TSV post-frontend and post-backend integration processes Cu-TSV filling using high-speed ECD Optimized and qualified TSV post-processes applied on wafer frontside and backside Evaluation and validation of new materials for TSV filling and isolation Optimized and qualified TSV post-processes applied on wafer frontside and backside Qualified high-yield TSV formation processes Wafer thinning, and Thin Wafer handling Wafer thinning and handling technologies are essential for the realization of 3D system architectures. Optimizing these technologies to meet specific requirements in wafer frontside and backside processing in 3D wafer level system integration remains complex. The increase of the wafer size to 300 mm poses additional challenges. In process development our focus is on: Optimization of temporary wafer-bonding and -debonding technologies (device wafer thickness: < 20 µm; multiple repeat bonding and debonding processes) Enhanced wafer thinning and stress relief technologies for ultra-thin wafers (< 20 µm) Enhanced dicing technologies using low k-materials, small dicing streets (< 40 µm) and reduced mechanical edge and corner damage to wafer frontside and backside

4 TSV-Interposer with high-density metallization Through silicon interposers are used as carriers for 3D architectures especially to meet the requirements of integrated circuits high I / O numbers and their high-density routing to the package or board. The technical requirements are defined by application-oriented system specification. According to the ITRS and SEMATECH roadmaps, multilayer high-density wiring on backside / frontside down to 2 µm line / space, as well as Cu- TSVs with diameters between 2 µm and 20 µm are required. The functionality of silicon interposers will be extended by the integration of passive devices, such as inductors, resistors and capacitors, with an emphasis on facilitating the development of RF applications. Future generations of silicon interposers will also include integrated active devices and will be designed for high power dissipation by means of innovative cooling architectures. We are also working on the integration of electrical optical interconnects. These new types of silicon interposers are the basic prerequisite for modularized 3D stacked architecture for fully heterogeneous integration on wafer level. In interposer technologies our focus is on: Interposers with high-density Cu-TSV High-density multilayer copper wiring (min. 2 µm line / space) Integration of passive devices (R, L, C) into the RDL Embedding of active and passive devices into the silicon interposer Compatible interconnects for 3D stacking of silicon devices and for assembly into the package or on the board Integration of cooling elements and optical interfaces Assembly and interconnection technologies Assembly and interconnection technologies relevant for 3D system integration are strongly affected by the IC technologies used in different products. Key parameters include die size, number of I / Os, pad geometries, terminal pad methodology and passivation layers, wafer-surface topologies and limitations to the thermal budgets that can be applied during assembly. Additional challenges in assembly and interconnect technologies for 3D systems include alignment accuracy, yield requirements and productivity that meet the demands of cost effective manufacturing. In assembly and interconnection technology our focus is on: Evaluation of die-to-wafer (D2W) and wafer-to-wafer (W2W) assembly technologies 3D IC assembly with high-density interconnects (> 1000 I / O) and ultra-fine pitch (< 50 µm) 3D IC assembly with thin and ultra-thin chips ( µm) 3D IC assembly on thin interposers mounted on carrier substrates (D2W) Evaluation of 3D low-temperature assembly technologies Evaluation of flux-free solder connections with self-alignment capability in 3D system integration Qualified 3D stack assembly processes

5 All Silicon System Integration Dresden Fraunhofer IZM-ASSID Fraunhofer IZM The Fraunhofer Gesellschaft is one of the leading organisations of applied research in Europe, undertaking contract research on behalf of industry, the service sector and the government. It maintains more than 80 research units in Germany, including 60 Fraunhofer Institutes. The Fraunhofer Gesellschaft s key objective is to transform scientific expertise into applications of practical utility. The Fraunhofer Institute for Reliability and Microintegration IZM is a worldwide renowned institute in the realm of microelectronic packaging and system integration. We specialize in developing advanced technologies and transferring research results to industrial applications for customer-specific solutions for microelectronic products in the overall scope of Smart System Integration. L e a d i n g edge microelectronic packaging a n d s y s t e m integration 300 millimeter w a f e r - l e v e l process line Fraunhofer IZM-ASSID Wafer level packaging and system integration has been one of Fraunhofer IZM s key competences for many years. According to the technical requirements of future microelectronic products 3D system integration becomes one of the main drivers whereas 3D wafer level technologies are among the most promising technologies for heterogeneous system integration. The center All Silicon System Integration Dresden (ASSID) with a 300 mm wafer process line has been established as part of Fraunhofer IZM to meet these specific challenges in performance, functionality and scaling requirements. Our new center has a state-of-the-art cleanroom facility and is equipped with a complete 300 mm process line for TSV formation, TSV post-processing on wafer front- and backside, 3D device stacking assembly, as well as testing and failure analysis. ASSID activities are embedded into the overall Fraunhofer IZM s 3D system integration strategy. The facility, infrastructure and know-how are especially tailored to partners in industry for research and development projects, as well as prototype realization. Fraunhofer IZM is a partner in different national, European and worldwide industrial and scientific networks for 3D System Integration, e.g. EMC 3D, HTA, Silicon Saxony, Euripides. Fraunhofer IZM-ASSID Targets Fraunhofer IZM-ASSID s vision is the heterogeneous integration of multi-functional electronic devices into one Wafer Level System-in-Package (WL-SiP) by using enhanced 3D integration, interconnection and assembly technologies. Fraunhofer IZM-ASSID develops leading edge technologies for 3D system integration on 200 / 300 mm wafer and provides solutions for customized product integration. Fraunhofer IZM-ASSID offers equipment, material and process evaluations for industrial partners. Fraunhofer IZM-ASSID services include the customer-specific qualification of processes and prototyping. Heterog e n e o u s w a f e r - l e v e l s y s t e m integration 5 I 6

6 Services Contact Apart from advanced packaging research and development, Fraunhofer IZM-ASSID also provides prototyping services. Its facilities are open to industry, institutes and universities for research and development activities, as well as material, equipment and process evaluation and improvement. Technological services include: TSV silicon interposer Deposition and patterning of dielectric polymers and metal films Redistribution layers (line / space: 10 / 10 µm) with customerspecific terminal pad metallurgies (Cu, Cu / Ni / Au, Cu / Sn) Wafer thinning and thin wafer processing Wafer-level bumping (Pb-free) Wafer-level solder ball attach ( µm) Wafer-level assembly Die attach (lamination, epoxy, flip chip) on various substrates Component assembly (bare die, active and passive SMD components) Customer-specific prototyping Fraunhofer IZM Dr. Klaus-Dieter Lang Gustav-Meyer-Allee Berlin Phone: +49 (0) Fax: +49 (0) klaus-dieter.lang@izm.fraunhofer.de URL: Fraunhofer IZM-ASSID Ringstr Moritzburg Germany Management and Coordination M. Jürgen Wolf Phone: +49 (0) (0) Fax: +49 (0) wolf@izm.fraunhofer.de TSV & Thin Film Layer Deposition Dr. Mathias Böttcher Phone: +49 (0) mathias.boettcher@assid.izm.fraunhofer.de Wafer Thinning, Handling, Assembly Dr. Jürgen Grafe Phone: +49 (0) juergen.grafe@assid.izm.fraunhofer.de Fraunhofer IZM-ASSID is supported by the Federal Ministry of Education and Research, the Free State of Saxony and the European Commission. Concept & Editing: Fraunhofer IZM Press and Public Relations, Berlin + M.Creutzfeldt / MCC Berlin Design: J. Metze / Atelier f:50 Berlin Photography: Fraunhofer IZM together with: Mario Müller (p. 2 top), all other Fraunhofer IZM ASSID 10/09-03e