Advanced Embedded Packaging for Power Devices

Transcription

1 2017 IEEE 67th Electronic Components and Technology Conference Advanced Embedded Packaging for Power Devices Naoki Hayashi, Miki Nakashima, Hiroshi Demachi, Shingo Nakamura, Tomoshige Chikai, Yukari Imaizumi, Yoshihiko Ikemoto, Fumihiko Taniguchi, Mitsuru Ooida, Akito Yoshida J-Devices Corporation, Amkor Technology, Inc. Yokohama, Kanagawa, Japan Abstract Power electronics is increasingly important in many industrial fields. Recently, in automotive, the demand for power packages in electric and hybrid vehicles has been rising. Those devices are required to have high thermal performance. However, conventional power device packages using wire assembly techniques have difficulty to meeting the requirements. To solve the problem, a new and expandable advanced package for power devices was developed using embedded dies and redistribution layer (RDL) technology. The new package has a low electrical resistance and good thermal performance due to heat dissipation through many via holes. A test vehicle was, designed and fabricated around the via structures process parameters. A fixed aspect ratio was used for the copper-filling plating and die attach film (DAF) material to provide sufficient adhesion. A fabricated test vehicle (TV) sample with embedded test element group (TEG) chip and live-die confirmed that the via structure is completely filled and connected correctly by the simple I-V curve measurements on this package. With its demonstrated thermal performance, this package should have many applications for future power devices. Keywords- Power device, embedded package, Panel Level Packaging, RDL, contact via, DAF, substrate, trace, power dissipation I. INTRODUCTION Power electronics is very important in many industrial fields. Power devices, including MOSFETs, IGBTs, and others, have been used for a long time as essential parts of power electronics for controlling or switching the current from the power source. Recently, in automotive applications, the demand for electric and hybrid vehicles has been rising [1] because of their fuel efficiency and concerns about the environmental pollution problems. The power devices in the power electronics circuits in those automobiles require high density assembly to obtain intelligent, high powered and reliable control. Additional requirements for each power device, including its package, dictate small size, fabricated with low cost manufacturing, and high thermal performance. However, conventional power device packages have miniaturization limits due to the use of a wire bonding process where each bond is fabricated one at a time. Moreover, the thermal performance is also restricted because the thermal flow inside the package only has a single path through the narrow metal wires to dissipate outward. Hence, a new package which has both small size and high thermal performance is definitely desirable. With that background, a new and expandable advanced package was developed for power devices to match the above requirements, which is one of the applications of previous work [4], [5]. The package uses a type of multilayer, laminated construction and can be fabricated using a printed circuit board (PCB) process. Power device chips are embedded in the laminated resin layer. The package size is very small and very thin due to well-controlled trace patterning, resin trace lamination, and trace metallization. In addition, the package has good thermal performance with low thermal resistivity and high power dissipation. Moreover, they have very low drain-source on resistance with low resistivity connections through many via holes. The package uses a re-distribution layer of a trace and multi-layer structure, so the pattern layout is easy to customize and there can be many types of devices including discrete or power module systems with integrated control driver chips. There are several technical issues for the fabrication of this package. First, there is the difficulty of filling in copper in the deep vias. The chips are mounted on a panel with copper foil as a copper base and a removable carrier sheet. Resin sheets used as an insulator layer are laminated over all the chips. The contact via is formed on the chips or on the copper base layer. Copper plating is employed to fill up the via and to provide electrically contacts. Since power semiconductor chips are much thicker than other semiconductor devices, the plating needs to be wellcontrolled. Second, a reliable method to contact the bottom side of the chip's pad is required. Most of the chips used for power device are vertical-type semiconductors which also have their pads with ohmic contact resistance at the bottom. So, a method to contact the bottom side of the chip after it is mounted with die attach film on the copper base layer is required. As part of the solution, a new chip contact structure was developed by forming contact with other vias through the die attach film. This structure must be well-controlled during the process to provide sufficient reliability. To confirm the thermal reliability of this structure, test vehicles were fabricated. In this paper, the outline of the new package structure is described and the expected mechanical and electrical /17 $ IEEE DOI /ECTC

2 characteristics of this package are confirmed through several methods. Electrical and thermal simulations of this package were initially performed and the details of the power dissipation and thermal resistance results will be presented. Second, the design and fabrication of a test vehicle for this package and the detail of its process flow using a PCB manufacturing process is explained. After that, the final inspection results of this test vehicle are shown. Finally, the high performance of the package for power devices is confirmed through the simple I-V tests. With its small size and good thermal performance, the package is well-suited for future power devices. II. PACKAGE DEVELOPMENT IN J-DEVICES Several different types of packages have been developed to improve their electrical and thermal characteristics. At J- devices, the roadmap of package types is shown in Figure 1 [2]. Most importantly, RDL interconnections are highly expected to realize higher speeds than flip-chip interconnections. In these technologies, the pattern and interconnection are formed concurrently by electrolytic plating. This provides a bump-less interconnection and can improve the electric performance for high frequency operation. It is assumed that further high speed transmission is required in next generation of electronic equipment. Figure 2 shows the standard type of package using RDL. A metal plate is used as a base plate on which dies are mounted with a die attach film. The dies are embedded in the insulator resin layer and connected with the RDL through via holes on each of die pads. The RDL includes some pattern of trace formed by a copper plating and etching process. Moreover, this package has demonstrated several thermal, mechanical and electrical characteristic advantages [4]. With these performance values, the package structure is well-suited for power devices. lower inductance, and higher power dissipation. The RDL package structure appears ideal for power devices, too. The structure of the package used as a test vehicle is shown in Figure 4. Dies for power devices have their pads on both the top and at the bottom. As a result, three types of contact vias were designed for each of the pads: on the top of and near the die through the insulator resin, and under the die through the DAF. But this structure had some technical issues. The vias near the die, or deep vias, should be much deeper than those of the standard type due to the thickness of the die, In contrast, the vias on top of the die, or shallow vias, should be formed with the deep vias at the same time in fabrication process. So, formation of those vias by copper plating poses issues for filling inside, and the proper designing of both via structure and process condition. There are also vias under the die, or bottom vias. They are formed through the DAF, which commonly has a larger thermal expansion coefficient than the trace or insulator resin. So the thermal reliability of the connections on the bottom vias had to be confirmed. Analysis of the package s electrical and thermal characteristics using simulation, and structure design of the three types of vias fabrication process and thermal reliability was performed. Figure 3. Road map of packages required for power devices. Figure 1. The packaging development roadmap in J-Devices [2]. Figure 4. The structure of the test vehicle package. Figure 2. The structure of the standard type of package using RDL [2]. III. EMBEDDED PACKAGE FOR POWER DEVICES Figure 3 shows a package road map required for power devices. In the future, higher electrical and thermal performance values are required, that is, lower resistance, IV. PACKAGE STRUCTURE ANALYSIS Using Ansys Q3D, the advantages of the package structure s electrical and thermal characteristics were compared to other conventional designs. A. Electrical Characteristics Figure 5 shows standard models that were used and compared to the new package structure and the electrical simulation results. RDL1 and RDL2 packages have trace thicknesses of 50 m and 250 m, respectively. LFPAK 697

3 represents one of packages which has a copper clip as the outer trace. D2PAK is used to compare the new package with as wire-bonding type package. Rds and Lds were calculated that are respectively defined as drain-source resistance on DC and inductance on AC while the FET is on. Figure 6 shows the results of the electrical simulation comparing the packages Rds. The Rds of the new package reduces the Rds of the wire bonded D2PAK by as much as 97%. The result means that the resistance with long and thin wires is much larger than with short and thick via holes. Moreover, the thick trace of 250 m in the new package is more effective. The Rds of the D2PAK could be reduced with many wires in parallel. However, the diameter and number of the wires will be limited while a smaller package size is required. The comparable results on Lds are shown in Figure 7. Lds of the new package is as much as 80% lower than D2PAK. That is because the wire traces need to be long and thin due to the step height between the bumps, which also increases the switching noise. In contrast, the RDL trace can be short and thick with a layer-by-layer structure, so the noise through the trace is much lower. Similar to the case of resistance, the wire's curved-form is also limited in a smaller package. As a result, the RDL structure has advantages for electrical characteristics required in a small package. B. Thermal Characteristics Thermal simulations were conducted on two types of module packages embedding two MOSFET chips and a controller chip. One type is conventional power quad flat no-lead (PQFN) (3in1) package in which the three dies are connected with wire trace and molded on one layer. The second one is the embedded package in which the two MOSFET dies are embedded in insulator resin on one layer and the controller chip is embedded in the upper layer. Those chips are connected with RDL trace and via holes. Figure 8 shows the results of the thermal simulation of the thermal resistance of heating flow through the junction in the dies to ambient, ja, and maximum junction temperature, Tjmax. Both parameters vary with the velocity of air flow. The embedded power package has better heat dissipation than the conventional package by 20% or 30%. The temperature distribution of the two packages is shown in Figure 9. The circles indicate the maximum temperature points in each model. They exist around the wires at PQFN model, and around the via holes in the embedded power package model. The reason is that the many via holes and wide plain trace in the power package has more effective thermal dissipation than the thick and long wires in PQFN package. Figure 5. Standard models used on electrical simulation Figure 6. Results of the electrical simulation comparing with several types of power package on Rds Figure 8. The results of the thermal simulation, thermal resistance, maximum junction temperature. Figure 7. Comparable results on Lds among several types of package 698

4 Figure 10. Cross-sectional views of test samples at the via having several aspect ratios, with resin thickness of 150 m, 300 m. Figure 11. Definition of filling ratio, M. Figure 9. The temperature distribution of the two packages, PQFN as reference, embedded Power Package. Circles indicate the area with the maximum temperature. V. STRUCTURE DESIGN OF THE VIAS A. Selecting the Via Size A copper filling test was conducted with various via aspect ratios. Figure.10 shows the cross-sectional views of those samples. The higher aspect ratio can get filled-vias, but it is also at high risk of voids in vias. On the other hand, the lower aspect via is close to the conformal via. Several samples were checked which had different aspect ratios. The plating conditions of each sample are all the same. The via filling ratio M, which is defined by the copper thickness of the surface and inside via as shown in Figure.11, strongly depends on the aspect ratio shown in Figure 12. When the aspect ratio is less than 0.8, M is less than 20% and the via is conformal. In the area where aspect ratio is around 1.0 to 1.5, the process repeatability is poor and some voids were found in the several vias in one sample. When aspect ratio is more than 1.5, the plated copper at the bottom of the via is missing or there were some voids. This analysis shows that the aspect ratio should be controlled around 0.8. Figure 12. Filling ratio versus aspect ratio on several copper plating samples. B. Via Formation in DAF Fabrication of the bottom via in DAF was a major technical challenge. A proper DAF material must achieve fine shapes of the vias by the laser drilling process and keep them in tact through a de-smear process. In the de-smear process, the DAF is etched and roughened sufficiently to have enough peel strength with the copper filling the via, but it could cause delamination depending on the process conditions. To determine the proper material, simple test was conducted with several different DAF materials to select the ones which have strong adhesion on the die or substrate through the de-smear process. Each of the materials are attached on the rough-surface substrate, and loaded in the de- 699

5 smear process. Only two materials; A and B, are remained on the substrate as shown in Figure.13. Next, vias were fabricated in the two DAFs by laser drilling and subjected to the de-smear process again. After inspection, material A was chosen as the DAF for the TV sample due to the fine shape of via as shown in Figure.14. Figure 13. The results of DAF delamination test before and after de-smear process from only four of the several materials that were tested. Figure 15. SAT image through the MRT, before and after Figure 16. Cross-sectional view of bottom vias after MRT. VI. TEST VEHICLE FABRICATION Figure 14. Inspection result of via in DAF material A and B after formation by laser drilling and de-smear. C. MRT of Bottom Via Connection The thermal stability of the via connection comprising the DAF and copper had to be confirmed because it is used as the bottom via in the package structure. To do this, a moisture resistance test (MRT) of the via connection was conducted. The samples were fabricated consisting of daisychain circuitry and inspected before and after the MRT. The scanning acoustic tomography (SAT) images are shown in Figure 15. The cross-sectional view of the daisy chain at the bottom of the vias in this sample had no problem as shown in Figure 16. No delamination or cracks were found after MRT of this via design. A. Process Flow As mentioned previously, the parameters for the package, including DAF material, via size, and resin thickness were chosen using the results of the previous tests. Test vehicle samples were fabricated with the design parameters in the RDL package as follows. Figure 17 shows the process flow of the TV samples. The first step is the pattern L1 formation; the substrate for attaching dies is fabricated on one panel by patterning the trace L1. Next is the die attach; a die is attached face-up on the substrate with DAF. In the insulator Resin Lamination step, the die is embedded in resin forming insulator layer by a lamination instrument. For via formation, the deep vias beside the die and the shallow vias on the die are formed by laser drilling into the resin. In the pattern L2 formation, the vias are filled by copper plating with trace layer L2 formed by patterning the plated copper layer. In the layer L3 formation, after peeling off the substrate, vias are formed in the DAF from bottom side of the die, with copper plating used to fill the bottom dies and to form the top of the package. In the SR formation step, the solder resist layer is laminated and patterned to open the windows for solder balls. Singulation at the end of the process, results in each package cut off the panel as a TV sample by a dicing cutter. 700

6 (c) Figure 18. The final inspection of the TV sample, bottom side, top side, (c) X-ray Figure 19. Cross-sectional view of the TV sample Figure 17. Process flow B. Final Inspection The final inspection of the TV sample is shown in Figure 18. The die is a type of TEG that includes a daisy chain to check the connection through the vias. There are four daisy chains across the vias. The deep vias can be seen at both sides of the package under the SR layer in the X-ray. Figure 19 shows a cross-sectional view of the package, and Figure 20 shows each of three types of via. Voids, cracks, or missing plating spots are not seen in any cross-section due to the appropriate design of parameters and well-controlled copper plating. The resistance of the whole daisy chain on TEG resulted in less than 0.4ohm, indicating a complete connection though the vias. 701

7 (c) Figure 20. Cross-section of three types of via, deep vias, shallow vias, (c) bottom vias, in view with package top side down. C. Embedding Live-Die Applying the design and process of the TEG sample, another package was fabricated embedding a live-die, that is, a MOSFET die. Figure 21 shows final inspection of the live-die sample. It has three types of pads for solder ball connections to the gate, source and drain which are connected through the vias to each of the MOSFET's pads. The x-ray observation shows a large plain pad as the source with many shallow via holes completely filled. To confirm the via connection and the package's function as a power device, a simple I-V test of the MOSFET was performed. The results of I-V curve tests depending on the gate voltage are found in Figure 22. Even though the drain current is a bit small, it is obvious that all of the vias are connected correctly. Reliability testing of this sample is the next step but is not reported at this time. Figure 22. I-V curve on gate voltage of the live-die TV Figure 21. Appearance of the live-die TV, Outline, X-ray observation VII. SUMMARY AND CONCLUSIONS Power devices are used in advanced products in several market segments. In automotive applications, the revenue is increasing rapidly, especially with the introduction of more and more electric and hybrid vehicles. The power devices used in those applications need to have large power capacity and have to work at high frequency. This requires the devices to have low on-resistance, low thermal resistance, and reduced switching noise. At the same time, they also require miniaturization for high density assembly devices to perform as multi-devices. However, it could be difficult to meet those requirements with conventional packages. The proposed solution is an embedded die package for power devices, which is one of applications of RDL packages from previous work. In this package, the die is embedded in the insulator resin, and via holes filled with copper are formed to connect the die pads with the redistribution layer. This package has three different types of vias to connect both top and bottom side of the die with the RDL, and between the RDLs. Specifically, the vias for the bottom side of the die are formed through the DAF. Simulations have been performed to confirm the electrical and thermal performance of this package. Better characteristics were obtained compared other packages, 702

8 proving that the vias are effective if reliable fabrication occurs. Process parameters were designed around via structures to determine a fixed aspect ratio for copper filling and a DAF material that provided sufficient adhesion through the process. Through test measurements, reliable connections of the vias were confirmed. Finally, TV samples fabricated with embedded TEG chips and live-dies, provided that the via structure is formed completely by measuring simple I-V curve on the package. ACKNOWLEDGMENT The authors deeply appreciate the cooperation by the support members in Research Center of Three-Dimensional Semiconductors on fabrication of the TV samples, and all of the people helping hands with development of this package. REFERENCES [1] New Venture Research Corp., The Worldwide IC Packaging Market, 2016 Edition. [2] M. Ooida, F. Taniguchi and T.Iwasaki Advanced Packaging Technologies supporting new semiconductor application, ICSJ. [3] H. Matsubara, T. Chikai, N. Hayashi, T. Iwasaki and F. Taniguchi, Thermal Properties at Package Elements for Power Management of Embedded Device Package, MATE2016. [4] N. Hayashi, H. Machida, N. Shintani, N. Masuda, K. Hashimoto, A. Furuno, K. Yoshimitsu, Y. Kikuchi, M. Ooida, A. Katsumata and Y. Hiruta, A New Embedded Structure Package For Next Generation, WFOPTM (Wide Strip Fan-out Package), SMTA Pan Pacific [5] N. Hayashi, T. Takahashi, N. Shintani, T. Kondo, H. Marutani, Y. Takehara, K. Higaki, O. Yamagata, Y. Yamaji, A. Katsumata and Y. Hiruta, A Novel Wafer Level Fan-out Package (WFOPTM) Applicable to 50um Pad Pitch Interconnects, EPTC