SiP packaging technology of intelligent sensor module. Tony li
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1 SiP packaging technology of intelligent sensor module Tony li
2 Contents What we can do with sensors Sensor market trend Challenges of sensor packaging SiP technology to overcome challenges Overview of JCET 2
3 What we can do with sensors Smart everything is the biggest trend, and the intelligent sensor module is the basis. Smart and Connected Car Smart and Connected Home Smart and Connected City Smart and Connected Body 3
4 What we can do with sensors Sensors and application for IoT 4 Souce:Yole
5 Sensor market trend Sensor market for wearables as a case 5 Souce:Yole Sensors for wearables could reach a total number of 1.2Bunits by 2020
6 Challenges of sensor packaging Size reduction Souce:Yole 6
7 SiP technology to overcome challenges High level of integration Souce:Yole Combo sensors are the trend for inertial sensor market 7
8 SiP technology to overcome challenges Hybrid SiP packaging technology for magnetic sensor in JCET Au wire Cu pillar joint substrate with solder paste WB chips Side FC Technology Features 2 die stack WB with Au wire. Side(Vertical) FC capability with Cu pillar. Min package size: 1.6*1.6*0.65mm Min die size: 0.47*0.47mm MEMS assembly MP started at Side FC WB chips 8 With the hybrid SiP packaging technology, the module can be smaller.
9 SiP technology to overcome challenges RF module in JCET Technology Features Cu pillar bumping: 150um pitch FC + SMT Components+IPD module SMT component: Min Die thickness: Min 100um RF module integrated with antenna The FC, IPD, and integrated antenna improve RF performance of the module. 9
10 SiP technology to overcome challenges Ceramic package in JCET Side view Ceramic lid Picture of real products Sealing epoxy Ceramic substrate Bottom view Side view Inner wire bonding Commonly used for applications requiring high performance and high reliability. An ideal package type for sensors(relatively low CTE and the cavity construction) 10
11 SiP technology to overcome challenges Cavity construction Cavity on chip Cap Glass cap Sensor wafer Solder ball TSV Solder ball Sensor wafer Cavity on package Mold compound Sensor wafer Bump Solder ball Substrate 11
12 SiP technology to overcome challenges WLP and TSV technology for CIS in JCET 12
13 SiP technology to overcome challenges TSV technology used in MEMS sensor Souce:Yole With the TSV technology, package size can be reduced almost by 55% 13
14 SiP technology to overcome challenges TSV technology in JCET TSV capabilities: TSV Assembly/Packaging (BEOL), TSV Post-Process (MEOL), TSV Silicon Interposer Technology and IPD compatible Enabling 2.5/3D package for low power, high performance devices in the mobile, wireless connectivity and networking markets Higher interconnect density and greater space efficiencies compared with traditional wirebonding and flip chip stacking by means of face-to-back and face-to-face bonding Micro bump technology for 50/40um u-bump plating 14
15 SiP technology to overcome challenges IPD technology in JCET WiMAX Balanced Filter GSM Balun IPD with TSV Embedded RLC components with excellent performance Resistors to 100,000 ohms, Capacitors range: 0.2pF-100pF, Inductors to 30nH, IPD diplexers, filters for wireless applications Adding TSV to the IPD structure results in a unique high functionality solution 15
16 SiP technology to overcome challenges Package level of EMI shield Sputter shielding technology Metal lid shielding technology Sputtered shield layer Metal can shield SiP module SiP module PCB board PCB board Traditional metal lid of EMI shield Package level of EMI shield The advantages of package level of EMI shield: 1, Save space of the PCB board, and make design layout for PCB much flexibility 2, Do not need to design metal can shield. 3, Make the package size much more smaller and thinner. Used in RF module, WiFi/BT module, RF module integrated with sensors, etc. 16
17 Overview of JCET Group Founded in 1972 and headquartered in Jiangsu, China Listed on Shanghai Stock Exchange in 2003 Largest OSAT in China and 4 th largest OSAT worldwide 2015 Ranking of OSATs Worldwide JCET Group Product and Service 19% Assembly Test 81% Source: Gartner (April 2016) *JCET Group based on JCET+SCL 2015 results Source: Gartner (April 2016) Note: JCET Group based on JCET+SCL 2015 results 17 JCET Group provides a comprehensive portfolio of packaging solutions ranging from discrete, leadframe and laminate packages to the most advanced flip chip and wafer level technology Strong IP portfolio and innovation in advanced technologies Significant manufacturing scale with factories strategically located in China, Singapore and Korea *Estimate based on JCET + SCL 2014 results.
18 Wirebond Packaging Combined Product and Service Offerings Packaging Type Product Category Laminate PBGA FBGA (Stacked Die) SIP PoP LGA MEMS Smart Card Packaging Type Leaded QFN DFN QFP SOP SOT DIP FCOL MIS SIP Packaging Type TO Diodes MOSFET Discrete SOD SOT Transistors BRT Rectifier TRIACS FBP TVS DFN 18
19 Testing Advanced Packaging Combined Product and Service Offerings Flip Chip Packaging Type fcfbga fcbga fccube Bare die fcpop Molded Laser fcpop Fan-in WLCSP ewlcsp Wafer Level Fan-out ewlb (2D, 2.5D, 3D) Integrated Passive Devices IPD Through Silicon Via TSV Test Platform Mixed Signal UltraFLEX, FLEX, Tiger Catalyst 93K PS400, PS800 ETS 300 / 364 Fusion CX Digital RF Memory UltraFLEX, FLEX / microflex, Catalyst 93K PS400, PS800 Fusion CX UltraFLEX, FLEX Catalyst 93K Portscale Fusion CX Magnum, Maverick (1PT / 1 VT / 1 / 2GT) T
20 Strongest IP Portfolio in OSAT Industry Patents Issued by the US Patent & Trademark Office JCET Group ASE Amkor SPILL Leading the OSAT industry with highest number of issued patents in the US and China Total number of US patents issued to STATS ChipPAC as of 1Q 2016 was 1546 Total number of patents issued to JCET/JCAP as of 1Q 2016 was 1011 Over 66% of JCET Group patents are related to MIS, advanced wafer level and flip chip technology 20 Source : Based on Patent Information Published in USPTO Website and SCL s product categorization.
21 Innovations for Value Date 21
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