Min Tao, Ph. D, Ashok Prabhu, Akash Agrawal, Ilyas Mohammed, Ph. D, Bel Haba, Ph. D Oct , IWLPC

Transcription

1 PACKAGE-ON-PACKAGE INTERCONNECT FOR FAN-OUT WAFER LEVEL PACKAGES Min Tao, Ph. D, Ashok Prabhu, Akash Agrawal, Ilyas Mohammed, Ph. D, Bel Haba, Ph. D Oct , IWLPC 1

2 Outline Laminate to Fan-Out WLP Transition FOWLP POP Key Elements POP Interconnect Features Conclusion 2 Oct 18-20, 2016 IWLPC

3 Outline Laminate to Fan-Out WLP Transition FOWLP POP Key Elements POP Interconnect Features Conclusion 3 Oct 18-20, 2016 IWLPC

4 Fan-Out Evolution OSAT / wafer foundries Opportunity area for wafer/panel level Fan-Out solutions Evolving 100um Substrate design Rule 10um ~ 8 2um 2um 4 Oct 18-20, 2016 IWLPC

5 Package Stacking Transitioning PIP Redistributed bonding pads 2.5D stacking with mostly wirebond based approach 5 Oct 18-20, 2016 IWLPC

6 Package Stacking Transitioning PIP Laminate POP Redistributed bonding pads 2.5D stacking with mostly wirebond based approach Solder only 1st Gen POP TMV Warpage control BVA Finer POP pitch 6 Oct 18-20, 2016 IWLPC

7 Package Stacking Transitioning PIP Redistributed bonding pads Laminate POP FOWLP POP 2.5D stacking with mostly wirebond based approach Solder only 1st Gen POP Chip last Wafer Level process replacing laminate substrate with thinner RDLs TMV Warpage control Chip first Achieving lowest stack profile with improved performance with RDLs built directly on chip BVA Finer POP pitch 7 Oct 18-20, 2016 IWLPC

8 POP Driving FOWLP Growth Source: POP is the major application to drive FOWLP market 4~5 X growth to $2.5B in Oct 18-20, 2016 IWLPC

9 Outline Laminate to Fan-Out WLP Transition FOWLP POP Key Elements POP Interconnect Features Conclusion 9 Oct 18-20, 2016 IWLPC

10 FOWLP POP Key Ingredients FOWLP 10 Oct 18-20, 2016 IWLPC

11 FOWLP POP Key Ingredients Manufacturing : Panel OR wafer FOWLP 11 Oct 18-20, 2016 IWLPC

12 FOWLP POP Key Ingredients Chip: First (face up OR face down) OR Last Manufacturing : Panel OR wafer FOWLP 12 Oct 18-20, 2016 IWLPC

13 FOWLP POP Key Ingredients Chip: First (face up OR face down) OR Last Manufacturing : Panel OR wafer FOWLP Vias: Formed post mold OR Preformed 13 Oct 18-20, 2016 IWLPC

14 FOWLP POP Key Ingredients Chip: First (face up OR face down) OR Last Manufacturing : Panel OR wafer FOWLP Vias: Formed post mold OR Preformed 1 st side RDL(s): after molding OR before molding on a carrier 2 nd side RDL: if needed 14 Oct 18-20, 2016 IWLPC

15 FOWLP POP Key Ingredients Chip: First (face up OR face down) OR Last Vias: Formed post mold OR Preformed Manufacturing : Panel OR wafer FOWLP 1 st side RDL(s): after molding OR before molding on a carrier 2 nd side RDL: if needed Molding 15 Oct 18-20, 2016 IWLPC

16 FOWLP POP Key Ingredients Chip: First (face up OR face down) OR Last Vias: Formed post mold OR Preformed Manufacturing : Panel OR wafer FOWLP 1 st side RDL(s): after molding OR before molding on a carrier Reliability: copper bumped die OR thick dielectric added 2 nd side RDL: if needed Molding 16 Oct 18-20, 2016 IWLPC

17 FOWLP POP Key Ingredients ewlb POP Chip: First (face up OR face down) OR Last Manufacturing : Panel OR wafer FOWLP Reliability: copper bumped die OR thick dielectric added Molding SLIM/SWIFT BEOL/RDL Vias: Formed post mold OR Preformed 1 st side RDL(s): after molding OR before molding on a carrier 2 nd side RDL: if needed 17 Oct 18-20, 2016 IWLPC

18 Chip First Facing Down: ewlb POP Source: S. W. Yoon et. al., IWLPC, Oct 18-20, 2016 IWLPC

19 Chip First Facing Down: ewlb POP Manufacturing : wafer Reliability: thick dielectric added Source: S. W. Yoon et. al., IWLPC, 2011 Chip: First face down) ewlb POP Molding Vias: preformed (embedded PCB vias) 1 st side RDL(s): after molding 2 nd side RDL: No 19 Oct 18-20, 2016 IWLPC

20 Chip First Facing Down: ewlb POP Manufacturing : wafer Reliability: thick dielectric added Source: S. W. Yoon et. al., IWLPC, 2011 Chip: First face down) ewlb POP Molding ewlb POP: Vias: preformed (embedded PCB vias) Chip first, face down; RDL L/S 10/10um; 1 st side RDL(s): after molding Preformed vias by embedding laminate PCB with through-vias; Min via pitch ~ 0.27mm 2 nd side RDL: No 20 Oct 18-20, 2016 IWLPC

21 Chip First Facing Up : InFO POP Source: C.F. Tseng, et. al., ECTC 2016 Source: System Plus Consulting 21 Oct 18-20, 2016 IWLPC

22 Chip First Facing Up : InFO POP Source: C.F. Tseng, et. al., ECTC 2016 Chip: First face Up) Manufacturing : wafer InFO POP Reliability: Tall Cu pads and thick dielectric added Molding Source: System Plus Consulting Vias: preformed (plated Cu pillars) 1 st side RDL(s): after molding 2 nd side RDL: PI only 22 Oct 18-20, 2016 IWLPC

23 Chip First Facing Up : InFO POP Source: C.F. Tseng, et. al., ECTC 2016 Chip: First face Up) Manufacturing : wafer InFO POP Reliability: Tall Cu pads and thick dielectric added Molding Source: System Plus Consulting InFO POP: Vias: preformed (plated Cu pillars) Chip first, face up; 1 Fan-in RDL + 3 Fan-out RDL; Preformed vias by plated Cu pillars; Via pitch 300um (could be as low as 60um) 1 st side RDL(s): after molding 2 nd side RDL: PI only 23 Oct 18-20, 2016 IWLPC

24 Chip Last: SWIFT and SLIM Source: Amkor White Paper 24 Oct 18-20, 2016 IWLPC

25 Chip Last: SWIFT and SLIM Manufacturing : wafer Reliability: Flip chip Chip: Last (flip chip) SWIFT/ SLIM Molding Source: Amkor White Paper Vias: Postformed (TMV) 1 st side RDL(s): before molding 2 nd side RDL: No 25 Oct 18-20, 2016 IWLPC

26 Chip Last: SWIFT and SLIM Chip: Last (flip chip) Manufacturing : wafer SWIFT/ SLIM Reliability: Flip chip Molding SLIM and SWIFT: Source: Amkor White Paper Vias: Postformed (TMV) 26 Oct 18-20, 2016 IWLPC 1 st side RDL(s): before molding Chip last with a flip chip reflow step; Finer L/S with SLIM BEOL layers; TMV like via by laser opening; Min Via pitch ~ 0.30mm 2 nd side RDL: No

27 Outline Laminate to Fan-Out WLP Transition FOWLP POP Key Elements POP Interconnect Features Conclusion 27 Oct 18-20, 2016 IWLPC

28 Chip Last Process Flow with Preformed Vias Release tape 1, Carrier wafer/panel with release tape 5, Overmold to cover die and POP Vias RDL Passivation POP Pad C4 Pad UBM 2, Build up RDL (second level UBM -> RDL -> C4 & POP pads) Preformed Vias (BVA or etched) 6, Grind back the mold to reveal the Via pads; optional 2 nd side RDL 3, Preform POP Vias on the wafer/panel (wire bond, etched, etc.) Die SoD 7-9, Remove carrier wafer/panel; Ball attach; singulation Fan-in RDL pads for POP connectivity 4, Flip chip attach dies with solder on pads, reflow to make joints Final Package with 2 nd side RDL 28 Oct 18-20, 2016 IWLPC

29 Preformed Vias Etched Cu upilr upilr is a scalable Fine Pitch Interconnect Technology with etched Cu post, suitable for POP, flip chip and BGA Etched Cu upilr Pillar on Substrate After stacking upilr POP: - Batch process fine pitch interconnect, min Pitch 150~200um - Good wetting and self-alignment capability for solder reflow - Superior drop and T/C performance compared to BGA An earlier upilr POP implementation 29 Oct 18-20, 2016 IWLPC

30 Preformed Vias BVA BVA is a Very Fine Pitch Vertical Wirebond Interconnect Technology, ideal for POP BVA Vertical Interconnects BVA POP: - Utilize existing wire bond facilities - Fine pitch capability of 150um - Validated HVM feasibility with a Tier 1 OSAT 30 Oct 18-20, 2016 IWLPC

31 BVA on RDL Bondability Study JEDEC Requirement TV: 10um PI with 5um Cu pad on 4 wafer All test legs passed JEDEC ball shear requirement with high margin BVA shows good bondability on RDL Ack: Tong Hsing Electronics 31 Oct 18-20, 2016 IWLPC

32 Cost Per Interconnect (Normalized) Cost Comparison Plated Cu Pillar BVA Wire Laser Drilled TMV Pitch ~0.3mm Pitch ~0.2mm Pitch ~0.16mm Estimated # of POP IO per 15X15mm WLP Ack: Savansys Solutions Sequential process has cost advantage up to ~800 IOs per package (15x15mm WLP on 12 inch wafer, all with 200um tall interconnect) 32 Oct 18-20, 2016 IWLPC

33 Interconnect Technology Comparison POP Interconnect BVA Wires/ Etched Cu posts Chip first, face up Compatibility ("X" for compatible) Chip first, face down Chip last Backside RDL Min Pitch X X X 0.15mm Plated Cu Pillars X X X 0.06mm- Through Mold Lased Vias X 0.30mm Solder balls X 0.4mm+ PCB Through-Vias X X X 0.27mm 33 Oct 18-20, 2016 IWLPC

34 FOWLP POP Comparison ewlb POP InFO SLIM/SWIFT upilr/bva Process flow Chip (face down) Interconnect (PCB through-vias) RDL Features - Mature FOWLP process; Limitations - Coarse POP pitch; - Process/material complexity Interconnect (Plated Cu pillar) Chip (face up) RDL - Thinnest POP in market; - Finest POP pitch - Package cost - Warpage 34 Oct 18-20, 2016 IWLPC BEOL/RDL Chip (flip chip) Interconnect (TMV) - Fine L/S (BEOL); - Chip last - Package cost - Thickness RDL/ Laminate Interconnect (etched Cu pillar, vertical BVA) Chip (flip chip) - Preformed POP Vias at fine pitch; - Process yield and reliability - BVA Sequential process; - Infrastructure compatibility

35 Conclusion Laminate to Fan-Out WLP Transition POP SoC requirement of IO density, thickness, and L/S drives transition to FOWLP 35 Oct 18-20, 2016 IWLPC

36 Conclusion Laminate to Fan-Out WLP Transition POP SoC requirement of IO density, thickness, and L/S drives transition to FOWLP FOWLP POP Key Elements Main distinguishing feature among FOWLP approaches is Chip first or Chip last, which impacts cost and yield 36 Oct 18-20, 2016 IWLPC

37 Conclusion Laminate to Fan-Out WLP Transition POP SoC requirement of IO density, thickness, and L/S drives transition to FOWLP FOWLP POP Key Elements Main distinguishing feature among FOWLP approaches is Chip first or Chip last, which impacts cost and yield POP Interconnect Features Cu post offers finest pitch and thinnest package BVA and upilr are fine pitch alternatives utilizing existing assembly infrastructure 37 Oct 18-20, 2016 IWLPC

38 Acknowledgement Tong Hsing Electronics for bondability study Savansys Solutions for BVA cost analysis Hala Shaba and Rajesh Katkar from Invensas team for FA support 38 Oct 18-20, 2016 IWLPC

39 Thank you! 39 Q&A Contact Info: Min Tao Tel: