3D integrated POL converter

Transcription

1 3D integrated POL converter Presented by: Arthur Ball I- 1

2 Motivation for this work Today s typical approach for >15A output Point of Load converters: Use PCB material for the entire circuit layout. Need heat sink or fan. In some cases, the entire backside of board is a heat sink. Thermally limited output. In many cases, the devices could do more but the circuit has to be derated. I- 2

3 Limitations of current approach Simplified schematic: Heat sink Devices Thermal paste PCB (e.g. FR4) Issues with current approach: 1. Heat sink is often necessary hurts power density and profile 2. Layout must conform to heat sink may not be most efficient 3. PCB material contributes very little to circuit cooling I- 3

4 New approach Conventional way Heat sink Devices Thermal paste PCB (e.g. FR4) Thermally-improved way Bare die devices DBC Heat spreader New way allows for true double-sided cooling I- 4

5 Thermal advantages 1. AlN DBC is 38x more heat conductive than PCB 2. Integrated thermal management replaces heat sink 3. Heat spreads easily in all directions 4. More even temperature distribution on surfaces This increases effective convection surface area 5. Power path and devices are directly bonded to DBC for rapid heat removal I- 5

6 Motivation for this work The dominant failure in power electronic systems is thermal I- 6

7 Stacked Power process Embedded devices allow for layering on both sides Thermal management is integrated using DBC layers Example: Buck POL operating at 1.3 MHz, 5V 1.2V This is our long-term goal for a fully integrated POL: AlN DBC heat spreader & interconnect AlN DBC with embedded devices AlN DBC heat spreader & interconnect 100 µf decoupling cap layer LTCC Inductor layer I- 7

8 Challenges High power density goal, ~ 150 W/in 3 in free space New processes are needed to achieve integration High frequency to reduce output cap = 1.3 MHz Low parasitic inductances for less loss Making the Interconnections Connecting the different layers while keeping parasitic inductance low Interfacing with the load Making a capacitor layer of high value capacitance So far we are concentrating only on inductor layer I- 8

9 Latest POL Hardware Circuit size is 20 x 18 x 5 mm This includes driver and room for a control chip Inductor is located on bottom side Devices are embedded inside ceramic active layer (they are not visible here) I- 9

10 Active layer: Fabrication Using 8/15/8 mil AlN Direct Bonded Copper as device carrier 1. Copper is etched to leave traces behind 2. Laser cutter makes holes for device dies, vias and snubber cap 3. Devices and cap wafer are epoxied in place 4. Interconnections are made with more DBC top & bottom I- 10

11 Comparing substrates This one uses PCB Tmax = 158 C Tavg = 96.8 C This one uses AlN DBC Tmax = 94.1 C Tavg = 91.0 C Stacked Power temps are 40% less than PCB version No heat sink is needed with Stacked Power at 25W I- 11

12 Electrical constraint Low inductance of this loop is important for high efficiency Its value must be as low as possible C dec Q2 Q1 L1 C1 RL Cdec value is ~ 22 uf Previous work I- 12

13 Effect of high loop inductance Both tests using discrete packaged devices: IRF IRF6691) Vsw (@1.3MHz) Vsw (@1.3MHz) From: Yu Meng IPS 2006 L_loop 1.8 nh ζ = ~ 0.06, Rac=~0.101ohm L_loop 1.23 nh ζ = ~0.25, Rac=~0.351ohm Does Stacked Power allow for a low value? I- 13

14 Another advantage Flip MOSFET pair S Cap dec Solder D Ceramic S D Bare dies and cap are shown in cross-sectional view We can get L much lower by flipping them relative to each other Loop inductance calculation using Maxwell 3D Lloop = 0.82nH with flip MOSFET pair I- 14

15 Stacked Power comparison Both use the same parts Integrated POL shows no loss of efficiency with PCB version We are currently working on an even better performing POL 3D POL 5V to 1.2V at 1.3MHz Stacked Power POL compared with PCB discrete version 92.50% 90.00% Efficiency (%) 87.50% 85.00% 82.50% 80.00% Stacked Pow er PCB 77.50% 75.00% Output Current (A) I- 15

16 Stacked Power advantages Substrate is 38x more heat conductive than PCB Devices run cooler by having very effective heat removal Increases effective surface area for convection to ambient Thermal management is integrated No heat sink is needed for full 15A output in natural convection! Integrates active devices and inductor layer Integration allows for stacked parts/layers in z-direction Circuit parasitics are reduced for less loss Higher switching frequency possible which reduces POL size Very high power density of 127 W/in 3 achieved This includes driver, integrated inductor and room for control chip I- 16

17 Future work for active layer Make the smallest package for highest power output Latest thermal camera shots show no need for a heat sink in natural convection at 20W output and up to 55 C ambient! With the right inductor and 200LFM airflow, we can do 20A output in a much smaller package than we currently have. Comparing single-layer DBC and 3-layer DBC converters What is the trade-off between thermal performance, packaging and cost? This technology can be scaled up High voltage applications High temperature applications I- 17

18 LTCC passives integration LTCC Low Temperature Co-fired Ceramics Typical sintering temperature ~ 900 ºC compared with HTCC (sinter temperature ºC) Starting material is in sheet form ~ um thickness Laminated to desired thickness before sintering Silver and its alloys can be used as conductor Conductors are typically in paste form Conductors are typically screen-printed on LTCC green tapes and co-fired after entire structure is built [5] [5] I- 18

19 Motivation: Strengths of ceramic technology over existing technology Temperature Capability Metal scheme Metal stability CTE (silicon) CTE (metal) CTE (substrate) Thermal cond. Elec. Cond. Of metal Ceramic 500 ºC Silver alloy Stable 4 ppm/k ppm/k 4 W/mK > 1.7e7 S/m PCB 135 ºC Copper Oxidizes at elevated temperature 4 ppm/k 17 ppm/k 17 ppm/k 0.3 W/mK 5.8e7 S/m Possibility of integrating LTCC passives with semiconductor bare die is good I- 19

20 LTCC planar inductor Discrete inductor 5 mm < 1 mm Profile of power inductor has been reduced to < 1mm LTCC inductor Plan view Cross-sectional view 0.9 mm 125 μm Alumina tile Magnetic core conductor 340 μm 1.9 mm I- 20

21 Thermal capability of LTCC inductor When inductor is shorted Thermocouple on top of LTCC inductor Inductor current waveform Inductor shorted out LTCC inductor is able to function at 190 ºC! LTCC ferrite has relatively high Curie temperature! I- 21

22 Inductance calculation VL [V] & IL [A] LTCC inductor I and fs=2mhz, Vin=5V, Vo=1.1V, I DC =5A V(avg) Inductor Current Δi/Δt V L time [us] Inductor voltage L = VL Δi Δt I- 22

23 LTCC planar inductor core Core thickness, g Conductor thickness, e Conductor width, w conductor I- 23

24 Non-Linear Inductance Property L [nh] Effective inductance vs. I out w =1mm inductor w =3.8mm inductor 23nH air-gapped inductor I out [A] IL [A] Inductor Vin=5V, IDC=0A No Load time [us] w=1mm inductor w=3.8mm inductor 23nH inductor Efficiency [%] Power stage efficiency vs. I out >30% >10% w=1mm inductor w=3.8mm inductor L2 23nH air-gapped inductor I out [A] IL [A] Inductor Vin=5V, IDC~12.5A w =1mm inductor Full Load w =3.8mm inductor 23nH inductor time [us] [1] M. H. F. Lim, J. D. van Wyk, and Z. Liang, Effect of geometry variation of LTCC distributed air-gap filter inductor on light load efficiency of DC-DC converters, Ind. Appl. Soc. Conf. 2006, 8-12 Oct 2006, Vol. 4, pp I- 24

25 Substrate Inductor with Integrated Shield No shield With shield Output capacitor Shield Gate driver Bootstrap diode Input capacitor Bottom switchinsulator Top switch Bootstrap capacitor Inductor substrate Power stage efficiency vs. I out Efficiency [%] shield no shield I out [A] V in I in Q2 Vsw Q1 I L + V L - L 25nH C I o R + V o - [2] Michele H. Lim, Y. Dong, J. D. van Wyk, F. C. Lee, K. D. T. Ngo, Shielded LTCC Inductor as Substrate for Power Converter, Power Electronics Specialists Conf., 2007, June I- 25

26 100 nh Inductor Design Specifications: L=100nH, I DC =16A, inductor footprint=28mm x 28mm thickness < 1.4mm Through hole Inductor electrodes 10mm apart 11.6mm Inductor electrodes 28mm 13.4mm 10mm 11mm 11mm 28mm I- 26

27 100nH Inductor Design L l = 4 w( I 8) ( DC 10 DC + + I For I DC = 16A, w=2.5mm, e=500um, g=0.433mm L l = 1.77 μh m For current flowing round a corner, Let L L corner = 0.5 = 2. 21nH sq / ) 1.37 mm 2 2 w + e w + e + 2g + + 4g μ 0 ln( 2 2 π 2 w + e w + e core conductor 2 + 2g( w + e) [3] mm 0.5 mm mm Cross sectional view [4] [3] M.H. Lim, Z. Liang, and J. D. van Wyk, Modeling of an LTCC Inductor Capable of Improving Converter Light-Load Efficiency, Appl. Power Electronics Conf. 2007, 25 Feb - 1 March [4] Prieto, M.J.; Pernia, A.M.; Lopera, J.M.; Martin, J.A.; Nuno, F., Design and analysis of thick-film integrated inductors for power converters, IEEE Trans. Ind. Appl., vol. 38, issue 2, March-April 2002 pp I- 27

28 100nH inductor design conductor length = 2 x ( ) = 51.5 mm L(51.5mm) = 91 nh L(4corners) = 8.8 nh L(total) = 99.8 nh Inductor electrodes I- 28

29 100nH inductor design R = = = Ω sq sheet t m / 7 σ l R(51.5mm ) = Rsheet = = 2. 42mΩ w 2.5 R( total ) = 2.42m μ = 2. 66mΩ R corner = 0.5*R sheet μω/ = 58.8 uω / Inductor electrodes [5] [5] M.H. Lim, Z. Liang, and J. D. van Wyk, Low profile integratable inductor fabricated based on LTCC technology for microprocessor power delivery applications, Appl. Power Electronics Conf. 2006, March 2006, pp I- 29

30 100nH Inductor with Integrated Shield Fabrication Inductor winding Inductor top layer Insulator with shield Inductor with shield I- 30

31 LTCC Planar Inductor Test Results I [A] Inductor current waveform time [us] Full load current = 16A Full load actual L = nh Full load designed L = 99.8 nh No load actual L = nh V [V] Inductor voltage waveform time [us] I- 31

32 LTCC Planar Inductor Test Results Inductor electrodes Efficiency 88% 87% 86% 85% 84% 83% 82% 81% 80% 79% 78% LTCC Discreet L=100nH Io (A) Vin=5V,Vo=1.2V,fs=1.3MHz, 1IRF6633+IRF6691 For Discrete L=100nH: DCR=0.17 mohm [6] 1.8% [6] J. Sun, IPS presentation, 12 Dec 2006 For LTCC: DCR=1.91 mohm I- 32

33 LTCC inductor testing LTCC 100nH inductor used with 1-DBC layer converter Only changes were 1. removing discrete inductor from board 2. Reflowed LTCC inductor on back side of board Top view Side view I- 33

34 Efficiency results Excellent light-load efficiency thanks to non-linear inductance Heavy load performance suffers from high DCR We are currently making different inductor versions with lower DCR 3D POL 5V to 1.2V at 1.3MHz 92.50% 90.00% 87.50% Efficiency (%) 85.00% 82.50% 80.00% discrete LTCC 77.50% 75.00% Output Current (A) I- 34

35 Thank you for your attention! Do you have any questions? I- 35