A new tool for next generation power semiconductors
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1 A new tool for next generation power semiconductors Cassandra Melvin / SEMICON China / Mach 16, 2018 Technology for tomorrow's solutions
2 Contents 1. HEV/EV market growth 2. Power module packaging 3. EmPower project 4. Results of experiments 5. Summary 2 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
3 HEV/EV market growth
4 Growth of automotive electronic systems Automotive electronics cost as % of total car cost Sources: Clemson University Vehicular Electronics Laboratory, Left; Statistica Automotive Report 2012, Right 4 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
5 Market growth for power modules in EV/HEV Sales $M USD 6,000 5,000 29% CAAGR ,000 3,000 2,000 EV/HEV 1, Electric/Hybrid bus Motors UPS Rail Wind EV/HEV PV Source: Yole Developpement 5 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
6 Requirements for power electronics "Developments for power packaging are needed because power electronics are facing many challenges, due to both environmental and technical requirements (Yole, 2015) High power density and temperature Power efficiency Costs CO2 reduction High reliability 6 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
7 Current power module packages Wafer Power module Component Die IGBT, MOSFET, DIODE PCB with component Hermes Project 7 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
8 Current power module packages Al wire bond Ribbon bond SBD IGBT DCB Heat sink C Limitations: High parasitic inductance of bond wires Lifetime limitation by bond wire reliability Requires height for vertical interconnection Single side cooling of the devices 8 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
9 New technology for embedding power modules Embedded package Miniaturization Price reduction High reliability Direct mounting on motor housing Wider switching range High power efficiency 9 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
10 New technology for embedding power modules Heat sink (IMS, 0.5mm) Thick Cu layer C Features: Thinned power components embedded Embedded power core (0.4mm) Heat sink (IMS, 0.5 mm) Embedded MOSFET Thick Cu layer C Double sided device cooling Shortest interconnection length for max electrical connection and heat dissipation Large area structured interconnection Embedded MOSFET chip <100µm Source Gate Full area back side interconnection Drain Challenges: Component flatness Well defined Cu termination on both sides 10 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
11 EmPower project
12 Consortium supply chain Wafer supply Wafer plating Wafer back end Die embedding Power module End user System development System simulation Development targets wafer plating: a) EQ and process for parallel double-sided Cu plating of power SC wafers b) Electrochemical Cu deposition on thinned (<100µm) wafers c) Automated solution to electrically contact both sides of a thinned wafer 12 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
13 Challenges for well defined Cu terminations Power die Taiko Standard 50 µm 1) Warpage, Bow 2) Handling of thin wafers, Tool automation 3) High Cu thickness 4) Different thickness on each side Challenges for all existing sequential plating tools Solution: new technology for simultaneous metallization on both sides of wafer 13 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
![EmPower targets for dual Cu termination Cu thickness [%] per side Requirements ± 5 [± 1] WIW NU [%] ± 10 Cu structure Cu resistivity [µohm.](/docs-images/77/75772189/images/14-0.jpg "cm] Internal stress [MPa] Polygonal Cu 2 < 50 Cu Embedded die 14 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON")
14 EmPower targets for dual Cu termination Cu thickness [%] per side Requirements ± 5 [± 1] WIW NU [%] ± 10 Cu structure Cu resistivity [µohm.cm] Internal stress [MPa] Polygonal Cu 2 < 50 Cu Embedded die 14 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
15 Results of experiments
16 Results for dual side Cu termination Cu thickness [%] per side Requirements ± 5 [± 1] Results Side A: Side B: WIW NU [%] ± 10 5 Cu structure Polygonal Polygonal Cu resistivity [µohm.cm] Internal stress [MPa] < µm Cu on both sides, unstructured front back 15µm Cu structured, front; 3µm Cu unstructured, back 16 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
17 Challenges for plating equipment Wafer handling Thick Cu Anode design & fluid management Cost efficiency Taiko wafer contacting and handling 600µm Grinding < 100µm Taiko Process Conventional Wafer holder for backside Cu plating (100% Cu area) with high Cu thickness (up to 50µm) > Plating of thick Cu warpage-free on thin Taiko wafer > Full backside plating of high Cu thickness up to 50 µm 17 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
18 Challenges for plating equipment Wafer handling Thick Cu Anode design & fluid management Cost efficiency Optimal electrolyte flow distribution with high and direct flow Adjustable current distribution by anode segmentation Insoluble, dimensional long-term stable anodes Segmented Anode Schematic diagram of fluid flow control of the plater module > Uniform and fast deposition of thick and pure Cu 18 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
19 Challenges for plating equipment Wafer handling Thick Cu Anode design & fluid management Cost efficiency Double sided plating (DSP) Sequential Plating 01. Taiko thinning 01. Front side PVD 02. Back side IGBT process 02. Front side photolithography 03. Back side PVD 03. Front side ECD Cu 04. Front side PVD 04. Front side photoresist stripping 05. Front side photolithography 05. Lega treatment 06. DSP ECD Cu 06. Seed layer etching 07. Front side photoresist stripping 07. Bonding 08. Lega treatment 08. Grinding without Taiko 09. Seed layer etching 09. Back side IGBT process 10. Back side PVD 11. Back side ECD Cu 12. De-bonding > Process efficiency > Cost reduction 19 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018 from 12 to 9 process steps 26% cost per wafer savings
20 Summary
21 Summary of technical benefits DSP 50 µm Cu Low internal stress, 10 MPa Cu resistivity, 2.74 µohm cm WIW Nonuniformity < 5% Plating different patterns / side Cu thickness 50 µm Zero warpage on Taiko wafers Fewer process steps 21 Atotech confidential A New Tool For Next Generation Power Semiconductors SEMICON China 2018
22 The future of power semiconductors Contact Cassandra Melvin Atotech Deutschland GmbH Erasmusstraße Berlin Germany + 49 (0) info@atotech.com Technology for tomorrow's solutions
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