ABSTRACTS Wednesday 20th of June Short courses

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1 After the three last successful events, Yole Développement & NCAP have decided to continue and strengthen the collaboration to organize the Advanced Packaging & System Integration Technology Symposium for the 4th time. The unique single-meeting event will take place in one of the most dynamic places in the semiconductor: Wuxi, China, from June 20 to 21, During 2 days, all packaging aspects including Panel Level, Fan Out, System in Package, Advanced Substrates, 3D Technology will be discussed. Focus on key applications such as 5G, Automotive, Artificial Intelligence and Memory will be at the heart of the conference. ABSTRACTS Wednesday 20th of June Short courses 9:00 AM 12:00 PM: Short Courses Session 9:00 9:30 Electronic Packaging Technology and Materials CP Wong, Regents Professor and the Charles Smithgall Institute Endowed Chair at the School of Materials Science and Engineering, Georgia Institute of Technology Polymers and nanocomposites are widely used in electronic and photonic packaging as adhesives, encapsulants, insulators, dielectrics, molding compounds and conducting elements for interconnects. These materials also play a critical role in the recent advances of low-cost, high performance novel No Flow Underfills, Reworkable Underfills for Ball Grid Array (BGA), Chip Scale Packaging (CSP), System in a Package (SIP), Direct Chip Attach (DCA), Flip-Chip (FC), Paper-thin IC and 3D Packaging, Conductive Adhesives (both ICA and ACA), Embedded Passives (high K polymer composites), nano particles and nanofunctional materials such as CNTs, graphenes. It is imperative that both material suppliers, formulators and their users have a thorough understanding of polymeric materials and the recent advances on nano materials and their importance in the advances of the electronic packaging and interconnect technologies. 9:30 10:30 HPC and Advanced Packaging Technology Development Yifan Guo, VP of Engineering, ASE Group In recent development of semiconductor technologies, it is becoming more and more clear that the AI, typically presented by the cloud computations, autonomous vehicles and neural networks, will be the next major area of applications. One of the key characteristics of the AI applications is that it demands for high speed and extensive computation power. However, since the Moore s Law is approaching its limit and the IC performance improvement by scaling will slow down eventually, using packaging technology to enhance the IC performance becomes urgent and important. In this presentation, the evolution of packaging technologies in high speed applications is introduces. Several advanced packaging platforms and their design and process challenges are presented. New and potential packaging solutions and development progress are discussed. June 20 21,

2 11:00 12:00 Accurate Package Characterization and Modeling for RFIC Design Fujiang Lin, Professor, University of Science & Technology of China Packages have great impacts on RFIC and high-speed IC performance for both bond-wire and package lead. They should be accurately characterized and modeled preferably in an equivalent circuit (EQC) model, so that they can be co-simulated for a reliable RFIC design. Although EM simulation is now widely used, it should be verified by practical measurement. This lecture will talk about experimental technique for accurate package modeling including full L and C matrix, as well as ground inductance based on VNA technique using RF probe station. Advanced EQC models are developed for RFIC design which have been proven for first-pass success in packaged IC testing. Wednesday 20th of June Symposium 1:45 PM 2:30 PM: KEYNOTE 1:45 2:30 KEYNOTE: Impact of the Industry Trends on Advanced Packaging Jean-Christophe Eloy, President & CEO, Yole Développement Multiple evolutions of the industry is impacting the technology developments and the markets of advanced packaging. The mega trends related to the implementation of 5G, the emergence or artificial intelligence in every part of our life, the revolutions of transportation electrification and autonomous driving, the every growing data center scale, the potential disruption of mixed and augmented reality all are based on the evolution of advanced packaging to its limits, in term of SiP integration, advanced substrates, wafer level integration The presentation will highlight the links between these trends and the potential impact at the technology and market level for advanced packaging. 2:30 PM 3:20 PM: Session #1 Advanced Power Packaging 2:30 2:55 MOSFET Embedding in PCB Sky Ran, Key Account Manager, Schweizer Electronic (Suzhou) Miniaturization of Power Electronic modules requires the minimization of losses and an optimized power dissipation. With the p² Pack technology it is possible to build ultra-thin modules which have less losses and improved power (heat?) dissipation characteristics by using embedding technologies and processes of the Printed Circuit Board industry. Due to the fact that the p² Pack is really flat, it is possible to go one step beyond and embed such a flat component into a logic control board. The Smart p² Pack construction is open to the bottom side of the PCB. A heat sink can easily be installed to the bottom side, either using a Thermal Interface Material or using sintering technologies to further reduce the thermal resistance from junction to ambient. 2:55 3:20 MultiPlate: a New Tool for Next Generation Power Semiconductors Bobby Chen, Business Manager of Semiconductor & New Field, Atotech Taiwan and China As electro-mobility gains momentum, there is increasing pressure on the power semiconductor supply chain to enhance existing technologies. To satisfy the requirements for next generation power semiconductors in HEV/EV and e-mobility products, power packages must provide higher June 20 21,

3 reliability and power density, better energy efficiency and management, and reduced package size. A new electroplating system addresses these requirements. The new system enables a more efficient and cost effective method for embedding power chips with simultaneous metal deposition on both wafer sides. Additional system features provide technical benefits for embedded technologies and enable further miniaturization of power semiconductor packages to comply with future product requirements. Power management is a primary concern particularly for thick Cu heat sink requirements and the new tool delivers the benefit of thick Cu deposition up to 50µm for optimized dissipation. Additional tool benefits include: 1) handling and processing of Taiko wafers with 50µm thickness, 2) significant warpage compensation using dual side metallization 3) individual control of plating parameters for each wafer side for plating on different design layouts and Cu thickness, 4) plating of up to 50µm Cu on wafer scale, and 5) improved manufacturing efficiency with 25 percent fewer process steps, thereby leading to 6) a cost per wafer reduction of 25 percent. This paper will discuss how the new system s features enable these benefits and will present key process results as demonstrated in the EmPower consortium. 3:45 PM 5:25 PM: Session #2 Panel Level Packaging 3:45 4:10 Is Industry Ready for Fan-Out Panel Level Packaging (FOPLP)? Santosh Kumar, Director Packaging, Assembly & Substrates, Yole Développement Currently Fan-out Panel Level Packaging (FOPLP) is attracting lot of interest in industry market because of its potential cost benefit and higher manufacturing efficiency. Panel-level manufacturing has the potential to leverage the knowledge and infrastructure of wafer-level packaging (WLP) and the PCB/flat-panel display/photovoltaic industries and this attracts players with many different business models, including outsourced semiconductor assembly and test (OSAT), integrated device manufacturers (IDMs), foundries, substrate manufacturers and FPD players. The supply chain is getting ready with many equipment and materials suppliers developed their product to support FOPLP processing. After years of development and qualification, FOPLP is finally entering mass production in This presentation will focus on the market and technology trends of FOPLP, including, supply chain and equipment/material readiness. 4:10 4:35 From Round to Square, cost effective sputter solutions for High Volume Manufacturing (HVM) Andreas Erhart, Senior Manager, Product Marketing Advanced Packaging, Evatec FOWLP has been in high volume production since more than a decade with different technologies like the Infineon ewlb or the RCP process from Freescale. Until now, only the introduction of TSMC s Integrated Fan-Out (InFO) technology around 2015 followed by scale up of manufacturing a year later created a new hype around FOWLP; still not in HVM but creating enormous attention within the packaging market. One feature all of these various Fan Out technologies share is the creation of additional area for more IO s compared to WLP the Fan Out area and a goal to deliver lower costs, enhanced process control and performance - mainly temperature control, stable contact resistance and of course satisfactory yield in production in order to achieve the cost target. Existing cluster type PVD tools in the market are able to support one or the other of the requirements for FOWLP but the indexer tool concept has an advantage in being able to support all requirements - from high throughput resulting in June 20 21,

4 lower costs per wafer/die, low contact resistance, temperature control and acceptable yield. As we anticipating the introduction of the next potential raising star in advanced packaging, FOPLP and all its various panel formats and challenges, new concepts and innovative solutions have to be evaluated. Different technologies compared to the well-established WLP sputter tools may also be required to achieve the target cost benefit whilst maintaining the ever more demanding process performance requirements already discussed for FOWLP. The presentation will explain the key differentiators to standard PVD cluster type tools, describe how the key requirements are fulfilled and supported with both - the Indexer tool in FOWLP and the Panel Level tool in FOPLP on substrates up to 620x620mm. 4:35 5:00 Electroplating in Advanced Packaging: Effortless Scaling from Wafer to Panels with High Speed and Excellent Uniformity Herbert Oetzlinger, CEO, Semsysco Wafer level packaging (WLP) has become increasingly important to the functionality of advanced mobile and automotive solutions, but is often more expensive that traditional packaging. A new trend, panel level packaging (PLP), will allow much lower prices. Scaling electroplating processes for panel applications is one of the few remaining roadblocks on the path to large scale adaption of PLP. With a unique high speed plating chamber, fast and uniform plating can be easily scaled from face down wafer processing to vertical panel processing, revolutionizing the packaging industry. In the patented chamber setup, the electrolyte is ejected uniformly over an area matching the substrate, be it wafer or panel, and effectively drained equally close. The constant refreshing of the electrolyte enables plating rates up to 8 times higher with otherwise identical conditions, as well as renormalizing the electric field over the entire area to be plated. As the so called high speed plate can be manufactured for any size, it allows the easy conversion of the plating process from WLP to PLP and will help drive down packaging costs for future applications. 5:00 5:25 The Convergent Future: Industries-wide Disruption through Flexible Hybrid Electronics Chong Chan Pin, Senior Vice President, EA/APMR and Wedge Bonders Business Lines, Kulicke & Soffa Semiconductor has traditionally been fragmented into specialized Front-End, Back-End, SMT (Surface Mount Technology) industry for many decades. With the ever increasing complexity in electronics, these industries are undergoing a paradigm shift. Convergence activity continue to gather momentum and existing boundaries are continually being re-defined. The industry now demands new innovation and methodology to provide a more comprehensive packaging solution. Delivering a solution which can span the breath of the new boundary has adopted the label of HYBRID. This presentation explores how Flexible Hybrid tool can support OSATS, EMS and OEMs to deliver a highly competitive product that can switch between applications to diverse their product portfolio. Experiences in diversifying new applications for EMS to support them in adapting business models to pursue new markets has helped companies to increase product breath and at the same time increasing depth. Presentation would be focus on examples in Wafer SiP / FoWLP / Embedded with hybrid technology tool. June 20 21,

5 Thursday 21 st of June Symposium 8:15 AM 9:00 AM: KEYNOTE 8:15 9:00 KEYNOTE: The Industrialization Road of Innovative Wafer-level Fan-Out Technology: esifo Dr. Daquan Yu, Vice President, Huatian Technology (Kunshan) Electronic Wafer-level Fan-Out (WL-FO) is a key technology, which not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore s Law. The embedded silicon fan-out (esifo ) technology based on both 8/12 in wafer process, which was developed by Huatian Technology has proprietary intellectual property rights. The esifo technology has combination of accuracy silicon etching, wafer re-construction and high density RDLs. The advantages include small form factor, low cost, simple process, small warpage, high yield and it is a platform technology for multi-die SiP and 3D integration. The esifo technology is regarded a significant achievement on leading edge advanced packaging field. 9:00 AM 11:20 AM: Session #3 Fan-Out Wafer Level Packaging 9:00 9:25 Fan-out Wafer Processing in the High Density Packaging Era David Butler, EVP General Manager, SPTS Technologies In an age where we are witnessing the emergence of high power computing requirements for a variety of applications, Fan-Out Wafer Level Packaging (FOWLP) technology is an increasingly popular solution for obtaining a high level of device integration with a greater number of I/O contacts, in a small package. First introduced for small die applications such as power management and RF transceivers, it now serves as a platform for mobile application processors. Today, makers of high density devices for AI, 5G and networking are pursuing the benefits of FOWLP. There are many different FOWLP schemes from the leading device manufacturers and packaging houses, all aimed at achieving better device performance in a smaller/thinner package, at a lower cost. While the different schemes vary in their detail, in simple terms, they all involve embedding die in a cost-effective epoxy mold substrate with metal redistribution layers (RDL) forming the interconnects between die and bump connections. Prior to UBM/RDL metallization by physical vapor deposition (PVD), the mold substrate needs to be degassed and native oxide needs to be removed from the metal contacts, within the relatively low thermal budget imposed by the epoxy mold. Due to a lower ion energy, Inductively Couple Plasma (ICP) etch processing induces less heating and lower levels of contamination from any organics on the substrate during the removal of the oxide, than alternative diode plasma etching solutions. Data will be presented showing long time between chamber cleans, and how a novel in-situ pasting technique gives low & stable contact resistance. A new pre-clean etch technology will be discussed giving improved removal of contaminating species, resulting in ~25% lower Rc. June 20 21,

6 9:25 9:50 10 years of Thermal Debonding and Warpage Adjust Klemens Reitinger, CEO, ERS electronic To create a new, reconstituted wafer/panel is the essential step in what we today know as coreless FOWLP. Typically, this wafer/panel is made by overmolding KGD arrays on a temporary carrier. After removing this carrier, the reconstituted wafer/panel is ready for the next process step. Since the invention of ewlb (embedded wafer level ball grid array) by Infineon, an advantageous and cost-effective way to do so is using a thermal release tape. At a certain temperature, one side of the tape is losing the adhesive force and can be easily separated from the reconstituted wafer/panel. Because this is a thermal process applied on a wafer/panel composed of parts made of different materials, warpage is a big issue with this technique. This presentation will describe the process steps of thermal debonding and warpage adjust based more than 10 years experience in Thermal Debonding. It will describe different methods of thermal debonding with their advantages and disadvantages, and show the context of the debonding method with important downstream topics like warpage, die shift and tape residues. Different techniques for fully automatic detaping and related issues, and the importance of warpage adjust and the unique method of ERS are described. 9:50 10:15 Defect Inspection for Shrinking RDL Line/Space in High-Density Fan-Out Wafer Level Packaging Stephen Hiebert, Senior Director of Marketing, KLA-Tencor The semiconductor industry is in a unique era where there are multiple drivers contributing to the increasing demand for silicon chips. The main drivers include mobile, AI / machine learning, autonomous driving, IoT and AR / VR applications. The industry needs Moore s Law to continue in order to meet the evolving requirements for high performance, low power and low cost. With the rise in cost for a front end fab to move from one technology node to the next, the industry is increasingly relying on new developments in advanced wafer level packaging (awlp) to continue achieving high performance and low power milestones. In the last two years, High Density Fan-Out (HDFO) packaging has seen increased adoption for mobile and networking chips. With each shrinking RDL node (10µm -> 5µm -> 2µm -> 1µm), the need for process control at this step is higher, while the challenge of inspecting these HDFO wafers has also increased significantly. Besides the expected need for high resolution and the reduction of metal grain nuisance, new challenges like the handling of warped substrates and additional inspection noise from die reconstitution have also emerged. This paper shares details of how our KLA-Tencor pattern inspection system overcomes these challenges, and how we have worked with key customers to improve their yield. 10:45 11:10 The Status of FOWLP Development in NCAP, China Daping Yao, Ph.D., Technical Director, NCAP China 1. A brief introduction of NCAP, China 2. Introduction to the development of fan-out technology 2.1 Market analysis 22 Major players in FOWLP 2.3 Patent analysis 2.4 Overview of process technology June 20 21,

7 2.5 Challenge and working solutions 2.6 Status of FOWLP in Chinese OSATs 3. Status of Fan-out packaging in NCAP, China 3.1 Status of wafer level fan-out packaging 3.2 A brief introduction of Casmeit, a dedicated FOWLP factory 3.3 Status of panel level fan-out packaging 4. Brief update on LPFO consortium 5. Summary 11:10 11:20 The Investment environment and Semiconductor Packaging and Testing Industry of Xuzhou Economic and Technological Development Zone Dai Lei, Member of the CPC Work Committee and Deputy Director of the Management Committee, Xuzhou Economic and Technological Development Zone NA 11:20 AM 12:35 PM: Session #4 High End 11:20 11:45 Advanced Die Attach Technologies Andreas Schopper, Vice President Flip Chip, Besi Switzerland Due to the tremendous performance, costs and power needs for future Internet of Anything applications, 3D Advanced Packaging and Heterogeneous Integration becomes one of the key technologies to feed future demand of connected and collecting (big data) devices and systems. Heterogeneous Integration is driving our Die Attach technology and equipment roadmaps at fast pace with different Advanced Packaging solutions like Flip Chip, Fan-out and 2.5/3D packages dictating Die Attach R&D focus areas. On one side machines accuracy levels are pushed to lower then 1 micron levels for future Hybrid applications with ultra-low pitches. Additionally, for ultra-accuracy systems a full clean machine concept to Class 1 is vital to control particle contamination. Cost of ownership factors with UPH levels >10k are key capabilities for Flip Chip and Wafer Level packages with larger bond ranges from wafer to panel level are demanded. Also, highly flexible and smart machine concepts with full yield control are supplement requirements for developer and system designers. Finally, with component dies and substrates getting thinner ultra-thin die handling solutions and highly complex bond process control systems for Thermo-compression and Direct bonding systems are necessary. Developing and working with unique and scalable building blocks and concepts based on common machine bases and platforms are key to leverage the vast and wide range of new key capabilities and meet time to market requirements. Besi has strengthened this approach to offer best in class advanced die attach equipment. June 20 21,

8 11:45 12:10 Equipment and Process Challenges for the Advanced Packaging Landscape Laura Mauer, Chief Technical Officer, Veeco The advanced packaging market spans multiple applications and approaches there is no single roadmap for advanced packaging, but a landscape. The growth drivers for advanced packaging include Big Data, smartphones, IoT, automotive and memory. Due to challenges with scaling at the device level, there is a critical need for heterogeneous integration at the package level. There are multiple approaches to packaging for a wide variety of devices for different applications. These approaches include 3D, TSV, and numerous 2.5D schemes using FOWLP concepts. In addition, the form factor (wafer vs. panel) and size have not been standardized. The various approaches that exist means tool suppliers must be able to quickly adapt and customize their technology to different wafer sizes and formats, integration sequences, materials, chemistries and process conditions. However, providing process flexibility while minimizing cost of ownership and tool footprint is challenging. This presentation will describe several different approaches to advanced packaging with examples, and explore the challenges and possible solutions associated with each. 12:10 12:35 High End Performance Application key Driver for Advanced Packaging Thibault Buisson, General Manager, Yole Développement The semiconductor industry has been facing a very high demand, driven by the adoption of more and more electronics components in end products was a tremendous year for the semiconductor industry and expectations are high for the next coming years. In this context, advanced packaging technology will become more and more preponderant, considering scaling and cost reduction will not be possible just by continuing to follow Moore s law. Devices below 10nm nodes are rising substantially and advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions. To answer market demands, the industry seeks further performance and functionality boosts in integration. Packages are now requested to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. They become enablers for new designs, new performances and new applications, this is what the industry is currently looking for. Artificial Intelligence (AI) will be more present in the future in consumers, automotive, medical and also industrial applications. 3D integration fits well AI and High-Performance Computing (HPC) products requirements, as it offers low-power consumption with capacity to transfer large quantity of data at low latency. The change that occurs in semiconductor industry is to be considered a new opportunity for silicon makers as emerging needs such as deep learning brought out more challenges to the IC but also to the packaging industry. Key players are now launching memory in specific package types and very high end products integrating advanced logics dies. The road is open for alternatives solutions and everyone would like to penetrate this exciting market. Intel has developed his own package solution so called Embedded Interconnect Bridge (EMIB) whereas others are developing high density fan out solutions and TSV less technology against current System In package solutions. This presentation will explain the challenges along the supply chain and describe the market dynamics. It will also explain the different solutions and challenges that the industry will have to face. Latest products launched in the market will also be presented. June 20 21,

9 1:45 PM 3:25 PM: Session #5 Equipment for Wafer Level Packaging 1:45 2:10 Plasma for Wafer-On-Frame Treatment Jack Zhao, Ph.D., Chief Scientist/Applications Director, Nordson March The use of thin silicon wafers is an enabling technology for 3D integration in the semiconductor industry and thin wafer handling is an important issue in 3D integration technologies. Temporary wafer bonding and debonding has emerged as a standard processes necessary for most 3D integration applications, such as Wafer Thinning, TSV Fabrication, Microbumping, and Backside RDL Formation. After wafer thinning and other WLP processes, the wafer debonding process is required for next step process. In most case, the thinned wafer is placed on the frame after debonding since the thin silicon wafer is fragile to handle and needs some support for the next step process. However, some adhesive residuals are left on the wafer surface after wafer debonding which are required to be removed by wet or dry cleaning process. Therefore, plasma becomes one of the solutions for adhesive residual removal of wafer-on-frame. Different from regular plasma for wafer only processing, the challenge of this application is the wafer on frame during plasma process. In this presentation, the design of plasma chamber is mentioned and wafer-on-frame plasma process is discussed. The result indicates that the adhesive residuals on the debonded wafer-on-frame can be plasma etched using MesoSPHERE from Nordson March, and the tape s mechanical property has no significant change except partial loss of stickiness on the exposed area. Furthermore, the tape used for holding wafer on frame did affect the etch rate and its distribution, especially on the edge, and therefore, affects the WIW uniformity. However, the within wafer etch uniformity can be controlled within 10% ((Max-Min)/2xAve) by proper plasma chamber design and optimized plasma recipe. 2:10 2:35 The Advancement of Carrier-Assisted Substrate Handling Technology for Advanced Packaging Dongshun Bai, Ph.D., Deputy Business Development Director, Brewer Science The current drivers for the semiconductor industry are consumer electronics, mobile devices, cloud computing, automotive electronics, and 5G technology. The demand for faster, smaller, lower-cost devices with reduced power consumption is now greater than ever. While the semiconductor industry continues to make progress in scaling integrated circuits, it is also turning to advanced packaging technologies to increase performance and integration while lowering costs. Carrier-assisted substrate handling, sometimes referred to as temporary bonding, was introduced to the industry about 15 years ago. Brewer Science was one of the first companies to recognize temporary wafer bonding as an enabling technology for ultrathin wafer handling. In the early stages, temporary bonding was viewed more as a means for wafer thinning and enabling backside wafer processing at high temperatures and high vacuum levels. With the introduction of fan-out and other advanced packaging technologies, the need to handle new types of packaging substrates such as reconstituted wafers and panels that easily deform under thermal stress has grown rapidly, and as a result, carrier-assisted substrate handling is now viewed as a critical mainstream processing technology. June 20 21,

10 2:35 3:00 Advanced Wafer Bonding Technologies Enabling Smart Connected Devices Martin Eibelhuber, Deputy Head of Business Development, EV Group Smart connected devices are gaining importance, where the focus is shifting from data sharing and consumption of video content, towards real time sharing of data as well as storage in the cloud. Many of the requirements are joined within the scope of 5G transmission standard. Many different device architectures have to be aligned in order to cope with the standard. Essentially, wafer bonding has a central aspect in order to enable these architectures. 5G will need low data connection devices, where 3D integration using W2W bonding or integration of individual chips using advanced packaging process flow such as fan out wafer level packaging. In this presentation we will concentrate on two different bonding processes, namely W2W fusion bonding and laser assisted debonding. The combination of both processes can be facilitated for die to wafer bonding. For collective bonding, individual dies are populated and tacked either on an interposer or a so-called handling carrier, depending on the bonding technology applied. In case of tacking die face-down on an interposer or other active silicon die, bonding is usually being done by thermal bonding. Here, heating and cooling of the substrates are only done once, considerably reducing process cost and thermal budget of the underlying substrate. The second case is tacking the dies face up on a carrier substrate. This reconstructed dies on a carrier can now be processes again on wafer scale, this means preprocessing steps such as direct bonding can be done before bonding the wafers using fusion or hybrid bonding. 3:00 3:25 Laser Based Direct Exposure Tool Status in Advanced Semiconductor Packaging Olivier Vatel, Chief Technology Officer, SCREEN In the presentation, we will introduce the advantage of direct imaging tool and discuss technical challenges with respect to advanced semiconductor packaging area. Laser based direct write exposure tool for advanced semiconductor packaging has been developed and introduced into the market. The technology used in this equipment has unique features compared to existing high-pressure mercury lamp based exposure tools. The tool does not require any masks or reticles thanks to the state-of-the-art light valve called Grating Light Valve (GLV) along with high power laser unit producing wavelength of 355nm. Minimum resolution that the tool is able to draw is 2um lines/spaces with overlay accuracy of equal to or less than 1um at average plus 3sigma, that satisfies most advanced packaging requirement as of today. The tool has also unique function of so called die-by-die alignment. This enables fine alignment to every single die on the substrates. Since substrates used in advanced packaging are relatively flexible so that actual location of dies are moved and rotated on substrates. June 20 21,

11 4:10 PM 5:00 PM: Session #6 Advanced Packaging Materials 4:10 4:35 Introduction of Dipsol TS -3500(SnAg) Chemical for Bump Application Atsushi Sakamoto, Manager, Dipsol Chemical Dipsol TS-3500(SnAg) chemical has been developed to meet the customer needs for the expected growth of semiconductor bump application. This presentation will take you through evaluation results of Cu Pillar and efficient performance at high current along with introduction of Dipsol. We hope Dipsol s technology will help in achieving customer satisfaction for the increasing bump application. 4:35 5:00 TBA Minghua Luo, General Manager, Dongguang Darbond YizTech Material In response to the advent of 5G era, the high density packaging and high thermal dissipation requirement have become the mainstream. However, in consider the era of low profit margin industry competition is coming, how to research and develop high CP product will be the main work to meet the needs of the times. In this speech, we start from the requirements of high reliability adhesive and meet the needs of high thermal conductivity products. Describe the current direction and future development of Darbond YizTech products. Looking forward to providing people who is in the industry as a reference. June 20 21,