Lithography Session. EUV Lithography optics current status and outlook. F. Roozeboom Professor TU Eindhoven & TNO-Holst Centre, Eindhoven, Netherlands

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1 Lithography Session F. Roozeboom Professor TU Eindhoven & TNO-Holst Centre, Eindhoven, Netherlands Fred Roozeboom is a Professor at Eindhoven University of Technology, The Netherlands and Senior Technical Advisor at TNO Holst Centre in Eindhoven, The Netherlands After his MSc from Utrecht University and PhD at Twente University in The Netherlands, he continued his career in catalysis with ExxonMobil in Baton Rouge, USA ( ). In 1983, he joined Philips Research (since 2006: NXP) in Eindhoven, The Netherlands, to work on thin film technology for III V and Si semiconductors and for soft magnetic materials. From he led a team on 3D passive Si integration. For this work he received the Bronze Award for NXP Invention of the Year 2007 and became NXP Research Fellow. In 2007 he became part time professor at TU Eindhoven. In 2009 he joined a team at TNO Eindhoven specializing in spatial ALD and ALE. In 2014 he became Fellow of the Electrochemical Society. Fred is co /author of 200+ publications (h index: 33), 5 book chapters, 35 granted US patents, and co /editor of 40 conference proceedings on semiconductor processing. Fred has been or is active in organizing committees of several conferences (Materials Research Society, Electrochemical Society) and is a member of the SEMI Europe Semiconductor Technology Programs Committee. Topics of interest: ultrathin film technology, plasma processing, spatial ALD, reactive ion etching, 3D passive and heterogeneous integration, RTP, microsystem technology, Li ion micro batteries, sensors, displays and EUV optics lifetime. EUV Lithography optics current status and outlook

2 D. Jürgens Program Systems Engineer Carl Zeiss SMT GmbH, ZEISS Semiconductor Manufacturing Optics, Oberkochen, Germany The year 2018 is generally perceived as year of breakthrough for EUV lithography. The introduction into HVM is currently being executed by multiple chip manufacturers and thus secures the continuation of Moore's Law far into the next decade. Furthermore, the development of High NA EUV lithography as the next generation lithography technology is well underway. This presentation provides an overview of the major performance improvements of EUV lithography optics achieved to until today and how High NA EUV enables unprecedented resolution at high productivity. Dr. Dirk Juergens studied Physics and Applied Optics at the University of Stuttgart, Rose Hulman Institute of Technology, IN, USA, and University of Konstanz and received his doctorate degree in He joined ZEISS in 2004 as a scientist and worked on several positions in R&D and in systems engineering. Since 2018 he is Program Systems Engineers EUV in Carl Zeiss SMT GmbH.

3 Full wafer scale NanoImprint and Mask Less Lithography status and synergies for advanced manufacturing and pre prototyping at LETI S. Landis Group Leader for Massively Parallel Electron Beam Lithography & Lithography Lab Deputy Manager CEA-LETI, Grenoble, France In the lithography landscape, extreme UV (EUV) lithography technology is now implemented in manufacturing lines. Meanwhile, 193nm immersion lithography, with multiple patterning strategies, is still widely supporting the industry requirements for advanced node develop ments, despite the tremendous effort required for process controls. Although these two options are suitable for high volume manufacturing, more affordable technologies are still needed for R&D evaluations, pre prototyping and small scale productions. In such landscape, lithography alternatives maintain promise because they may present competitive compromises for the industry. Massively parallel electron beam and nano imprint lithography techniques remain highly attractive, as they can provide noteworthy cost of ownership benefits. In addition, directed selfassembly (DSA) lithog raphy shows promising resolution capabilities and appears to be an option to reduce multi patterning strategies, and therefore the associated mask set budgets. Even if large amount of efforts are dedicated to overcome the lithography side issues of these new patterning solutions, they introduce also new challenges and opportunities for the integration schemes. Through three collaborative R&D programs, IDEAL for Directed Self Assembly Lithography, IMAGINE for Massively Parallel Electron Beam Lithography and INSPIRE for NanoImprint Lithography, CEA Leti is currently assessing and boosting the development of these alternative technologies through strategic partnerships and innovative mix of them. In this paper, we will present how the development of the Massively Parallel Electron Beam Lithography may contribute to strengthen the supply chain of the NanoImprint Lithography through master manufacturing capabilities. We will review both Massively Parallel Electron Beam and NanoImprint Lithography technology status at CEA LETI and then show some realizations. Stefan LANDIS, Senior Scientist, received his Master s Degree in Engineering in Physics and Solid State Physics, from the INPG Grenoble Engineering School and his Master of Science (MSc) in Quantum & Statistical Physics from Grenoble University. After a PhD thesis in patterned magnetic media for ultra high density recording, he joined in 2001 the Lithography Laboratory of CEA LETI to develop high resolution Ebeam lithography processes for CMOS devices. Then he has been in charge of the NanoImprint lithography activity for 14 years and recently managed the Multi Electron Beam Lithography Project at LETI for the development and qualification of the Mapper Lithography solution. He is now working on business development for patterning activities and services available at LETI. Author or co author of more than 70 papers and 30 patents, Stefan Landis has edited two books Nanolithography and Lithography (ISTE Wiley, 2011) and contributed to Plasma Etching for CMOS Device Realization book (ISTE Press Elsevier, 2017).

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5 Front to Back Alignment and Metrology Performance for Advanced Packaging G. Kenyon Senior Applications Engineer Ultratech, San Jose, United States Foundry customers and makers of leading edge devices have established TSV for next generation 3D and 2.5G packaging. Scaling the diameter of TSV s is a major driver for improving system performance and cost but requires tighter back to front overlay. The transmission of IR wavelengths through silicon is utilised for embedded feature alignment and subsequent metrology. IR alignment can also be used for die to wafer, wafer to wafer bonding and photonics applications that are gaining in traction. Via Last applications enable distinct advantages for process integration, minimising the impact on BEOL processing and removing the requirement for TSV reveal processing. The Via Last TSV process introduces a requirement for lithography alignment, typically through thinned silicon to embedded targets. Performance enhancements can be realized by scaling TSV s and landing pads, creating a critical parameter for overlay. In contrast, photonics devices require front alignment through full thickness silicon to marks on the back surface to a high degree of tolerance. The lithography system used in this investigation has a top IR alignment package with wavelengths that support back to front side alignment and metrology applications through full thickness 300mm silicon wafers. This paper details system methodologies used for both alignment and overlay metrology including routines to diagnose and compensate for measurement error due to focus and for Tool Induced Shift (TIS), critical for determination of system measurement error. We also discuss alternative use cases borne from the development including die to wafer misalignment. The in line optical registration data was then correlated to detailed electrical measurements performed on the same wafers at the end of the process to provide independent assessment of stepper self metrology accuracy. Long term experimental overlay data was collected to determine robustness and repeatability of experimental wafer lots over a two month period. Gareth is a Senior Applications Engineer based in Scotland, supporting customers worldwide. He has been employed with Ultratech for 26 years with an active involvement in the semiconductor industry for some 35 years, observing plenty of changes in that time! He has authored numerous publications on lithography & process technology. A graduate of Glasgow University, Gareth achieved an MBA with merit. When spare time permits, he is a keen golfer with a passion for Highland pursuits such as hiking and whisky.

6 Direct Imaging Solutions for Advanced Fan Out Wafer Level and Panel Level Packaging M. Goeke Manager Product Engineering SCREEN SPE Germany, Product Engineering, Ismaning, Germany In recent years, the increasing use of smartphones and other mobile devices has created a demand for even higher integration, speed and miniaturization of devices. As scaling according to Moore s Law is slowing down, the industry is focusing to boost device performance by advancing in 3D integration and packaging. This trend has motivated SCREEN to develop an entire line up of direct imaging systems for both application spaces Wafer Level and Panel Level Packaging. This talk will outline the specific challenges an exposure tool has to cope with in the packaging arena. A unique method of image creation by using a proprietary spatial light modulator will be presented as well as image correction functions, that automatically adjust exposure data to prevent alignment errors. This feature resolves the previously challenging issue of positional deviation when rearranging the individual dies for fanout processing. Mark Goeke received his Master of Science in Photo Engineering from the University of Applied Science, Cologne in After holding various positions in lithography engineering he started working with Dainippon Screen Mfg.Co. (now Screen SPE, Germany) in Here he moved to hold the position of the Europen Product Engineering Manager, responsible for engineering, technology and product marketing for Screen s product lines of lithography and single wafer processor equipment.