450mm silicon wafers specification challenges. Mike Goldstein Intel Corp.

Transcription

1 450mm silicon wafers specification challenges Mike Goldstein Intel Corp.

2 Outline Background 450mm transition program 450mm silicon evolution Mechanical grade wafers (spec case study) Developmental (test) wafers Product (prime) wafers Challenges ahead Objective Short review the 450mm program Discuss 450mm silicon wafer spec development Asses the wafers current status and expected future challenges

3 450mm wafers driving force There factors are driving the 450mm diameter wafers program: cost, fab capacity and environmental footprint From it s beginning cost is a major factor affecting the industry. The transistor size shrinks and the density increases driving the cost reduction predicted by Moore Law, however increased device area, more complex designs and new materials are increasing the wafer cost for every new generation. To keep on the Moore Law curve a wafer size scaling is required every 4-5 generations. The industry is currently engaged in two other projects designed to reduce cost by increasing the wafer utilized area: elimination the wafer notch and decrease of the edge exclusion zone

4 450mm wafer cost vs. 300mm S. Jones, IC Knowledge: A Simulation Study of 450mm Wafer Fabrication Costs, ISMI manufacturing week (2010) ISMI productivity gap analysis ISMI Industry Briefing, SEMICON West (2007) Past Future [ca 2010] D. Fandel, Strategic Semiconductor Scenario Workshop, Austin (2010) D. Fandel, ISMI 450mm Industry Driver Analysis (2011)

5 Past wafer size conversions 150mm and 200mm conversions A single company led the conversion and funded the new wafer size, the pilot line equipment and all the improvements required. It was very expensive and stretched the company resources. 300mm wafer size conversion A new wafer conversion model was proposed - collaboration. I300I and J300/Selete coordinated the generation of standards and performed equipment evaluation for member companies. Detailed joint guidelines was provided to the equipment community. Automation become an intrinsic element of 300mm equipment development and not a custom requirement. The conversion stretched for a long time, suffered from several false starts and global economy major events (Asian flu, dot.com bubble burst and 9/11). It occurred only when all the equipment reached the necessary quality level (beta tool or better). Suppliers got frustrated holding the R&D bag while the ROI was much longer than they planned.

6 450mm wafer transition The 450 mm wafer transition started as a industry collaboration by ISMI and is currently coordinated by G450C. The program faced a divided industry, with many major suppliers, especially equipment manufacturers strongly opposed to the transition. From the start the program worked to apply 300mm lessons learned: Industry collaboration and coordination are crucial Early engagement of equipment and materials manufacturers is required. Beta tools level or better is essential for the conversion. Consensus on fab architecture and operation needs to be established from the beginning. Develop standards and tool metrics early. The silicon and PIC standards committees started engagement in 450mm activities. For silicon the 450mm International Task Force was created to achieve industry consensus on 450mm wafers critical requirements.

7 450mm silicon program objective Create a reliable 450mm silicon wafer supply line enable to support future generations needs. Focused on: Availability Quality Cost Generate 450mm silicon specifications. The standards creation is a significant precompetitive activity required to enable industry alignment for a smooth and efficient transition. Support the industry alliance 450mm program.

8 450mm Wafer Milestones Three wafer types have been developed to support the 450 transition in the most efficient way: Type Application Key Parameters SPEC Mechanical Handling Wafer Robotics and Carrier Testing Diameter, Thickness, Edge Profile, Mechanical Integrity M74 Developmental (test) Wafer Process and Metrology Equipment R&D Global Flatness, Metals, LLS, Particles, COPs, Surface Roughness M76 Product (prime) Wafer HVM Particles, Defects, Electrical, Chemical, LLS, Flatness, NT, ERO. M1-0812

9 Mechanical handling wafers One of the first challenges was the specification of wafer thickness. There is no rational in the historical trends Lessons learned from past wafer size transitions showed that once determined wafer thickness is difficult to change. We started scaling evaluation based on simulations Gravity Sag vs. Wafer Thickness Stress vs. Wafer Thickness Process induce warp Later ISMI ITB (Interoperability Test Bed) team measured 450mm wafers thickness impact on gravitational sag and wafer shape in different wafer handling configurations. The data showed a good correlation between the simulations and the real measurement. Mechanical handling wafer spec SEMI M74 was published in Nov Required for pitch spec Gravitational Sag + Wafer Thickness (µm) point support (Periphery) S a g W afer Thickness (µm) 4 point support (Sag Measu minimum) red Wafer carrier and measured positions

10 Developmental test wafers Silicon suppliers progressed on the learning curve, started moving from the modified 300mm equipment used in the earlier stages to 450mm dedicating equipment In parallel inspection equipment development enabled wafer quality improvement Developmental (test) wafers spec - SEMI M76 was published in July 2010 Three types of wafers have been specified with properties defined to assist manufacturers in choosing the most cost effective wafers for a given application: Lithography monitor having tighter wafer flatness Particle Monitor - having less surface particles and allowing higher Boron concentration to reduce COP Other monitors for example monitor wafers for furnace and thermal cycles development requiring Oxygen concentration specification

11 Silicon wafers - current status Silicon suppliers are continuously enhancing their 450 manufacturing capability improving wafer quality. Current state of the art crystals and cleaning processes allow producing a wafer quality compliant with the SEMI M76 spec, and advancing toward prime wafers capability. Wafer particles level are well in spec for both 45nm and 32nm size. Polishing process still requires improvement mainly of wafer periphery to achieve the required SFQR. SEMI M1 spec have been revised (August 2012) to include basic 450mm prime wafer requirements for the and 16nm technology generations. Notch replacement by a fiducial mark will require participation of several SEMI standards committees (silicon, traceability and PIC) updating many existing specs (M1, M74, M76, MF1152, T7, T10, E118) and creating new ones. EE reduction will also require modification of several specs MI, M49 and M52.

12 450 silicon - challenges ahead The silicon suppliers past technical efforts focused on improving the crystal quality and reducing defects have been successful. In recent years the focus has shifted from crystal defects to mechanical aspects of wafer fabrication, driven by the device shrinking litho requirements. The strong interaction between the wafer geometry and the process yield, drives tightening of geometry requirements. New parameters are specified as we progress from generation to generation and gain better process understanding. Wafer shape is impacted by the IC process, further limiting bare silicon flatness requirements. Wafer geometry characterization is challenging for both silicon and device manufacturers. This effort will be amplified by transistors shrinkage and by the increased wafer size Wafer cleaning process and inspection equipment improvement enabled reduction of both LLS size and levels; looking forward the silicon manufacturers and the inspection equipment challenge is too produce, measure and classify continuously smaller sizes defects..

13 Wafer Geometry Evolution Flatness NT ERO Edge Dimensions Localized Features Wafer geometry is critical to lithography application and has been driven by IC scaling in the past decades. Wafer geometry roadmap is driven by shrinking depth of focus. DoF requirements are same for un-patterned and patterned wafers. 193i extending beyond 18 nm half pitch D o F ( n m ) Half pitch (nm) SEMICON West 2011 ARFi EUV ITRS wafer flatness Wafer Flatness Scaling with DoF According to ASML. wafer flatness represent about 30% of DoF for immersion lithography Localized feature (back surface) ASML Height Data (nm) Defocus (Front Surface) (nm) (nm) Localized features on the back surface of the wafer can impact defocus

14 Wafer shape Traditional bow and warp metrics are insufficient or non-optimal to characterize complex contour of wafer shape. New higher order shape (HOS) metric is required to capture local shape variations. Rethinking Wafer Shape Concept J. Qiu and J. Sinha SEMI Standards AWG, SEMICON West 2011

15 Wafer Edge Roll-off and Lithography defocus Edge roll-off impact is clearly observed in the near edge defocus data and good correlation is observed between ESFQR and near edge Edge roll off improvement is critical for improving edge die yield for advanced technology nodes Distance from edge where this ESFQR can be achieved determines usable wafer area. In the case of G450C edge exclusion reduction program correct ERO specification is critical to achieve anticipated yield improvement. 32 nm 22 nm 18 nm 16 nm ESFQR EE 1 mm (SEMI M ) [nm] ESFQR EE 1 mm (required) [nm] ESFQR Computation Method Advanced Wafer Geometry vs. Lithography Workshop SEMICON Japan Dec ESFQR is computed for 72 sectors (Radial length of sector: 30 mm) Thickness profile is computed by connecting values at each radii Sample ERO in a sector

16 450 program - looking ahead Currently the 450mm consortium (G450C) is working intensively with suppliers to complete development and test >50 tools platforms. The next 450mm transition phase will be the establishment (in house) of pilot lines by individual IC manufacturers, with detailed technology goals defined by the company business requirements. A full flow set of automation systems, production process and metrology tools capable of meeting technology targets will be required for this time. 450 mm process, tools and metrology modules will continue to progress through technology generations just like 300mm There are many challenges ahead of us, some 450mm specific others related to the evolutions in the technology generations and amplified by the wafer size increase.