Adaptive Patterning. ISS 2019 January 8th

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1 Creating a system to balance natural variation ISS 2019 January 8th Tim Olson Founder & CTO

2 Let s start with an industry perspective Historically, three distinct electronic industry silos Foundries SATS EMS Semiconductor Devices Nanometers Packaging 10 s of Microns Electronic Systems 100 s of Microns

3 in past few years Blurring of lines to convergence Foundries SATS EMS

4 in past few years Blurring of lines to convergence Foundries SATS EMS With industry leaders investing across historic boundaries

5 Examples from industry leaders #1 Foundry #1 SATS #1 EMS TSMC Grew a new $2.5B business in wafer bumping, test, CoWoS & InFO ASE Grew a $1.4B wafer level and a $1.5B systems modules business Foxconn Launching $9B USD new chip fab through Sharp acquisition

6 What technology s leading the convergence? Wafer Level Fan-out Technology (WLFO) High Level Fan-out Process Chip First Fan Out Chips First Fan-out Wafer Silicon Dicing Device Wafer Singulated Wafer Devices Chip Reconstitution Attached on Carrier Molded Molding Plastic Wafer RDL Formation Wafer Fab Processing Backend Processing Part assembly - SATS Part wafer fabrication - Foundry Part electronic system integration - EMS Flow courtesy of John Hunt, ASE

7 Fan-out - Let s take a look inside The concept The realization Backside Epoxy Silicon Device Cu Stud Mold Compound Planar Surface Cu RDL 1 3 layers Embedded Chip Note: Multiple patents granted & pending

8 M-Series Fan-out Process Modules

9 M-Series Basic Process Flow Die attach leads to # challenge in fan-out Die Shift

10 Die shift - #1 challenge in fan-out Precision of monolithic silicon is lost - semiconductor devices are singulated & recombined in a physically different format to re-create a 300mm wafer (in plastic) Two major sources of positional variation Die placement tolerance Die shift during molding Nominal designed positions Resulting chip position in fan-out wafer (panel) Nominal designed positions Actual measured positions

11 M-Series Basic Process Flow 300mm plastic wafer (panel) post planarization

12 M-Series Basic Process Flow Actual measurement data of 2,478 devices in a 300mm panel

13 Tax revenue How to solve the die shift challenge? Conventional linear thinking is usually the starting point i.e., Drive all sources of variation to zero to eliminate die shift Let s draw a corollary to something that impacts everyone in the room Taxes & Tariffs January 7, % 100% Tax rate Rep. Alexandria Ocasio-Cortez, D--N.Y. Proposing 70% tax rate! Conventional linear thinking Increase taxes & tariffs lead to increased tax revenue

14 Conventional linear thinking is the wrong model Taxes, Tariffs & the Laffer Curve Art Laffer economist, author, educator Source: Forbes 2012 Overcoming the classic failure of conventional linear thinking! 1974 Art Laffer met with Dick Cheney & Donald Rumsfeld drew his curve on a napkin

15 Back to solving the die shift challenge? Conventional linear thinking Use a high precision die attach machine Partially effective and very expensive

16 Just how expensive is it? Breakdown of capex for overall fan-out flow Pareto of top five capex items

17 Deca 10X thinking the inspiration Space Invaders Use video gaming methodology to create real-time EDA in manufacturing.. adapting a nominal design to perfectly match the variation of every chip on every wafer We call it

18 Let s look at in action Deca s M-Series structure Deca test chip

19 in action Adaptive Alignment* Align the entire Cu interconnect pattern to the measured die position Adaptive Routing* Dynamically adapt Cu interconnect to the measured die position Enables high metal density designs Precisely aligns inductors to the die BGA array fixed to package outline Enables multi-die fan-out & SiP *Note: Multiple patents issued & pending

20 Adaptive Routing in Action A Fully Molded Fan-out Wafer Level Package

21 Multi-mode IoT Module 2 chips High performance MCU 40nm Bluetooth radio 55nm Package 5.0 x 3.8 mm 104 IO, 0.4mm pitch Die 1: 3.7 x 3.2 mm Die 2: 1.0 x 2.0 mm

22 Multi-mode

23 Multi-mode

24 Scale of Adaptive Patterning LSST - Large Synoptic Survey Telescope World s largest camera, 8.4m primary mirror Coming online in 2022 in Chile Maps the entire sky every two nights Deca s Adaptive Patterning 1 st real-time design in manufacturing In production since mm round reticle in single GDS II file LSST Camera Specs: 3.2 Gigapixels every 20 seconds 160 Megapixels per second Adaptive Patterning Specs: 300mm designed & exposed each 28 seconds 90 Gigapixel file, 3.2 Gigapixels per second 600mm next gen 2µm system 36 Terapixels in 140 seconds 257 Gigapixels per second

25 Back to our fan-out problem Die location measurement results why bimodal?

26 High speed die attach with dual gantries 20 nozzles per head, two heads = 28,000 cph

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28 Adaptive Patterning Delivering > 10X capex cost breakthrough for die attach

29 Adaptive Patterning Conventional linear thinking Power of thinking differently Pareto of top five capex items Pareto of top five capex items

30 M-Series Building Blocks Direct Connect Thick Cu Low contact resistance, multi-via capture Polymer Isolated Via Further stress isolation, tighter design rules Multi-Layer, multi-thickness RDL & Dielectrics 10µm 5µm 2µm 5µm Nested Lines 5µm Isolated Line

31 Fan-out incorporating decades of learning Wafer fab bumping WLCSP Flip Chip Assembly Coreless Substrate Wafer Level MEMS Fan Out Fan Out Heterogeneous Integration Conformal Shielding Antenna on Package Fan Out Multidie Fan Out 3D 2.5D Interposer Graphic created by & courtesy of John Hunt, ASE

32 Why does it matter? Source: TechSearch International & Deca estimates

33 What s next? Integration of 4 reticle size chips in 80mm x 80mm format Graphics created by & courtesy of Craig Bishop, Mango Dynamics

34 What s next? Adaptive patterning with < 1µm total system inaccuracy Graphics created by & courtesy of Craig Bishop, Mango Dynamics

35 What s next? Scaling to 600mm wafers (panels) Future Production Initial production 300mm round Large panel format

36 What s next? Scaling to 600mm wafers (panels)

37 Why large panel M-Series? Wafer Processing Cost 300mm round baseline* 7% 5% 43% 45% Depreciation Materials *Estimated industry average COGS of M-Series with Adaptive Patterning Labor Fac, Ovhd, Other M-Series large panel fan-out has the potential for >30% cost reduction Capital productivity Material efficiency

38 Scaling to large panel in cooperation with ASE Initial Production Future Production 300mm round (post chip attach) (post mold & debond)

39 A Closing Thought What lies behind us and what lies before us are tiny matters compared to what lies within us. Ralph Waldo Emerson Ralph Waldo Emerson

40 Thank You