Brief Introduction of Sigurd IC package Assembly

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Merilyn Allen
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1 Brief Introduction of Sigurd IC package Assembly

2 Content Package Development Trend Product Brief Sawing type QFN Representative MEMS Product LGA Light Sensor Proximity Sensor High Yield Capability Low Cost Solution Rapid Product Design / Phase-in 2

3 Sigurd Assemblies Today Thin WLCSP QFN/DFN LGA Proximity sensor TSOP SOT/TSOT QFP SSOP MEMS Thick DIP SOP CIS/CCM PLCC Large 3 Small

Assembly Product Roadmap 300mm WLCSP Technology Integrate LED & Receiver Light Sensor Single receiver RF 3G technology LGA Embedded component Solar cell module MEMS G-sensor

4 Assembly Product Roadmap 300mm WLCSP Technology Integrate LED & Receiver Light Sensor Single receiver RF 3G technology LGA Embedded component Solar cell module MEMS G-sensor technology Glass Wafer sawing MEMS SIP assembly Jan Jan Jan Jan Development Photo type Production Direction: small size, multi-chip, more component. 4

5 Package Structure Sawing type / QFN Molding Compound Chip Gold Wire Chip Mold Compound Cross section 0.55, 0.75 & 0.9 mm Lead Frame (PPF/ Spot Ag) Exposed Die pad Marking OOOOO OOOOO DA Epoxy Bottom view Top view 5

6 Package Type QFN/ DFN Remark: : L/F is ready. : L/F need to be created. Package thickness: 0.55, 0.75, and 0.90 mm 6

7 Representative MEMS Product MEMS Telecom Switch (production) High-volume application Stacked Die for small footprint and low impedance interconnect CMOS Controller for switch drive and digital interface Lid (LCP) CMOS Controller MEMS Die Au Bond-wire Leadframe 7

MEMS Stacking Die Technology Design and develop MEMS

Package thermal expansion control solution.

8 MEMS Stacking Die Technology Design and develop MEMS with driver in one package System in Package technology. Multi-layer bonding 4-layer wire loop capability. Package thermal expansion control solution. Package type: Injection molded type & Air cavity type. Turn key solution. Pictures of stacking die with wire bonding 8

9 Thin Package Solution - SOT / TSOT Features: 2.9x1.6mm package size 1.9mm lead pitch SOT thickness 1.1mm TSOT thickness 0.75mm Green product Application: Power management Power switch RFID 9

4mm lead pitch Green finish available Excellent electrical and thermal

10 Features: LGA (land grid array) 3x3mm to 10x7mm package size 7 to 29 pin counts 0.4mm lead pitch Green finish available Excellent electrical and thermal performance Full in house design ability Passive component Application: RF module Logic Memory Epoxy Substrate Passive component 10

11 Light Sensor Features: 1.6x1.6mm to 3x3mm package size 4 to 12 pin counts 0.5mm lead pitch Green finish available Excellent electrical and light performance Full in house design ability Application: Clear Compound Chip Gold Wire Cell phone Notebook `` Clear Compound Chip Touch control panel Silver Epoxy PPF Lead Frame 11

Excellent electrical and light performance Full in house design

12 Proximity Sensor Features: Customized package 4 to 12 pin counts Integrate LED and Receiver in one package Green finish available Excellent electrical and light performance Full in house design ability Application: Cell phone Notebook Touch control panel 12

13 WLCSP Chip Cover Chip Bump Carrier Features: Die size: 0.3mm x 0.3mm till 15mm x 15mm Bump size: 90 ~ 250um Carrier/Cover tape: 8/12/16/24/32 mm tape width capability waffle pack: 2 x 2 ~ 4 x

14 High yield capability Ass y y Yield trend: Assembly Yield 100 Total Yield 99.5 Power QFN 99 Jan' 10 Feb' 10 Mar' 10 Apr' 10 May' 10 Jun ' 10 July ' 10 Aug '10 Sep '10 Oct '10 Nov '10 Dec '10 Jan '11 Feb '11 Mar. '11 Apr '11 May '11 Jun. '11 LGA Total Power QFN LGA Month Remark: average yield above 99.95%. 14

15 Equipment List For Assembly Process Vendor Remark Grinding Okamoto Accuracy: +/- 5um Saw Disco/TSC Die Bond ESEC / ASM / Panasonic Accuracy: +/- 25um Wire Bond ASM / KNS / Panasonic Accuracy: +/- 3um Sealing RJR / GPM Molding Towa / Ki-Giant Offset: +/- 20um Marking Singulation saw Trim/Form Printer Mounter GPM / E&R Disco / KnS GPM / Ki-Giant Hitchchi Suzuki Re-flow NRY540SCC7Z Yamato 15

16 Grinding Die Bonder Die Sawer 16 Wire Bonder

17 Mold System PMC Ovens SMT Line Singulation Saw 17

18 Microscope 3D Optic System Die Shear System Wire Pull Tester 18

19 Assembly capability (bond wire size (Au/Cu), bonding capability for single row/ dual row and offset pads, grinding capability, and so on) 19

20 Process Capability Process Item Process Capability Wafer Size 6'' / 8'' Wafer Grinding Minimum final thickness 4mils Parallelism TTV < 5um Thickness Variation between wafers <=10μm Wafer Size 4~8 inch Cutting Method through Cut/ Step Cut Wafer Sawing Minimum chip size cutting 0.2mm square DI water Resistivity >=10MΩ Chipping width <=10μ m Cutting street >50μ m Wafer Size 4 ~ 8'' Acceptable die size >0.2mm square Pick Type wafer mapping/ Ink Dot Die Bonding Bonding Type Epoxy type Epoxy Bleeding <10mils Epoxy thickness 5~40um Epoxy Voids within 5% in die area Die Placement Accuracy Theta :±0.5º ;X/Y:± 2 mils 20

21 Process Capability Process Item Process Capability Wire Bonding (Au wire) Wire Bonding (Cu wire) Fine Pitch Capability wire size Loop height control Bonding Frequency Bond placement repeatability Bond pad pitch (single/ dual row) Bond pad openning Staggered bond Wire Span Fine Pitch Capability wire size Loop height control Bonding Frequency Bond placement repeatability Bond pad pitch (single/ dual row) Bond pad openning Staggered bond Wire Span 45um 0.7 ~2.0 mils ±25um 138K HZ 3um 45um 40um 30um ~8mm 60um 0.9~1.2 mils ±25um 138K HZ 3um 60um 50um 40um ~10mm 21

22 Process Capability Process Item Process Capability Die Coating Viscosity 500 ~ cps Sealing Accuracy 4mils Molding thickness 0.55/0.75/0.90mm Lead frame handling thickness 0.15mm Molding Wire sweep <5% Body offset/ off center <1 mil Marking Symbol Laser/ Ink Plating Plating composition Pb/Sn(85/15%) (Apply to lead frmae type) Lead free capability Pure Tin (100%), Sn/Bi(98/2%), Sn/Cu(99/1%) Trim \ Forming Coplanarity <4mils Solder Thickness 0.12 ± 0.06 mm SMT Component size Min Mount for SMD ± 2.0 mils 22

23 Low Cost Solution Material evaluation ex. To study low cost materials with high quality Au wire Cu wire To co-work with customer to reduce the gold wire dimension Package design ex. Smaller package design to increase product value QFP QFN SOT TSOT To integrate more chips and components in one package (SIP design) 23

24 Rapid Product Design/Phase-in in 1. Capability: Stack die SIP design MEMS product design/production Product design 2. Sample making timeline: Available package: 1 week for sample making. New type lead frame/substrate: 4~6 weeks for prototype. New package/product: around 3 months (based on product requirement) 24

MICROELECTRONICS ASSSEMBLY TECHNOLOGIES. The QFN Platform as a Chip Packaging Foundation

West Coast Luncheon January 15, 2014. PROMEX PROMEX INDUSTRIES INC. MICROELECTRONICS ASSSEMBLY TECHNOLOGIES The QFN Platform as a Chip Packaging Foundation 3075 Oakmead Village Drive Santa Clara CA Ɩ 95051