2016 Substrate & Package Technology Workshop Highlight

Transcription

1 2016 Substrate & Package Technology Workshop Highlight Webinar July 13, 2016

2 Theme of the Workshop inemi roadmap and Technical plan highlighted that year 2015 was the year entering critical package technology in revolution, especially on SiP integration. This workshop focused on the advanced package technology area, and to have discussed on the technology status and future needs on this technology areas. 2

3 The Workshop Goals Identify the top few gaps where pre-competitive collaboration can and will deliver meaningful progress for the industry and the players

4 Workshop Program # Presenters Presentation Title # Presenters Presentation Title 1 Santosh KUMAR Yole Development An Overview of Market and Technology trends in the Advanced Packaging ecosystem 7 SW Yoon, STATSChipPAC ewlb /FO-WLP : Present and Future of Advanced Wafer Level Packaging Technology 2 3 Wei Keat Loh Intel Sze Pei Lim Indium Corp. Package Scaling and heterogeneous integration Solder Alloy Options for the Semiconductor and PCB Assembly 8 Hiroaki Fujita Hitachi Chemical Advanced substrate materials for next generation low CTE/thinner package with high reliability 4 Tetsuya Koyama Shinko Device Embedded Package MCeP for SiP application 9 L.C. Tan, NXP Semiconductors SiP in NXP 5 Eric Kuah ASM Wafer/Panel Level Encapsulation - an Alternative Format for Plastic Packaging: Its Challenges and Solutions Koichi Nonomura KYOCERA Stanley Wu ASE High End Organic Substrate Direction Innovative SiP Technology 6 Curtis Grosskopf IBM An End User's Perspective on Qualifying New Packaging Technologies 12 Surya Bhattacharya IME Heterogeneous Integration Platforms for Mobile and IoT 4

5 5 Example #1 Yole

6 6 Example #2 Intel

7 7 Example #3 Indium

8 8 Example #4 Shinko

9 9 Example #5 ASM

10 10 Example #6 IBM

11 11 Example #7 STATSChipPAC

12 12 Example #8 Hitachi Chemical

13 13 Example #9 NXP

14 14 Example #10 Kyocera

15 15 Example #11 ASE

16 16 Example #12 IME

17 Presentations Quality/ Reliability Testing Failure modes of advanced packages Field return defects, appropriate test Materials Requirement & Performance Substrate, laminate, underfill FO-WLP, WLCSP, Embedded Compression Molding for High Dense Module Process & Yield Improvement Standardization (cost reduction potentials) Guidelines for board level assembly to handle various new packages 17

18 Opportunities for Collaboration Quality/ Reliability Testing Common Materials Process & Yield Improvement 18

19 Team A Quality & Reliability Testing

20 Team A participants Feng Xue / IBM Haley Fu / inemi CK Yeo / Delphi Wayne Ng Chee Weng / Nihon Superior Tony Tong / Microsoft Tao Li / Microsoft Tetsuya Koyama / Shinko

21 Problem statement Lack of understanding of the assembly processes and application environments of all potential end-users (vs targeted end-users) to develop the reliability test methodology for new package/materials development

22 Current situation - Test plan only focus on standard test methodology and comply to customer requirements - Current test standards may not capture the reliability risk in the new package, or may over stress the new package. - Field failures do not really feedback to test plan - For new materials/package development, test plan completeness is always questionable. - Little effort for the industry to come out with new test standard

23 Key Challenge Industrial Collaboration on early learning of failure mode and application condition Information is largely shared between supplier and customer under NDA. No common platform for early learning sharing. The boundary between sensitive data and data which can be shared is not clearly defined. Lack of Understanding on the impact of assembly process condition on packaging reliability.

24 Recommendation Develop a methodology (highlighting best practice, e.g. test to fail, FMEAs) for qualifying new packaging technology Validate the methodology by reviewing issues and failure modes from a few recent packaging technologies developed in past ten years (e.g. copper wire bonding, wirebonded stack die, Package on Package) Apply the methodology to selected new technologies for effectiveness and completeness

25 Test to Failure for Packaging Development Problem: In the product development phase of a project, the purpose of validation testing is to prove product designs meet an acceptable minimum reliability level; not to conduct a full-scale reliability/life test. The result is a demonstration test to pass in which failures are hoped to be avoided. Test to Failure and Its Benefits New Packages/Products are tested beyond minimum specification levels. Depending on the new design or materials involved, the relevant test to failure experiment can be selected from power cycle, thermal cycling or shock, high temp/low temp storage and etc. Endurance type testing exposes the weakest link in the product reliability Failure modes can be investigated and identified to improve future designs Statistical distributions can be tracked and compared between products Historical data can be used to design experiments for new products Data can be used to correlate with validation test results and vehicle life cycle in various environments (under hood, in cabin, etc. )

26 Team B Material Performance & Requirement 26

27 Team Discussion Facilitator: M. Tsuriya Lead: Dr. Loh Wei Keat (Intel) Team Participants: Koichi Nonomura (Kyocera) Alex Orbacedo (Kester) Lim Sze Pei (Indium) Qiang Wei (Nelco) Tetsuya Koyama (Shinko) Hiroaki Fujita (Hitachi Chemical, Shimodate Works) Stanley Tsui (ASM) Eric Kuah (ASM) 27

28 Environment Scan and Challenges Environment scan: Higher density; thinner packages Smaller interconnects FLI (First Level Interconnect) and SLI (second level interconnect) Complex multichip package (WLP &FCCSP/BGA etc) that leads to longer assembly process Increasing use of mold for WLP and PLP Challenges: Increasing reliability issues in these areas Substrate/Mold/CUF outgassing (moisture and volatiles) Laminates delamination and poor adhesion of MUF and CUF Warpage due to high CTE polymer Limited liquid mold supplier with compatible mold properties that meets packaging needs (eg: <50um mold cap, low cost, <25um gap) Filler size used in DAF polymer become substantial geometry compared to interconnect size.

29 Top Priorities & Recommendation Polymer Outgassing/Hydrophillic Behavior Laminates and MUF/CUF Adhesion Improvement Next Gen Encapsulant (CUF/MUF)

30 Polymer Outgassing/ Hydrophillic Behavior Re-establish the mechanism of outgassing & hydrophillic behavior of packaging material: substrate (core, ABF, SR, prepreg), mold, cuf and etc. Reformulate resin to give better resilient to outgassing nano pores formation during curing (see pix below) Define qualification method for outgassing gravimetric alone is not enough as stress is a function of pressure, specific volume and temperature. Blister Second level solder splashed during the blistering event UF Crack 30

31 Laminates and MUF/CUF Adhesion Improvement Define better surface treatment (adhesion promoter, plasma, blasting, silane and etc). Significant process optimization needed to enhance adhesion need more robust method Consistency of surface treatment coverage and repeatability (wettability adhesion strength) Surface treatment need to sustain across exposure assembly environment Develop test methods and analytical techniques Lab scale vs actual sample Standard test procedure for material suppliers wetting angle and standard test 31

32 Next Gen - Encapsulant (CUF/MUF) Low cost and smaller filler size encapsulant - (<50um mold cap) Compatible to existing molding platform Wafer to Panel New encapsulant formulation that exhibits: Good flowability, shear curing behavior, low volatile voids that meets current molding design. Compatible CTE to address warpage concern Plating Compatibility Standard chemical shrinkage quantification 32

33 33 Panel Size Processing

34 Problem Statement Compare with wafer form manufacturing, manufacturing cost should be lower with standardization of panel size. Based on the package quantity in wafer form or panel form, for panel form it might be increasing package quantity especially large package size. Therefore packaging manufacturing cost of panel form is lower than wafer form manufacturing. Wafer Form Panel Form

35 Suitable Panel Size Standardization of Panel Size: For wafer size, wafer size standard specification was decided. But for panel size, there is no standard size of panel form. Therefore, each equipment supplier made their own panel size. It should be increase equipment cost. To reduce equipment cost, panel size standardization is necessary. Area to be considered: equipment process optimization material

36 Potential Area Investigate the Future needs of Panel Size Processing Technology Collect the inputs from Assembly houses, equipment manufacturers and material manufacturers for current status and their strategy Material Process Equipment readiness Suitable Size Issue the white paper for cost benefit 36

37 37 NEXT STEP

38 Initiative Development These recommendations are followed up for initiative discussion. Your proposals are welcome. Contact Haley Fu 38

39 Haley Fu M. Tsuriya