System in Package Workshop

Transcription

1 TWI, Granta Park, Abington, Cambridge 12th December 2007 The IeMRC s System in Package Workshop took place on 12 th December 2007 at TWI s Granta Park facility near Cambridge. The event was opened by Dr Roger Wise, TWI s Technology Group Manager, who welcomed everyone to TWI and gave an overview of the history and activities of TWI. TWI was originally known as The Welding Institute and had originally focussed its attention purely on welding but in recent years it had diversified significantly and now specialised in a much wider range of joining technologies including those pertinent to electronics. Martin Goosey, the IeMRC s Industrial Director, then gave an introduction to the IeMRC, its objectives and mode of operation. The IeMRC was currently supporting over 30 research projects in UK academia ranging from relatively small feasibility studies to two large scale flagship projects, each involving several universities and numerous industrial partners. Three brief examples of current IeMRC projects were cited and these included the flagship project that was working on the development of optical interconnect PCBs. Martin concluded by thanking TWI and the Electronics Enabled Products KTN for sponsoring the event. The first presentation of the workshop was given by Dr David Pedder, Technology Manager at TWI, and was entitled Recent Developments and Future Trends in System in Package and Embedded Passive Technologies. David began by outlining the drivers that were causing industry to take more interest in System in Package (SiP). Interestingly, these included the changes in manufacturing competence and the shift of manufacturing to China. Another driver was the growth in cell phone functionality, which now often required imaging, web access, , Bluetooth and decreasing cost per function. The growth in silicon device size was slowing and silicon feature size reduction was also slowing, while product lifetimes were getting shorter. Additionally, there was growing use of MEMS in electronics. On a typical PCB, passive components typically comprised 91% of the component count and 29% of the solder joints, while occupying 41% of the board area. One trillion passives were surface mounted per annum and the number of devices required was still growing. As discrete components became smaller, there were increasing issues around yield, solder joint reliability, performance and parasitics. Thus, there was increasing interest in embedded passives; they offered reduced size and weight, higher functionality, improved performance, reduced cost per function, improved reliability and EMC issues, reduced wiring demand and several other advantages. David then reviewed the technology options such as the on-chip, thin film, LTCC and PCB based technologies. The thin-film route had a growing manufacturing base as it could offer higher resolution, performance and enhanced passives density. Companies such as NXP (formerly Philips) were pushing this route. On-chip

2 passives were then reviewed and the advantages and disadvantages discussed. Thin-film passives were typically produced on silicon or glass and conductors/inductors were made using either aluminium or copper. Examples of thin film applications were shown and these included RF modules such as HIPERLAN, GSM and Bluetooth devices. LTCC offered a mature technology on glass ceramic substrates. Inductors were formed using thick film silver alloy metallisation and capacitors could be formed using glass ceramic or ferroelectric materials. Example RF modules were also shown. There was said to be a drive for PCB based passives and standard substrates such as FR4 could be used. In this case, inductors were formed using the copper metallisation and capacitors could be made using both laminate and polymer thick film or ceramic thick film routes. Resistors were made using nickelphosphorus, platinum alloys and polymer or ceramic thick film routes. David then showed a chart comparing each of the techniques in terms of key attributes. He then moved on to discuss the benefits of SiP and to compare the approach with System on Chip. Multiple active and passive die could be included in a standard package outline. The ITRS roadmap for SiP was then discussed showing the predicted evolution from 2004 to The number of die in a package was expected to fall from 10 to 8 by 2013 and this reflected the higher levels of integration that were being achieved. Design methodologies were then reviewed and the importance of right first time design was highlighted. It was also essential to start with a well-defined process architecture, using stable processes with known capabilities. A design example of a 0.9 GHz filter was then shown. David discussed the ADEPT-SiP multipartner project and the device architectures that were being developed. Shipments of SiP devices were said to have been 3543 million units in 2006, up from 2877 million in TechSearch International was predicting that the figure would exceed 4500 million units by The key application focus areas for the future would be high frequency, high clock speed and size. Professor Andrew Richardson of Lancaster University then gave a presentation on System in Package Research within the IeMRC. These projects included work at Lancaster, Heriot Watt and Greenwich Universities, as well as contributions from a large number of industrial partners both within the UK and the rest of Europe. Andrew described the two key projects the IeMRC was supporting. The first was called Design for Manufacture for SiP and was focused on the reliability engineering of SiP assemblies. The second was called Integrated Health Monitoring of MNT Enabled Integrated Systems. This had a focus on embedded test and health monitoring of SiP based systems and included NXP, Qinetiq, Coventor and MCE as industrial partners. Andrew then went on to detail what exactly System in Package was; it was defined as the integration of several integrated circuits and components of various technologies (RF, silicon, GaAs etc) in a single package resulting in one or several electronics systems. The SiP approach enabled cost reductions and a higher speed to market because existing known die could be

3 used. Market trend information from Gartner showed that SiP would have a 10% CAGR from 2004 to 2009 and that SiP devices were finding as much use in consumer applications as in communications. The team at Lancaster University was specifically looking at wafer level SiP and the drivers were size reduction, performance cost improvements. The key challenges included board level reliability, assembly flow and customer acceptance. Results of studies into solder fatigue were then shown. As the modules became larger, the number of cycles to failure became shorter, thus highlighting the importance of thermally matching disparate materials. Andrew then moved on to describe the actual work being undertaken in the IeMRC supported projects. The influence of different types of underfill on reliability had been investigated. The health monitoring concept for SiP was then described. A key challenge was monitoring the performance of devices that had no electrical input/outputs etc such as MEMS/accelerometers. One possible solution was to incorporate additional sensors within the package and the industrial partners had confirmed that there was a real need for this approach for some applications. For example, a humidity sensor was needed for monitoring the environment around some MEMS devices. Lancaster were now thinking about a complete embedded test architecture that covered both interconnect, intraconnect and MEMS within the SIP. This could be envisaged as being based on the use of plastic electronic devices with a standard pin-out/footprint for the test interface. The concept of bias superposition was then presented and initial results had shown that it could be successfully applied to certain functions, such as with embedded accelerometers. Andrew concluded by showing an example of a novel DfX flow which included the reliability, integration and test issue considerations right at the start of the process. The final presentation of the morning session was given by Dr Stoyan Stoyanov of Greenwich University and his paper was entitled Design for Reliability for System in Package. Stoyan began by reviewing exactly what SiP was and why it was so important. He then introduced the WL-SiP reliability challenges, such as thermal mismatch, board level solder joint reliability and the fact that reliability decreased with increasing size. There was thus a need for co-design in SiP incorporating thermal, mechanical and electrical analysis and several other factors. Stoyan then went on to discuss a new SiP friendly package platform processed at the wafer level with built in substrate routing; this used a moulding compound to carry the fan-out area. Fan-out and fan-in WL-CSPs were then compared and contrasted. Fan-in was miniature and low cost but had pad limitations and poor acceptance by some customers. An analysis of a fan-out SiP structure was then presented and simulation technology had been used to assess the effect of moulding compound thickness, fan-out ratio and moulding material. It had been found that the reliability improved if the moulding compound thickness was reduced. An example of a transmitter receiver module used in an avionics application was shown and the results of lifetime prediction modelling were presented. Simulation work had also been carried out on crack growth rates for various

4 field cycles likely to be encountered in service. It was found that, with no underfill, the package would not survive the required service life. Also, even when there was an underfill, it was critical to use the correct material. Stoyan then discussed virtual prototyping and design for reliability work that had been undertaken. A finite element model of a SiP was shown and this used an eighth section of the device. Design variables included PCB thickness, board level solder joint stand-off height and passive die thickness. Damage parameters such as maximum warpage of the package and device lifetime were included. Stoyan concluded by confirming the large amount of interest in both SiP and Wafer Scale SiP. He also reinforced how design for reliability for SiP was a key requirement. Following a networking lunch, the first presentation of the afternoon was given by Alaa Abunjaileh of Leeds University and this was on the subject of Simulation and Design Route Development for ADEPT-SIP. The ADEPT- SIP project included industrial partners such as AWR Ltd, Flomerics, Zarlink, Filtronics, Wurth and TWI. This DTI supported project aimed to develop and demonstrate a rigorous, right-first-time, design and supply chain management methodology for novel System-in-Package electronics product functions. The ADEPT-SIP PCB had 6 layers and the outer layer had 100 micron track widths and 300 micron vias. Two types of capacitors were being evaluated; prepreg and polymer thick film and the prepreg capacitors typically had values of 1 pf/mm 2. The aim was to achieve the optimum component performance and to build this into a design kit. Project deliverables included technology test vehicles for characterisation, model derivation and verification, technology and component models, embedded passives parameterised component models and design toolkit, a supply chain management methodology and SiP demonstrators in the digital, mixed signal and RF applications areas The next presentation was given by Piers Tremlett from Zarlink and he discussed Future Trends in SiP for Medical and Related Applications. 75% of packages processed by Zarlink at their packaging foundry in Caldicott were for medical applications. Piers then went on to describe the design requirements for cardiac pacemakers that were implanted in the shoulder region. Pacemakers dominated the medical implant market and they provided the most effective treatment for arrhythmia. These devices had to be as small as possible, with high reliability and relatively low cost. The SiP format was therefore quite attractive and Zarlink were involved in three related research projects; SHIFT, CiP and ADEPT. There were various difficulties that had to be overcome when using an embedded component approach eg full PCB manufacturing was required. The SHIFT project was working on embedding die in flex circuits. Thermo-compression bonding was used to connect the die to the substrate and this assembly was then laminated using prepreg. The Chip in Polymer project had the objective of reducing RF module SiP devices to below half their existing size. The approach was based on an FR4 core with plated via connections to the die. This required the die wire bond pads to be plated with nickel/gold or gold. After lamination of another layer on top of

5 the chip, vias were laser drilled down to the device bond pads. This type of module had been shown to be capable of surviving 3000 thermal cycles but it did incur extra costs in terms of the need to plate the die pads. It also offered a much more compact module size. Planar embedded passive components were then discussed and the focus was on laminated layers for inductors, capacitors and resistors. The concept of embedding discrete passives in the substrate was described and it was currently used in some products made in Japan. Piers then went on to describe a potential Zarlink module design which was based on normal PCB and SMT assembly approaches and that offered reduced size and reliability similar to CiP. It also gave an integral RF shield with protection of the components. Currently, the supply chain was immature and Zarlink still had some way to go before they would achieve what they needed. However, Piers said that SiP would ultimately deliver the next generation of miniaturisation. Then final presentation of the workshop was given by Davide de Maio of NPL and was entitled Fatigue Properties of SIP Solder Joints. The design of test specimens used in this work was described and these were used in a shear configuration with copper arms and solder joint (SAC305). The samples were subjected to isothermal fatigue testing with a 40 minute cycle. The influence of surface finish on lifetime had also been investigated via measurements of increases in resistance. An immersion silver finish had shown a better lifetime than tin at room temperature. Stress relaxation at various temperatures, and for various dwell times, had also been evaluated. For each solder joint there was a limited amount of energy required to break it and this depended on the geometry and the material. Simple shear strain had been evaluated as a function of the crack length and hysteresis stress strain data measured at 24 C was shown. Davide then discussed the techniques used to assess electromigration. The workshop then concluded with Darren Cadman of the IeMRC thanking the speakers for the excellent coverage of the papers. The intention was to make the presentations available on the IeMRC website in the near future ( Overall, this was a well attended workshop that, thanks to the expertise of the speakers and their breadth of coverage, provided a wealth of useful information to the attendees. Martin Goosey 12 th December 2007

6 L to R: Davide de Maio (NPL) and David Pedder (TWI) L to R: Nigel Rix (Electronics KTN) and Darren Cadman (IeMRC) L to R: Alaa Abunjaileh, Davide de Maio, Martin Goosey, Andrew Richardson and Stoyan Stoyanov