Newsletter no. 01 / Nov. 2009

Transcription

1 Newsletter no. 01 / Nov. 2009

2 Content Issue No. 1: I. Why chip embedding? II. Objectives & aims III. Supply chain IV. Building up the business V. Embedded applications in HERMES HERMES consortium Contact Welcome to this first issue of the HERMES Newsletter! HERMES is the first EU funded project in the frame of FP7 that enables an industrial consortium to develop a technology to the maturity level for industrialisation. The idea to bring the chip embedding technology in the European market place to enable new business on large scale was for the European Commission a very strong argument to approve the HERMES proposal. The technology that will be used for chip embedding uses the top level of HDI printed circuit board (PCB) technology combined with a novel ultra fine line technology and a modified component assembly process. The combination of these technologies enables a breakthrough approach for new IC packages and complex high density modules for new 3D applications. This newsletter wants to provide the means for supporting the dialogue between the HERMES consortium and the industrial and research & development communities, which are active or interested in the field of chip embedding. In this first issue of the HERMES Newsletter we want to inform you about the general aspects and backgrounds of the project, the objectives, the possible applications, as well as on the background of the consortium partners. The following issues of the HERMES Newsletter will keep you informed on the progress made in the project, its intermediate results, new applications and market news. I. Why chip embedding? fered by the embedding technique. Components are located between the PCB conductor layers and not on top of the PCB and the contacting can be done from either side. The cost efficiency of the embedding technology at system level is finally the real benefit and enabler for the industrialisation. Standard materials and high-volume manufacturing equipment and robust processes will be used to manufacture this technology on a large production format. II. Objectives and aims The HERMES project wants to initiate a new mainstream packaging concept not bound by the existing supply chain, and by large-scale manufacturing technology. The project consortium will develop a technology for embedding active and passive components, allowing more functional integration and higher density. The technology will be based on PCB manufacturing and assembly practice, and on standard available silicon dies, highlighting fine pitch interconnection, high power capability and high frequency compatibility. Apart from research necessary for the technological advances towards fine pitch, new materials, multilevel stacking and high reliability, essential developments are needed for setting up an integrated manufacturing technology. Key issues are testability of the circuits during and after manufacturing, yield and cost of the processes, and the organisation of the supply chain. HERMES H E R M E S igh density integration by mbedding chips for educed size odules and lectronic ystems The aim of HERMES project is to develop the chip embedding technology and to set up the supply chain for its industrialisation. System miniaturisation, design flexibility and cost efficiency are amongst others essential benefits provided by HERMES. The development of the chip embedding technology has already a longer history and started with a funded project on chips in polymer in 2000 led by the Fraunhofer Institute IZM. The basic research & development work for chip embedding was done in the former STREP project Hiding Dies. The first functional demonstrators have been shown in this project and FhG-IZM patented a face-up embedding technology for chip embedding. With this experience of embedding passive discrete components and the increasing market interest FhG-IZM and AT&S saw a big opportunity in creating the supply chain for chip embedded applications in the frame of a European consortium. This consortium was willing to develop the chip embedding technology and the supply chain for the industrialisation of embedded applications. The partners of the consortium consist of end users, material suppliers, equipment and process suppliers, a silicon supplier, a test house, a PCB supplier and research institutes. It was also important to attract potential players, to create business power and to generate a move to chip embedding technology. Dissemination and exploitation of the technology has been a focus from the beginning of the HERMES project to prepare the market field. Arguments for embedding The embedding of active and passive components offers a wide range of benefits and potentials. System miniaturisation is one of the top priorities to use embedding technology which is most interesting for module applications. With additional space on the outer layers by moving the components to the inner layers more active and passive components can be placed on the same foot print. 3D system-in-package will be generated in that way with higher functionality and complexity. The improvement of the electrical performance of signals with short copper interconnections reduces parasitics compared to e.g. bonding structures leading to minimal signal distortions. High mechanical system stability, no soldering or bonding and highly reliable copper interconnections result in an improved all-over reliability which is a clear benefit of the embedding technology. One of the major challenges of high performance systems is an efficient thermal management in the modules. Copper via or other thermal structures can be contacted directly from the front or back side of the component. Design flexibility, especially for complex applications, is a further benefit that is of- III. Supply chain The embedding technology asks for a new organisation of the supply chain. The objective in the project is to set up the supply chain for the embedding technology. The HERMES consortium is organised in a supply chain to learn about the needs in building an efficient supply chain for an ongoing industrialisation process. Beside the consortium an Early Adopters Group and a Silicon Supplier Group have been installed. These groups of companies are important to get the necessary inputs for the build-up of an industrial supply chain and to develop it from the results gained in and outside the consortium. * External support of HERMES Figure 1: The HERMES supply chain A further important aspect is the setup of a generic yield and cost model based on the new technology and the new supply chain organisation and to compare it to those of more classic packaging concepts. The demonstration of the cost competitiveness of the embedding technology against existing packaging and assembly solutions will strongly influence the success and speed of the implementation. HERMES plays an important role in enabling new business in the European region. By forming a consortium with business potential partners it has the function of a spearhead for entering this new market of PCBs with embedded active and passive components. HERMES provides high tech technology for high I/O counts of complex silicon dies. During the development phase of the technology the output can be ta- The HERMES consortium is organised in a supply chain to learn about efficient process organisation for an ongoing industrialisation of the technology. HERMES will demonstrate the cost competitiveness against existing packaging and assembly solutions and will enable new business in Europe.

3 Products with embedded passives and actives with low pin count will be the first on the market to achieve customer acceptance and to gain field experience. ken to enable die embedding on a lower complexity. New potential customers for the technology level of HERMES will be convinced for the next step of embedding. It is important to prove the embedding technology on a lower risky level in the field before proceeding to the next step of HERMES. During the last year more than 2 new customers came in contact with the consortium and they are focussing now on the next steps with embedded technologies. results from the EAG. The EAG delivers input for test strategies and design rules with the objective to merge these data with the experience of the consortium and to start a standardisation process for embedded chip technology. The supply of different silicon dies for test vehicles and demonstrators is crucial for the manufacturing of the applications in HERMES and the EAG. Concerning the complex applications that are proposed it became obvious that several silicon houses will be needed to get the required silicon. The technology and designs used on the silicon will be quite different. This silicon will have different passivation layers which have to be compatible with the backend processes that are needed to adjust the design of the silicon die to the design rules needed for the embedding process. This adjustment of the design is done with a redistribution layer. These backend processes will be supported by FCI Flip Chip International, a US based company. An Early Adopters Group delivers valuable input for test strategies and design rules to standardise the process of chip embedding. V. Embedded applications in HERMES Technology IV. Building up the business Figure 2: HERMES the business enabler The exploitation activities for embedding technologies with discrete components have been started with a market analysis even before the HERMES project was started. We could see a rising interest from OEMs from different market segments for the embedding technology and that was the trigger to start the analysis. A so-called Business Focusing Project took place at AT&S in order to identify the scope for future chip embedding business activities alongside the HERMES project. The HERMES project aims at embedding active dies, face up or face down (flip chip), and (thin) passive components, inside the dielectric layers of a printed circuit board. The technology development within HERMES will concentrate on manufacturing an embedding technology for fine-pitch components (pitch 125 µm), and on high-end ultra-fine pitch components (pitch 60 µm) at research level. The technology development targets for production are 25µm line/spaces and 15µm at research level. These goals will be accomplished with parallel development of ultra thin 2µm copper foils with high etching rate, new plating chemistries and single board platers. By sequential building up the substrate, multiple levels of chip embedding can be achieved. The HERMES project targets 2 levels of embedding in volume production and 4 at prototype level. The HERMES project aims at embedding active dies, face up or face down (flip chip), and (thin) passive components, inside the dielectric layers of a PCB. Customer Needs over all Applications The goals were to: Industrialisation Development Identify customer needs, benefits and necessity for choosing embedding technology Map customer needs to possible applications and products Rate applications to create a priority list for market development Identify risk criteria for industrialisation and especially in regard of customer acceptance Risks over all Applications Figure 3: All over benefit and risk analysis for all customer applications of embedded technologies Basically, the process was designed in three parts: Data collecting, rating and filtering. Methods like market analysis, key customer contacts, creative techniques and rating with tools like portfolios have been used (see figure 3 to the left). The customer needs are important to understand and to rate the customer projects and identify the potential applications. When an analysis of the risk assessment is done in the early phase before industrialisation it is obvious that manufacturability is the biggest topic and design and supply chain issues have to be solved during the project. The entrance to the market is where the customer-pull starts. This is the field with highest business attractiveness and low technology complexity. Products with embedded passives and actives with low pin count will be the first on the market. These products will be the front runners to get customer acceptance and field experience. The Early Adopters and Silicon Suppliers Groups The HERMES consortium installed at the start of the project a so-called Early Adopters Group (EAG) with members as both users and producers of high density electronic systems. The EAG members have the intention to industrialise chip embedding applications during the HERMES project phase. The companies are benefiting from the development results that are implemented in their applications and the HERMES supply chain. On the other side the HERMES consortium benefits from the Figure 4: Development and industrialisation of chip embedding The final goal within the HERMES project is to set up an integrated manufacturing process that includes PCB processing and die assembly in one production line, in order to benefit the most from this combination (increased density, shorter routing, space for SMD ), without the difficulties of transport between production lines/ plants. HERMES applications The applications with embedded active components of HERMES are driven by the end-users Bosch, Thales and Infineon who are responsible for the product specifications and who are developing the design for manufacturability and the test concept with the other partners in the HERMES supply chain. The end-users are coming from different business fields automotive, communication and consumer. The product profiles are quite different and the chip embedding technology has to show its capability and competitiveness. Product reliability, miniaturisation and thermal performance improvement are the most important topics that have to be shown in the applications of the end-users. The end-users are coming from different business segments automotive, communication and consumer.

4 The HERMES project will put a lot of efforts to establish reliable design rules taking into account parameters such as die thickness and dimensions, relative positions and PCB build-up. Product reliability, a topic for all applications Embedding active dies and passive discrete chips deeply impacts the thermo-mechanical properties of the PCB which in turn affects the reliability of the components assembled on the board external sides. The HERMES project will put a lot of efforts to establish reliable design rules taking into account parameters such as die thickness and dimensions, relative positions and PCB build-up. The generic approach that will be used to address design rules is depicted on the following Figure 5. Figure 5: Schematic view of the thermo-mechanical modelling methodology used in HERMES A FEA (Finite Element Analysis) model will be developed to determine the board strain distribution. This model will rely on PCB base material properties which will fully issue from actual experimental measurements. TMA (Thermo-Mechanical Analysis) and DMA (Dynamic Mechanical Analysis) techniques will be used to precisely measure characteristics like coefficients of thermal expansion (CTE), Young modulus and visco-elastic moduli. An extensive test matrix comprising of 46 different PCB constructions has been defined to cover the various base material types, resin contents and thicknesses involved within the HERMES project. Most of the results are now available, in the process of being compiled and analysed. Chip embedding promises two advantages: Firstly, it is expected to reduce the complexity of the system by finding a more homogeneous solution, since only one packaging technology is used instead of two. Secondly, cost at least on the long run should be reduced by utilising high-volume PCB production facilities. It is the goal of HERMES to embed the power device(s) into the PCB according to Figure 7 and to place the application-specific logic devices and passives on top of the PCB. This concept provides high flexibility for the logic parts combined with a careful power removal design for the power devices embedded in the PCB and isolated from the heat sink according to the isolation specifications discussed above. The challenges for this solution are particularly great since in addition to the embedding process the high thermal conduction under electrical isolation has to be implemented. Mold compound Figure 7: Typical schematic sketch of power chip(s) embedded into the PCB and logic devices and passives mounted on top. Thales: Security communication Logic SMD device Power device (70 μm) Passive component PCB For power applications, chip embedding promises two advantages: reduced complexity of the system and minimised costs by utilising high-volume PCB production sites. Infineon: Power application The power module application is a particular challenge for the chip embedding technology to realise a power system, although a very promising one. Today, Control integrated Power Systems (CiPoS) as shown in Figure 6 are used as motor controls for variable speed drives in industrial applications such as washing machines and air conditioners. Parts of the system operate at voltages of 600 V and electric currents of 5-50 A, whereas other parts of the circuit operate at the moderate voltages and currents of state-of-the-art CMOS. For the existing solution Direct Copper Bonding (DCB) technology is used for the high-power part with a ceramic carrier and thick copper metallisation on both sides. The electrical isolation requirement is 2.0 kv over 1 min against the heat sink while effective thermal conduction is necessary to allow for a sufficient power loss. Power is redistributed by aluminium wires. This power part is controlled by an application specific logic part with driver IC, passive components and a lead-frame soldered on a PCB. Both parts are moulded together. External contacts are via Single Inline (SIL) or Dual Inline (DIL) connectors. DCB In summary, the proposed power module application combines complex redistribution for power and logic functions, high performance power interconnects and challenging thermal management. It is a complicated and costly solution. In the frame of the HERMES project, Thales Communications will develop a demonstrator to show the compatibility of the technology to implement a complex design, including large embedded dies simultaneously with SMD components. This implies the feasibility of processing such PCB with embedded active and passive components on a standard assembly line. The robustness of the process will be validated by embedding many dies coming from different suppliers. Once the chip-scale package is not sufficient in terms of integration, the HERMES technology provides a solution. In addition, to prove the ability of the technology to protect intellectual properties rights by embedding the confidential data and avoiding the cloning of electronic boards, the chosen application represent an AES (Advanced Encryption Standard) civilian crypto board, to demonstrate the capacity of the technology to offer a high security level at a low cost. Bosch: Motor management module This module uses the miniaturisation capabilities of the chip embedding technology to provide the ultra high density interconnection technology for complex silicon. The reliability requirement and the tractability requirement for the product and the process will challenge the development of this product. The driver for the development of this product is the growing number of control units in cars. Especially in the luxury class of cars the number of control units for comfort increased. Modularisation and miniaturisation are needed to implement all the new functions in the cars. For security communication, a demonstrator will be developed to show the compatibility of the technology to implement a complex design. For the development of a motor management module, miniaturisation capabilities are used to implement all the new functions in the cars. PCB Figure 6: Typical CiPOS module using both DCB and PCB technologies

5 The HERMES consortium The consortium of the HERMES Integrated Project is set up as a lean consortium. Participants have been selected based on proven background expertise in one or more of the areas or research proposed in HERMES. The HERMES project consortium consists of eleven European participants, coming from six different Member States of the European Union. AT&S has capabilities in manufacturing high density PCBs and knowledge on embedding technologies. The main contribution will be to provide the manufacturing technology for the realisation for the end-user applications. The most important processes which will be developed in HERMES are: Semi-additive process for ultra fine line technology for 25 µm line/space and below, and a high speed Chip assembly process for thinned dies. AT&S is the coordinator of the HERMES project. Atotech is the PCB plating specialist in the HERMES consortium. They will develop electroless and electrolytic copper plating technologies by utilising the experimental plating Single Board Plater concept. They will connect embedded chips by means of conformal plated or filled micro via with the surface wiring circuitry of the PCB layer. Bosch will primarily concentrate in the HERMES project on the evaluation of the feasibility of embedding technologies in automotive applications. In the HERMES project Bosch will provide the special requirements for automotive products and verify the benefit of embedding technologies on the basis of near-series demonstrators. Circuit Foil is the copper foil manufacturer in the HERMES project and will develop a 2µ ultra-thin copper foil. This copper foil is the base for the development of a modified semi-additive technology IMEC, as a research institute will mostly concentrate on advanced technology developments. IMEC will also lead or participate in supporting tasks with a more generic character: DfX guidelines, design of test vehicles, test methodologies. Finally IMEC is well placed for dissemination at R&D level. Infineon will primarily concentrate on the preparation issues of the wafers/chips for embedding into the PCB. Large co-operation with the other HERMES beneficiaries is necessary in this context for achieving a high-yield and low-cost embedding solution. The specific interest of Infineon in this project is on the Control Integrated Power System (CiPOS), an industrial control system for refrigerators and air conditioners which contains power and logic chips. FhG-IZM will be primarily responsible for the development of the ultra-fine line technology and for the chip surface adhesion research activities. Through their large expertise in the field they are well placed to take the lead of the main work package activity on Embedding technologies. This work package is at the core of the research and development work within the HERMES project. Rood Testhouse is the test specialist within the project. Their role will be to develop the test methodology for embedded components. They will also be responsible for die testing and for functional test validation of the different end-user technology validation demonstrators. Siemens Electronics Assembly Systems is responsible for the development of the large panel die assembly equipment. This is also a very unique position in the whole HERMES consortium. Thales Communications will primarily concentrate on the evaluation of the proposed technology for its different product lines. In the HERMES project Thales Communications will bring in the special requirements for aerospace and security products and verify the benefit of embedding technologies on a dedicated security demonstrator. Thales Corporate Services will concentrate its efforts on its main background based on technologies and process knowledge, as well as design and reliability expertise. As leader of the Modelling and Reliability work package in HERMES, Thales CS will coordinate and manage the modelling and simulation activities of the various involved beneficiaries. Contact Project Coordinator: Johannes Stahr AT&S Austria Technologie & Systemtechnik AG Fabriksgasse 13, 8700 Leoben, Austria Tel.: h.stahr@ats.net