INSIGHT SiP. RF System in Package, design methodology and practical examples of highly integrated systems
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1 INSIGHT SiP RF System in Package, design methodology and practical examples of highly integrated systems Chris Barratt Insight SiP Sophia Antipolis France 1
2 RF SiP Technologies PRD Design Methodology Initial Design Phase Detailed Design Phase Examples Bluetooth Modules WLAN Module Substrate Tool Box Integrated IQ mixer 2
3 RF SYSTEM in PACKAGE Complete 3D RF system Including RF semi-conductors Base-band semi-conductors SMT passives Buried RF passives Interface to application PCB (LGA, BGA) Fully self contained system Tested Form of a standard semiconductor package 3
4 ROLE OF SiP IN LIFE CYCLE Time to Market in Months Design cost à x x x SiP 10 x 10 mm 3.5 x SiP 5 x 5 mm SoC 3.5 x 3.5 mm 12 à 18 1 st level of Integration on PCB 30 x 30 mm 6 à 12 Prototypes 50 x 50 mm (Bluetooth Model) Design Complexity Level of integration Size reduction 4
5 RF SiP Substrate Technologies Laminate based (ε r 3 5) 4 to 6 metal layers Interco. RF Baluns in substrate LTCC based (ε r 7 10) 6 to 20 metal layers Interco. RF baluns, Filters, matching in substrate Silicon Based (ε r 11.2) 2 to 4 metal layers + doping Interco. RF baluns, Filters, matching and high C in substrate 5
6 RF SiP Design Objective Design for manufacture - highly integrated custom (RF) systems and sub-systems Based on System in a Package (SiP) approach Multi-technologies : PCB, LTCC, Thin film, Thick film Emphasis on optimum overall cost in production Use of mature non proprietary technologies available on the open market Initial Design & Feasibility Determine tradeoffs Select technology platform Determine system partitioning Detail Design Create and optimize schematic Generate and validate layout and assembly Build and validate prototypes Optimize the technology choices for size, cost and time to market 6
7 INSIGHT PRD Initial Design & Feasibility Objective : choose the Best Architecture to Optimise Performances according to the Market Requirement, Production and Development Costs, Design to Production Lead Time. Method : System partition Semiconductor Technology Choice : Si, GaAs, SiGe, SiP Technology Choice : Laminate, LTCC, Silicon Based SiP Assembly options (Flip-chip vs Bond-wires) Buried passives vs Si passives vs SMT Compare SiP substrates Size, Cost, NRE Compare Assembly options Wire-bonding, Flip-chip, RDL, bumping, SMT, Compare test options 7
8 INSIGHT PRD 8
9 INSIGHT PRD 9
10 INSIGHT PRD 10
11 INSIGHT PRD SiP Substrate Comparison Size & Performances Cost & Time to Production 11
12 INSIGHT PRD Step 2 System Design Partition Functions Die, SMT, Substrate Detailed Design of Buried Functions Layout Complete SiP Integrate all Functions Measure Buried Functions Adjust BoM Test Complete SiP N OK? Production Electrical Schematic Optimise Choose Layer Structure Generate Parametric Mechanical Objects EM simulate Parametric Objects Optimise Circuit with Parametric Objects Auto generate 3D layout Full EM simulation of 3D layout Y OK? N Standard EDA software based. Flexible process with no fixed libraries for each substrate Step-by-step Process System model development Project-specific component library Optimise Layout Circuit Optimization taking interactions into account Exhaustive simulation of electromagnetic behavior Performance Optimization through electro-magnetic simulation feedback to circuit model. Proven two-pass success (with one-pass objective) 12
13 INSIGHT PRD Step 2 S Parameters Active Circuits Parametrical/Mechanical Objects S Parameters For Each Object Circuit Simulation, ADS, Designer, EM/Circuit Simulation, ADS, Designer, HFSS, CTS Layout/EM ADS, Cadence, Designer, Circuit Design L, C, Balun Buried Function Design Layout Design SiP Final Test Test of Buried Functions Substrate Manufacturing Multi-layers / Thin Film 13
14 FLOW FOR BURIED FUNCTIONS Electrical Schematic L One pass success Choose Layer Structure Generate Parametric Mechanical Objects Optimise Circuit with Mechanical Parameters Auto Layout Generation EM Check Layout C1 Y C2 X X L S(X,Y) Parameters X,Y TL 1 TL 2 TL 3 TL 4 X C1 X C2 Optimise Layout OK X L XC2 X C1 14
15 UWB FILTER EXAMPLE Specification Paremeter IL Units db Spec < 4 Comments 3.2 to 4.7 GHz RL db > to 4.7 GHz Rej WLAN b/j db >20 2 to 2.6 GHz Initial Circuit Idea Rej WLAN a db > to 6 GHz Num=1 Z=50 Ohm Z=Zs Ohm E=Es Z=Zs1 Ohm E=Es1 Z=Zs Ohm E=Es Z=Zs1 Ohm E=Es1 Z=Zp Ohm E=Ep Z=Zint Ohm E=Eint Z=Zs2 Ohm E=Es2 Z=Zs3 Ohm E=Es3 Z=Zs2 Ohm E=Es2 Z=Zs3 Ohm E=Es3 Z=Zp1 Ohm E=Ep1 Z=Zint1 Ohm E=Eint1 Z=Zs4 Ohm E=Es4 Z=Zs5 Ohm E=Es5 Z=Zs4 Ohm E=Es4 Z=Zs5 Ohm E=Es5 Z=Zp2 Ohm E=Ep2 Optimised Filter Response Num=2 Z=50 Ohm 0 S21 < -20dB GHz S11 < -20 db S GHz db(s(1,1)) db(s(2,1)) freq, GHz < -20 db GHz 15
16 L3000 to 7500 um L3000 to 7500 um L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 L3000 to 7500 um L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 L3000 to 7500 um L3000 to 7500 um 1 2 RF SiP UWB FILTER EXAMPLE Generate Parametric Objects using EM simulator Schematic Layout L3000 to 7500 um 1 2 Optimize Circuit with Parametric Objects W=W L=L W=W L=L W=W2 L=L2 W=W2 L=L2 W=W4 L=L4 W=W4 L=L4 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 W=Wint L=Lint L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 W=Wint1 L=Lint1 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 W=W1 L=L1 W=W1 L=L1 W=W3 L=L3 W=W3 L=L3 W=W5 L=L5 W=W5 L=L5 Num=1 Z=50 Ohm W=Wp L=Lp L3000 to 7500 um 2 W=Wp1 L=Lp1 L3000 to 7500 um 2 W=Wp L=Lp Num=2 Z=50 Ohm 16
17 UWB FILTER EXAMPLE Auto-generate Layout Simulate layout Optimise to lock performance S21 < -20dB GHz S11 < -20 db S21 db(s(1,1)) db(s(2,1)) GHz < -20 db GHz freq, GHz 17
18 Bluetooth Module 0-20 db(s(2,1)) freq, GHz 18
19 WLAN Module - NANORADIO Full WLAN capability bg Digital to Antenna 8 x 8 x 1.4 mm size Ultra low power modes 19
20 WLAN Module - NANORADIO 20
21 Substrate Tool Box 21
22 IQ Mixer ATLANTIC RF/NXP 3D high-density capacitors 22
23 RF SiP Technologies PRD Design Methodology Initial Design Phase Detailed Design Phase Examples of RF SiP Bluetooth Modules WLAN Module Integrated IQ mixer 23
24 ACKNOWLEDGEMENTS NANORADIO NRG723 WLAN Module ATLANTIC RF - IQ Mixer NXP Use of Silicon based PICS technology INSIGHT SIP
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