3D Integration developments & manufacturing CEA-LETI. D. Henry CEA-Leti-Minatec

Transcription

1 3D Integration developments & manufacturing CEA-LETI D. Henry CEA-Leti-Minatec

2 Outline Introduction 3D Integration R&D activities overview 3D integration Manufacturing offer : Open 3D platform Concept Technological offer Means & facilities Conclusions / prospects 2

3 CEA The CEA at a glance LETI at a glance Commissariat à l Énergie Atomique et aux Énergies Alternatives is one of the largest research organizations in Europe, focused on energy, health, information technologies, and national defense 16, People (10% PhD and Post Doc) Research centers Founded in 1967 as part of CEA 1,700 researchers 190 PhD students + 34 post PhD with 70 foreign students (30%) Over 1,700 patents 265 generated in % under license 210 M budget ~ 40M CapEx CEO Dr. Laurent Malier 40 start-ups & 265 industrial partners 3

4 Introduction : What is 3D Integration? In electronics, a 3D integrated circuit is a chip in which two or more layers of active electronic components are integrated vertically into a single circuit, component or system. 3D Integration key drivers : Form factor decrease Performances improvement Heterogeneous integration Cost decrease Interposer / substrate passives Memory Logic 4

5 Introduction : 3D Integration hierarchy 4 different worlds in 3D Integration : 3D name 3D SiP or 3D packaging 3D WLP (wafer level packaging) 3D SIC (Stacked IC) 3D Monolithic (or 3D IC) Global / Intermediate Local Schematic view Interconnect level Package Bond pad Pad size (µm) > Supply chain OSAT Packaging subcon. WL pack. Cie OSAT IDM IDM Foundries IDM Foundries PoP / SiP / C2C Wire bond / FC C2W /TSV last / Interconnections C2W / W2W TSV last & first/ Direct bonding Low temp IC Key Techno approaches 5

6 Main actors of 3D Integration / Geo mapping 3 main areas : North America Europe Far east Source : Yole developement 6

7 Outline Introduction 3D Integration R&D activities overview 3D integration Manufacturing offer : Open 3D platform Concept Technological offer Means & facilities Conclusions / prospects 7

8 3D LETI : 3 research axes Substrate evolution Advanced SOI substrates for More Moore More than silicon: Add new materials compatible with silicon technologies 3D IC evolution Solve memory logic bandwidth equation Mix different nodes to reduce the cost Compensate Moore law s difficulties 3D Packaging evolution: Si Interposer Design Design (r)evolution (r)evolution Fill the gap between advanced IC and Plastic Integrate heavy functions as near as possible from IC (Passives, Thermal management, ) 8

9 3D LETI : 3 research axes Substrate evolution Advanced SOI substrates for More Moore More than silicon: Add new materials compatible with silicon technologies 3D IC evolution Solve memory logic bandwidth equation Mix different nodes to reduce the cost Compensate Moore law s difficulties A common generic toolbox 3D Packaging evolution: Si Interposer Design Design (r)evolution (r)evolution Fill the gap between advanced IC and Plastic Integrate heavy functions as near as possible from IC (Passives, Thermal management, ) 9

10 Mode ling LETI toolbox for 3D Integration Thermo mechanical & thermal Modeling CSi COx G Si Electrical Modeling C Si R COx L G Si C EA-Leti Design layout TX-BIT + NoC perf 3D implementation & partitionning SME EXT NoC n ode S ME Mep histo T RX OFDM TR X OFDM ARM117 6 ARM1176 CORE S ME + SM E Mep histo unit TRX OFD M TRX OFDM SM E Meph isto 80C51 UW B-LDPC Mep hist o M ephisto SME RX-B IT + HARQ AS IP GALS adapt er W IFL E X Ch1 North Ch1 South Ch1 East Ch1 West Ch1 3D/Res Standard Design rules manuel & Design kit Ch0 North Ch0 South Ch0 East Ch0 West Ch0 3D/ Res Ch 1 5x5 router Ch 0 5x5 rout er Ch1 North Ch1 South Ch1 East Ch1 West Ch1 3D/Res Ch0 North Ch0 South Ch0 East Ch0 West Ch0 3D/Res Layout & masks Indust. / Mfg Components placement (WTW or CTW) Face to Face connections Through Silicon Via (TSV) atio t n Redistribution layers and Board connections se e r s p y a To d Reliability us c o nf Kelvin 5µm Re f 10-Re f Re f 12-Re f Re f % Technological modules Thinning & Handling 14-Re f SLE SLE 17-SLE 0 0 0,1 0,2 0,3 0,4 Resistance [W ] 0,5 Test strategy Cost analysis 10

11 Toolbox : Temporary bonding / Thinning/handling Process flow summary Device Temporary bonding 3D techno Debonding / handling / Stacking Source : A. Jouve / Brewer Science / 3D IC 2009 EVG 560 bonder Wafer bonded with temp. glue Debonded wafer (70 µm) Debonder EVG

12 Toolbox: Face to Face connection Well-established process Cu pillars Classic Flip chip (Ball or stud bump) Disruptive concepts Si µtubes Si Solder-free µ-inserts > 100 µm Cu Cu-Cu Direct bonding µm range µm range SiO2 Down to 5 µm Pitch 12

13 Toolbox : TSV TSV First (Polysilicon filled) Trench AR 20, 5x100µm TSV Middle (Copper or W filled) AR 7, 2 x 15µm TSV Last (Copper liner or filled) mét al RDL W filled 60µ m S i O 2 fl a n c B C B bulle air sous BCB AR 10, 10x100µm AR 1 80x80µm AR 2, 60x120µm AR 3, 40x120µm AR 7, 2 x 15µm 13

14 3D Integration : applications examples Substrate evolution Advanced SOI substrates for More Moore More than silicon: Add new materials compatible with silicon technologies 3D IC evolution Solve memory logic bandwidth equation Mix different nodes to reduce the cost Compensate Moore law s difficulties 3D Packaging evolution Design Design (r)evolution (r)evolution Fill the gap between advanced IC and Plastic Integrate heavy functions as near as possible from IC (Passives, Thermal management, ) 14

15 Leti Interposer Technology Component partitioning Advanced technology top die Mature technology Bottom die Die to Die Copper pillar Thinned wafer (120 µm) Cu Pillars Top Die TSV Silicon Interposer Substrate or Via Mid Via Last (Aspect Ratio 2-3) ViaTSV Last Die to substrate copper pillars 15

16 Leti Interposer Technology High Density Interposer Advanced components top dies High density routing Micro bump Metal line + via Metal line Top metal line Debonded wafer on tape Seed layer deposition 16

17 3D Integration : applications examples Substrate evolution Advanced SOI substrates for More Moore More than silicon: Add new materials compatible with silicon technologies 3D IC evolution Solve memory logic bandwidth equation Mix different nodes to reduce the cost Compensate Moore law s difficulties 3D Packaging evolution Design Design (r)evolution (r)evolution Fill the gap between advanced IC and Plastic Integrate heavy functions as near as possible from IC (Passives, Thermal management, ) 17

18 Cmos on Cmos Integration Cu Pillars 3D Partitioning demonstration Analogue Analogue/ Digital partitioning 65nm node, 7 metal layers + TSV Digital 65nm 80µm Cu Pillars VFBGA, 4x4mm 25µm wide, 30µm high Pourcentage cumulé (%) TSV 100 P01_2TSV P02_2TSV P01_10TSV P02_10TSV P01_50TSV P02_50TSV ,0 0,5 1,0 1,5 2,0 2,5 3,0 R ( ) TSV s Via Middle, Ø10µm x 80µm, 40µm pitch. Cumulated resistance of a 2, 10 & 50 TSV daisy chains 1st wafer 80% yield 18

19 Multi-Stacking, N>2 Copper Pillars Via middle NAND Flash Memories Via middle: ~Ø12µm x 60µm Cu pillar interconnections 12µm Mem4 Mem3 Mem2 Mem1 60µm Top Die 60µm Bottom Die 60µm Bottom Die Substrate Die Multi-partner project 19

20 Outline Introduction 3D Integration R&D activities overview 3D integration Manufacturing offer : Open 3D platform Concept Technological offer Means & facilities Conclusions / prospects 20

21 Introduction to Open 3D Platform The concept : Open 3D is a 3D technology offer, targeting industrial & academic customers Open 3D will give access to 3D innovative technologies with the following key drivers : Cost effective technologies : Based on mature technologies Customization upon request Short cycle time Global offer including design, technology, tests & packaging Proof of concept (small quantity of wafers) or small volume production Means & Facilities : Open 3D will operate on CEA-LETI technological platforms : 200 & 300 mm Support by LETI skills on layout, process, metrology, charac., tests & reliability Open 3D customer s typology : Laboratories, universities and international Institutions Fabless / Niche markets manufacturers & integrators IDM Projects already started with : 21

22 Technological offer overview Technological modules definitions : Through Silicon via (TSV) Redistribution layer (RDL) UBM Interconnections Components stacking Packaging with partner collaboration Top die Front side UBM Micro-bumps Micro pillars Bottom die or interposer RDL Back side UBM TSV Passivation Bumps Pillars Substrate or BGA or package 22

23 Technological offer overview Design & Layout 3D Technology TSV Open 3D TechBox Packaging As a Lego approach Electrical Tests Interconnections Metalization 100,00% 90,00% 80,00% P02 P03 P05 P06 P07 P08 P09 P10 P11 P12 70,00% 60,00% 50,00% 40,00% 30,00% 20,00% 10,00% 0,00% 0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50 4,00 Components stacking Contact : OPEN_3D@cea.fr 23

24 Technological offer in details : 3D design & layout 0pen 3D design approach Complete Design Rules Manual (DRM) Implementation of customer design 3D Design kit (DK) Layout capabilities / Verifications Cadence Virtuoso tool Mentor graphics Calibre tool Mask generation 3D DRM & DK Open 3D PDK Generator Techno Customer Techno Léti Design rules for Micro-bumps & RDL Customer DRM L éti DRM Customer PDK Léti PDK Customer Layout & verifications Design 24

25 Technological offer in details : TSV + RDL TSV & RDL DRM & schematic Wafer size : TSV type : Minimum pitch : TSV diameter : Aspect Ratio (AR) : 200 & 300 mm via last / Cu liner 80 µm 30 to 100 µm from 1:1 to 3:1 RDL material : RDL thickness : RDL minimun width : RDL minimun space : Cu / protective layer possible 1-10 µm 20 µm 20 µm Customer Top metal Customer Top passivation Customer Metal 1 TSV Dielectric liner CMOS Wafer 1 TSV Metal liner Bulk contact RDL Backside UBM Backside Passivation TSV & RDL morphological results AR 2:1 Cu RDL integration : pillars on RDL + passivation Solder bump AR 1:1 AR 3:1 RDL 25

26 Technological offer in details : TSV gallery TSV diameter 30 µm 40 µm 50 µm 60 µm AR 1:1 & 1.5:1 Not yet demonstrated Available Not yet required AR 2:1 Not yet demonstrated Available Not yet required Not yet demonstrated AR 3:1 26

27 Technological offer in details : Under bump metallurgy (UBM) UBM DRM & schematic Frontside ubm Customer Top passivation Wafer size : 200 & 300 mm UBM material : TiNiAu Possible on frontside and / or backside of the components UBM thickness : µm UBM width : µm UBM minimun pitch : 40 µm Customer Top metal CMOS Wafer 1/ Bot. die Wafer 2/ Top die CMOS Customer Top metal Customer Top passivation Backside ubm UBM morphological results Available technology : AR 2:1 - Metal sputtering / thickness range : µm Different shape possible : - Square - Polygons - Circle 27

28 Technological offer in details : Micro bumps & micro pillars Micro bumps & micro pillars DRM & schematic Wafer size : Micro-bumps material : Micro pillar material : possible Minimum pitch : Micro-bumps diameter : Micro pillars diameter : Micro-bumps thickness : Micro pillars thickness : Wafer 2/ Top die CMO S 200 & 300 mm Cu post / SnAg solder Cu post / NiAu protection Micro pillar Cu stud Solder alloy Protective layer 50 µm 25 µm 25 µm µm 8 12 µm Customer Top metal Top passivation Micro bump Cu stud Customer Top passivation Customer Top metal CMOS Wafer 1/ Bot. die Micro bumps & micro pillars morphological results Micro-bumps characterization Micro pillars on top metal Micro-bumps after reflow Micro pillars with protective layer 28

29 Technological offer in details : bumps & pillars Bumps & pillars DRM & schematic Wafer size : Pillars material : Minimum pitch : Pillars diameter : Pillars thickness : Customer Top metal Customer Metal & 300 mm Cu stud / SnAg solder 120 µm µm µm TSV CMOS RDL Backside Passivation Cu stud Bumps Solder alloy Bumps & pillars morphological results Bumps cross section Solder bump Bumps TSV Pillars integration with TSV 29

30 Technological offer in details : 3D electrical tests Electrical test approach Electrical tests at each level Specific structures for 3D technologies Non invasive structures into dicing lines Using of Standard probe cards Data exploitation tool Electrical test results & tools 100,00% 90,00% 80,00% P02 P03 P05 P06 P07 P08 P09 P10 P11 P12 70,00% 60,00% 50,00% Probe card 40,00% 30,00% 20,00% Electrical test results 10,00% 0,00% 0,00 3D tests structures 0,50 1,00 1,50 2,00 2,50 3,00 3,50 4,00 Electrical test tool 30

31 Outline Introduction 3D Integration R&D activities overview 3D integration Manufacturing offer : Open 3D platform Concept Technological offer Means & facilities Conclusions / prospects 31

32 Technological Minatec campus General overview of LETI s MINATEC campus Nanotech D 300 ms r o CMOS 200 mm tf pla D 3 MEMS 200 en p O Design / layout Nanoscale Characterization B2i / applications building Microtech for biology Photonics 32

33 MEMS 200 pilot line MEMS 200 tools Litho cluster Metal deposition Litho In line Metrology MEMS 200 buildings & facilities Litho MEMS 200 CMP Pilot Line Cleanrooms Cleanrooms Raider ECD Mobile cleanroom between platforms Dry Metal etching Litho Cleaning Metal etching Stripping / Cleaning 33

34 New 3D 300 pilot line (fully operationnal 2012) 3D 300 future installation tools Complete line for Q Reflow Balling / Screen print. 3D 300 installed base Wet etch Stripping Coater Deep etchnig Vacuum laminator 3D 300 Pilot Line Mask Aligner Diel. Deposition Edge grinding ECD 2 Dry film laminator Cleaning / deconta Bonder Pick & place Metal deposition ECD 1 Grinding 34

35 Conclusions / Prospects Conclusions : Since 20 years, LETI has worked on 3D integration An original approach, based on a technological toolbox, has been developed Industrial transfers & technological demonstrations have been achieved since few years Now, a new platform, Open 3D, is proposed by LETI for academic & industrial partners with the following key drivers : Cost effective / mature technologies Short cycle time Global offer including design, technology, test & packaging Operations on LETI Minatec campus / Grenoble France Proof of concept or small volume Already two projects have started on the platform 3D integration prospects : To continue the R&D projects in order to develop disruptive 3D technologies To continue to fill the Open 3D catalog with mature technologies in accordance with our customer needs 35

36 Thank you for your attention