MEMS Processes at CMP

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1 MEMS Processes at CMP MEMS Processes Bulk Micromachining MUMPs from MEMSCAP Teledyne DALSA MIDIS Micralyne MicraGEM-Si CEA/LETI Photonic Si-310 PHMP2M 2

2 Bulk micromachining on CMOS Compatible with electronics Front side bulk micromachining ams 0.35µ CMOS, SiGe, High Voltage Suspended passive device MPW run turnaround: 8/10 Weeks Post process turnaround: 5 weeks 3

3 Compatible with electronics Front side bulk micromachining ams 0.8µ BiCMOS Anisotropic Etching without additional mask Bulk micromachining on BiCMOS Suspended passive device Cross section Suspended beams 4

4 Bulk micromachining designs Front end electronics close to MEMS sensor for better signal to noise ratio Test sensor structures Fondazione Bruno Kessler MPW A35C11_5 Thermal inertial sensor LIRMM MPW A35C11_6 MEMs accelerometer and signal conditioning MPW A35C14_5 5

5 Backside bulk micromachining Backside bulk micromachining Integration of MEMS sensor and front end electronics A CMOS Compatible Ultrasonic Transducer Fabricated With Deep Reactive Ion Etching Libor Rufer, Christian C. Domingues, Salvador Mir, Valérie Petrini, Jean Claude Jeannot, and Patrick Delobelle JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 15, NO. 6, DECEMBER 2006 Membrane and suspend structure on top of cavity Applications: piezoresistive devices, pressure sensors, transducers Discussions ongoing to provide such MEMS process along with ams 0.35 µ CMOS 6

6 Access to bulk micromachining Design Kit Standard DK for the 0.35µ CMOS process C35B4C3 from ams Design Rule Manual and technology files provided for MEMS structures MEMS DK for: Fabrication schedule ams C35B4C3: next run starts on January 30th Price list 650 /mm² (4.49 mm² mini) for 10 chips 7

7 MEMSCAP Company created in 1997, technology available through CMP since different processes: PolyMUMPs SOIMUMPs PiezoMUMPs 8

8 PolyMUMPs Features 2 mechanical and 1 electrical layer of polysilicon 2 sacrificial layers 1 electrical conduction layer 1 electrical isolation layer Optional post process: etching/release, CO2 drying, sawing Applications Acoustics (microphones) Accelerometers Micro fluidics Display Technologies POLY 2 9

9 SOIMUMPs Features Silicon On Insulator substrate Reactive Ion Etching (RIE) 10 to 25 µm structural layer 2 Metal layers Applications Gyros Optical devices Display technology METAL Si OXYDE Substrate Cross section of RIE etching 10

10 PiezoMUMPs Features Based on SOIMUMPs process 0.5 µm Aluminium Nitride piezoelectric layer Active piezoelectric device 2 Metal layers Applications Energy harvesting Ultrasonic transducers Microphones Actuators 11

11 Access to MUMPs Design kits and CAD tools Physical design, DRC: Specific MEMS CAD tools: Fabrication Schedule PolyMUMPs: 4 runs in 2017 SOIMUMPs: 3 runs in 2017 PiezoMUMPs: 3 runs in 2017 Price list 1 PolyMUMPs: / (added cost for optional post process) SOIMUMPs: / PiezoMUMPs: / : for 15 identical chips 1cmx1cm fixed size except for SOIMUMPs 0,9x0,9cm 2: price for Educational Institutions and Research Laboratories 3: price for Industrial Companies 12

12 Teledyne DALSA MIDIS platform MEMS Integrated Design for Inertial Sensors (MIDIS ) Features Getter free high vacuum sealing allows resonator Q factors > 20,000 Efficient wafer level packaging minimizes overall die size 1.5 μm feature size in a 30 μm thick membrane Comb height control allows out of plane sensing TSV allows compact design ready for co packaging Applications Accelerometers Gyroscopes Resonators Inertial sensor combos (Sensor fusion) Inertial sensor Courtesy of CMC 13

13 Teledyne DALSA MIDIS platform Picture from CMC 14

14 Teledyne DALSA MIDIS platform Cross section of Typical MIDIS process Picture from CMC 15

15 Access to MIDIS Process Design Kit from Teledyne DALSA Process parameters specifications Design rules DRC deck Technology files for solid model generation MIDIS solid model generation Offers a truly representative 3D view of your design Ready for design review Multi physics simulations Fabrication schedule 1 runs scheduled for 2017 (1 st run March 10 th /devices shipment 1 st October) Price list / per 4x4mm minimum for 40 chips 1: price for Educational Institutions and Research Laboratories / Industrial 16

16 Micralyne MicraGEM Si process MicraGEM Si Platform MicraGEM SiTM technology based on a Silicon on insulator (SOI) MEMS process features two thick SOI structure layers and gold metallization on the top surface, enabling the design of vertical comb drive actuators along with optically flat silicon surface. Target applications include variable optical attenuators (VOA) and wavelength selective switch (WSS) modules as well as resonators and bio sensors. Horizontal comb drives can also be created for use in inertial sensors. Picture from CMC Picture from CMC Academic Price: / (4mm x 4mm) Fixed size 1: price for Educational Institutions and Research Laboratories / Industrial 17

17 CEA/LETI Photonic Si 310 PHMP2M Photonic Si 310 PHMP2M Silicon film 310 +/ 10nm HR BOX 800nm 200mm CMOS platform Tungsten plugs (vias) 2 Metal layers (MET1 and Alucap) Passive & Active components Very high performance building blocks (λ=1.31µm and later λ=1.55µm) Black boxes and PCells Rib Wave guide Deep Rib Wave guide 18

18 Packaging Compatibility Open 3D process CMP Interposer Tindal packaging Applications Telecom DataCom ComputerCom CEA/LETI Photonic Si 310 PHMP2M Our offer 2 MPW runs/year: next run in March 2017 Starting Price: 1600 /mm² for 25 samples 3D Post process option available Supported PDKs: Cadence, Mentor (Pyxis), Phoenix software (in development) 19

19 Realization Examples CEA/LETI Photonic Si 310 PHMP2M Optical Receptors 1D Fiber coupler 2D Fiber coupler Rib Waveguide GE PIN Diode 20

20 Thank you!

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