New fabrication and packaging technologies for CMOS pixel sensors: closing gap between hybrid and monolithic

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1 New fabrication and packaging technologies for CMOS pixel sensors: closing gap between hybrid and monolithic Outline Short history of MAPS development at IPHC Results from TowerJazz CIS test sensor Ultra-thin chip embedding in plastics Coming CMOS process: thick, fully depleted substrate Conclusions and prospects 1

2 Monolithic Active Pixel Sensor: effective use of a thin epitaxial layer (10 20 µm) for MIP tracking R.T. May be extremely thin (~25 µm of silicon in total, ~0.027 % X 0 ), flexible (!) and still fully efficient for MIP tracking! 2

3 Some break points in MAPS development at IPHC (Mimosa sensors series) - M1: first CMOS MIP tracker (2000) - M5: first large area device (2003) - M8, M16, M22: binary readout ( ) - M25: high-res, semi-depleted epi (2008) - M26, M28: first applications in physics (EUDET, STAR) ( ) 3

4 Recent evolution of fabrication process: TOWERjazz CIS µm CMOS - 18 µm thick, > 1 kω cm epi layer - Quadruple well process NMOS PMOS Pwell Nwell Pwell Nwell Pwell Deep (Burried) Pwell P - epitaxy P ++ substrate Wafer Cross Section 4

5 Layout of test pixel (SF readout + two inverter cells): study of influence of parasitic Nwells (screened by Deep Pwell) on charge collection Deep Pwell Parasitic Nwells Charge collecting Nwell 5

6 Charge collection test results (120 GeV pions beam) Combined irradiation: n/cm Mrad (Xrays) Standard SF pixel Test SF pixel (Deep Pwell) Before irradiation After irradiation Almost negligible difference between the standard and the test pixel! 6

7 Charge collection study (beam tests) Charge (electrons) vs. cluster size Cluster multiplicity distribution before (left) and after (right) combined irradiation Other tracking parameters (after combined irradiation, at 15 C) SNR seed > 25 ε tracking > 99.5 % σ x,y < 2 µm Fully satisfactory for ALICE ITS upgrade expected in coming years! 7

8 Study of charge collection using Fe 55 photons (laboratory) Seed pixel Cluster 2*2 Calibration peak Fe55 (5,9 kev) 8

9 Study of charge collection using Fe 55 photons (laboratory) P1: standard pixel, P9 : test pixel (Deep Pwell) CCE vs. neutron fluence ENC vs. neutron fluence Rather small changes up to 3*10 13 n/cm 2, requires more neutrons to see the limit 9

10 First real scale exercise of large system based on MAPS: new STAR Microvertex Detector Data taking (1/4 of detector) expected in 2013, full detector installation in 2014 Estimated 0.37% X 0 /ladder. Can we do better? 10

11 PLUME concept: double-sided ladder (ILC compatible) - 2x6 Mimosa26 sensors thinned down to 50 µm - Standard double-side kapton PCB: Cu conductor (20 µm/layer) - SiC foam (8%) for spacer between layers - Estimated 0.6 % X 0 /two sensor layers 11

12 Novel approach for ultra thin sensor packaging: use of a standard flex PCB process for chip embedding in plastic foils (IPHC/CERN CERNVIETTE Project, Rui de Oliveira, Serge Ferry) Sensor gluing between two kapton foils (22 kg/cm2, 200 C, vaccum) Opening vias using lithography. Kapton chemical etching (ethylene diamine) + plasma etching of epoxy Metallization: Al (5-10 µm) Lithography to pattern metal. Chemical etching (phosphoric acid) Single module: intermediate tests Complete ladder assembling, laser cut along sensor edges Gluing of another kapton foil for deposition of second metal layer Laser cut along sensor edges Soldering of connector and discrete components 12

13 CERNVIETTE: stack formation (during processing, before copper substrate dissolution) ~150 µm Polyimide, 50 µm Polyimide, µm Polyimide Silicon chip Acrylic glue Polyimide Acrylic glue Copper substrate 1.5mm Aluminum (5 to 10 µm) Thin layer of epoxy glue (3 to 10 µm) acrylic glue 50 µm Impedance of readout lines (last metal, 100 µm width, 100 µm gap) as a function of kapton thickness: 100 Ω for 60 µm thick kapton (last layer) 13

14 CERNVIETTE in pictures Solid state flexible sensor wrapped over cylindrical shape (R=20 mm) Metal1-bonding pads vias Finished two-metal layer flex (one sensor) with mounted discrete components (capacitors and connector) Next step: full ladder built with six M26 sensors (4 kapton/aluminum layers) 14

15 Some problems in the first iteration: too short plasma etching of glue layer, no electrical contacts But excellent metal adhesion and thickness uniformity! Corrected in the second iteration! Processing would be far easier if the first redistribution metal layer implemented already in the CMOS foundry (top metal)! 15

16 Future technologies for MAPS: perspectives of fabless CMOS foundries Principle: process developed and owned by company at TCAD level, available for external users as a standard MPW or engineering runs. Fabrication is subcontracted at real silicon foundry, post processing (if needed) included. All transparent to users, for a highly specialized structures and comparable costs Example: ESPROS Photonics Corporation (EPC) in Switzerland 16

17 ESPROS CMOS (+CCD!) process (150 nm) Detector grade, n-type, fully depleted 50 µm thick bulk silicon + deep p-implant to separate transistor level + backside processing No restrictions for use of both PMOS and NMOS in pixels 17

18 Sample of measured performance of ESPROS IR sensors (waiting for our own prototypes to be submitted soon ) 18

19 Possible scenario for CMOS MAPS technology push Example: optimization for application requiring thicker substrate or more radiation hardness - Purchase of high-resistivity, detector quality bulk wafers (200 mm) is possible nowadays (market exists for both p and n- type material) - CMOS processing by standard, modern CMOS foundry (triple well) possible. Several companies interested to try ( nm process range) - Post-processing: wafer thinning, back-contact or back-junction implementation and activation at low temperature. Technology available through many sources, starts to be cheap and reliable - TCAD simulation based on realistic process parameters from foundry exists and confirm that this scenario may work!* * Credit to Tomasz Hemperek, Bonn University 19

20 Conclusions - Present generation of CMOS Monolithic Pixel Sensor technologies may satisfy number of physics experiments requirements for vertex detectors (except Atlas, CMS and LHCb) from the point of view of their radiation hardness, speed and tracking parameters. Because of comparable costs, replacement of silicon strips may be also envisaged - Construction methods of ultra-light sensor ladders are progressing rapidly, embedding in polymer seems to be a new interesting option. Before end of this year we expected to finish six-sensors (M26) ladder, with four kapton/ aluminum layers and estimated radiation length of ~0.12%. Outlook - Application optimized but still commercial (cheap!) CMOS process with thick, high-resistivity bulk substrate are coming and may sweep classical hybrid (silicon) pixels in many applications. Progress in 3D integration of heterogeneous CMOS wafers may push pixel technology even further 20

21 Appendix: history of MAPS (Mimosa series) in pictograms M-1 (2000) M-5 (2003) M8, M16 ( ) M-25 (2008) M26,M28 ( ) M33-Mxx (near future) 21

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