THE need for increased die-to-die bandwidth in highperformance

Transcription

1 552 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 4, APRIL 2017 Design and Demonstration of a 2.5-D Glass Interposer BGA Package for High Bandwidth and Low Cost Brett M. D. Sawyer, Yuya Suzuki, Ryuta Furuya, Chandrasekharan Nair, Ting-Chia Huang, Vanessa Smet, Kadappan Panayappan, Venky Sundaram, and Rao Tummala, Life Fellow, IEEE Abstract Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass interposer described in this paper is superior to silicon interposer in cost and electrical performance, and to organic interposer in interconnect density. This paper describes a 2.5-D glass interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly for a 2.5-D glass interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF. Index Terms 2.5-D interposer, electronics packaging, excimer laser via, glass interposer, high-performance computing (HPC), multichip modules, semi-additive process (SAP). Manuscript received December 29, 2015; revised September 20, 2016; accepted January 9, Date of publication March 2, 2017; date of current version April 18, Recommended for publication by Associate Editor T.-C. Chiu upon evaluation of reviewers comments. The authors are with the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA USA ( bsawyer@gatech.edu; yuya.suzuki@ece.gatech.edu; rfuruya3@mail.gatech.edu; cnair3@gatech.edu; thuang68@gatech.edu; vanessa.smet@prc.gatech.edu; kadappan@prc. gatech.edu; vs24@mail.gatech.edu; rao.tummala@ece.gatech.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCPMT I. INTRODUCTION THE need for increased die-to-die bandwidth in highperformance computing (HPC) is a direct result of the continued proliferation and projected growth of connected devices. Not only is the increase in personal mobile services pushing HPC bandwidth, but machine-to-machine communication required for a new era of Internet of things, autonomous electric vehicles, and smart homes and cities is expected to result in an unprecedented demand for bandwidth at lowest latency, lowest cost, and highest reliability [1]. As a result, new packaging architectures and technologies, such as 2.5-D integration as shown in Fig. 1, are needed to meet five critical requirements. A. System Requirements The five fundamental parameters in achieving the needed bandwidth in any commercialized package architecture include the following: 1) high interconnect density at short interconnect length; 2) low power consumption; 3) low package layer count; 4) low cost; 5) high reliability. Optimization of these parameters leads to a maximum bandwidth per unit watt signal power per unit dollar cost BWF such that δr BWF = η(r)cl 2 (1) where δ is the interconnect density in lines per unit length per layer, r is the data rate per line, η is the signal power per unit length at a given data rate r, C is the fabrication cost per unit area per layer, and L is the interconnect length. Increasing interconnection density is dependent on two factors: 1) decreasing redistribution layer (RDL) line pitch and width, and 2) decreasing chip-level bump pitch. Minimizing RDL line pitch requires a substrate with low surface roughness and total thickness variation, as well as high coplanarity to improve lithography ground rules. Reducing chip-level bump pitch requires a substrate coefficient of thermal expansion (CTE) matched to the IC to improve chip-level interconnect reliability, while also enabling direct IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 SAWYER et al.: DESIGN AND DEMONSTRATION OF A 2.5-D GLASS INTERPOSER BGA PACKAGE 553 TABLE I COMPARISON OF 2.5-D DIE INTEGRATION TECHNOLOGIES Fig D die integration on generic interposer or substrate with a highdensity interconnect volume defined by L (interconnect length), w (I/O width), and N (number signal layers) through which BWF is defined. attach to board by surface-mount technology (SMT) to reduce off-package signal power. Decreasing die-to-die I/O power requires a reduction in conductor and dielectric losses for individual signal lines, simultaneous switching noise and crosstalk between adjacent lines, and die-to-die interconnect length using advanced chip-level assembly technologies. Lowering packaging cost is achieved by reducing total package layer count and reducing RDL processing cost. B. Prior Art The first implementation of a 2.5-D interposer was Xilinx s stacked silicon interconnect (SSI) technology [2]. Stringent I/O density, signal latency, and signal power requirements determined the need to integrate a split field-programmable gate array die on a passive silicon interposer fabricated using a 45- or 65-nm process node. In doing so, greater than die-to-die interconnects are used to provide one-fifth the latency and 100 bandwidth per watt compared to standard I/O packaging implementations. According to (1), the main constraint on SSI becoming a ubiquitous 2.5-D packaging solution is cost since back-end-of-line (BEOL) processes are used to fabricate the high-density RDL layers on a 300-mm wafer format. Furthermore, die-to-die interconnects are subject to increased conductor losses due to a reduced line height determined by BEOL design rule, while off-package interconnects with through silicon via (TSV) require high-resistivity (20 cm) wafers to improve the electrical performance further increasing packaging costs [3]. To address the scalability and cost of 2.5-D silicon interposers, alternatives have been proposed including organic interposers and embedded interconnection bridges. Organic interposer implementations include integrated thin-film highdensity organic package (i-thop) by Shinko and Advanced Package X (APX) by Kyocera [4], [5]. Embedded 2.5-D solutions require a passive die with high interconnect density embedded within a substrate build-up layer. Embedded 2.5-D integration includes embedded silicon interconnect bridge by Intel and embedded glass interconnect carrier by Unimicron [6], [7]. These alternative solutions, however, are ultimately limited according to (1) by interconnection density on an organic substrate suitable for 2.5-D integration. Specifically, low-dimensional stability due to CTE mismatch affects layer-to-layer registration that reduces line density per layer, while warpage due to low modulus limits fine-line lithography as well as fine-pitch chip-level assembly and reliability. Current 2.5-D die integration technologies are compared in Table I based on the aforementioned system requirements. Silicon-based 2.5-D interposer enables high interconnect density, but at high packaging cost and high layer count. A laminate substrate is required between the silicon interposer and system printed wiring board (PWB) due to the fixed CTE

3 554 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 4, APRIL 2017 Fig. 2. Glass interposer package schematic (not to scale) with detailed cross section (looking from die gap into the die region) depicting fine-pitch RDL, blind microvia, and chip-level assembly combined with direct board attach to provide low-power high-density die-to-die interconnection. of silicon. Low chip-level reliability results without the use of an intermediate substrate ball grid array (BGA). Package layer count is inherently increased without the ability for direct SMT to PWB. Organic-based 2.5-D interposers using thin-film technologies enable SMT to PWB and reduce RDL costs, but at the expense of I/O power and warpage at large body sizes. Organic-based 2.5-D interposers using an advanced laminate material set, while leveraging an established manufacturing infrastructure, ultimately result in higher layer count and lack of scalability to fine pitch at large body size. Embedded 2.5-D integration addresses the scalability of silicon to large body size while enabling direct board attach, but still requires wafer scale BEOL processing at higher packaging cost. Therefore, no existing 2.5-D technologies provide an optimal BWF. Georgia Tech proposes a 2.5-D glass interposer package as shown in Fig. 2, which satisfies the aforementioned system requirements. Specifically, the advantages of glass for 2.5-D integration to maximize BWF according to (1) include the following: 1) advanced semi-additive processes (SAP) with interconnect density comparable to silicon; 2) thick signal layer metallization on low-loss dielectric to reduce signal power; 3) tailorable CTE to enable large body glass BGA with SMT to PWB; 4) double-sided panel-scalable processes to reduce packaging cost; 5) high chip- and board-level reliability at less than 50-μm chip bump pitch on glass BGA with no in-between substrate. The proposed glass interposer package stack-up in Fig. 2 minimizes losses in high-speed off-interposer nets using finepitch low-loss through package vias (TPVs) as described in [8] where TPV insertion losses less than 0.15 db at f = 20 GHz are demonstrated. A glass interposer package with BGA and direct attachment to PWB can be achieved using SMT described in [9] where a glass package stack-up, similar to Fig. 2, was demonstrated with high reliability at a body size up to mm 2. Direct attachment to board using a glass interposer BGA package decreases both interconnection length and layer count compared to silicon, thus improving off-package signal performance and power delivery. Existing glass interposer technologies described in [8] and [9] motivated the focus of this paper items 1), 2), and 4) to demonstrate die-to-die interconnect density required for 2.5-D die integration at optimal BWF. Interconnect densities comparable to silicon are achieved using a double-side SAP and chip-level interconnect by thermocompression bond (TCB) with copper pillar. High line density by advanced SAP is achieved on glass due to its low surface roughness and low total thickness variation across panel. Furthermore, SAP can reduce conductor loss and dielectric loss by fabricating large aspect ratio lines on low-loss thin-film dielectrics. The following sections describe the design, fabrication, and characterization of a low-cost 2.5-D glass interposer test vehicle (TV). Section II discusses specific interposer design rules showing how the proposed SAP and blind microvia rules compare to silicon interposer line density. Section III gives an overview of the double-side fabrication process while analyzing specific RDL processes and their effect on finepitch interconnect yield. Section IV describes the 2.5-D chiplevel assembly process used and provides time zero electrical yield results in the demonstration of the proposed 2.5-D glass interposer package. II. DESIGN One of the critical enabling technologies for 2.5-D integration is line density. Line densities up to dieto-die interconnections have been achieved using single-sided wafer-scale processing. Section II-A discusses the design of a low-cost 2.5-D glass interposer, with comparable interconnect density enabled by an advanced fine-line SAP and microvia excimer laser scan ablation. A. Interconnect Density and Microvia Process Processing nodes at which silicon interposers are being fabricated employ a dual-damascene process, which enables the simultaneous fabrication of an embedded trace and blind microvia. In doing so, the need for large via capture pads in these interconnects layers is reduced and line density is maximized for efficient die escape. The microvia technology employed in the proposed fabrication process must minimize capture pad size to provide comparable line density between dies at lowest packaging cost. Lithography alignment, substrate dimensional stability, and via drill alignment are the main contributing factors to the size of a microvia capture pad. The dependence on the number of lines n routed between two via capture pads of diameter at pitch D is n (D + P) (2σ + + W) P (2)

4 SAWYER et al.: DESIGN AND DEMONSTRATION OF A 2.5-D GLASS INTERPOSER BGA PACKAGE 555 TABLE II DESIGN RULE SUMMARY FOR GLASS INTERPOSER TEST VEHICLE Fig. 3. Isometric view of escape routing interconnect density at line pitch P and width W where D is the minimum microvia pitch, is the via landing pad diameter, and σ is the minimum line to pad spacing. Fig. 4. Single-layer line density at 40-μm pad pitch and various via capture pad sizes from 5 to 25 μm as a function of SAP line pitch and width. where σ is the pad to line space, P is the line pitch, W is the linewidth determined by SAP design rules, and D is determined by the microvia process implemented as depicted in Fig. 3. Given the number of lines escaped and the inline escape geometry shown in Fig. 3, the line density δ for a single routing layer is 1000 (n+1) δ = (3) D where pad pitch D is in micrometers. The dependence on routing density on capture pad size = 5 25 μm isshown in Fig. 4 for D = 40 μm at various SAP line pitches and linewidths. Based on this plot, the design rules for escape routing and via capture pad were determined for the 2.5-D glass interposer TV. Assuming that the minimum line pitch and width are 6 and 3 μm, respectively, via capture pad diameters between 15 and 20 μm are suitable to achieve 100 lines/mm. At a signal bus width of 25 mm, 2500 dieto-die interconnections can be routed in a single layer, and identical four routing layers are required to achieve the interconnections compared to BEOL processes. Fig. 5. Glass interposer TV stack-up (not to scale) and design rule summary all units are in micrometers (μm). The TV stack-up is symmetrical. Interconnect geometries, dielectric layer names, and metal layer names are identical on top and bottom sides. B. 2.5-D Glass Interposer Test Vehicle Design The 2.5-D glass interposer TV is designed in order to demonstrate the integration of advanced fine-line SAP and fine-pitch TCB to achieve interconnect densities required for high-performance applications on a larger than reticle size coupon. TV design rules are summarized in Table II, and a schematic of the interposer stack-up including layer thickness and layer design name is shown in Fig. 5. A symmetric dielectric and metal layer stack-up is used where TPVs are not integrated into the design and the inner metal layer is fabricated on a polymer laminated glass core. The targeted interposer size is mm 3.Total interposer thickness does not include C4 bumps and is based on 100-μm and 10-μm glass core and dielectric build-up film thicknesses, respectively. A single fine-line routing layer M2 with 100 lines/mm is included with design rules based on the line density analysis above. The target metal thickness is 4 μm nominal resulting in a fine-line aspect ratio of approximately High-density lines combined with dummy metal included on M2 are used to provide a copper density

5 556 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 4, APRIL 2017 of approximately 55%. Therefore, a dielectric thickness of 7 μm is expected after lamination and cure resulting in a blind microvia aspect ratio less than one. A blind microvia diameter of 8 μm is based on an excimer laser drill process described in subsequent sections. The top metal layer M1 is implemented as a routing layer using a nonsolder mask defined (NSMD) solder resist opening (SRO). In addition to the fine-line routing layer on M2, routing on the top metal layer is beneficial in reducing layer count and interposer cost where typical 2.5-D implementations limit the top metal layer to copper pillar for fine-pitch chip-level assembly. C. Designs for Test Multiple points for tests are required during TV fabrication to identify yield limiting processes. Due to the aggressive SAP and microvia stack-up design rules, test structures to determine individualprocess yields for 6-μm pitch SAP and 40-μm pitch microvia laser ablation are included in the TV design. Fine-pitch SAP test structures shown in Fig. 6(a) are a unique interdigitated structure mimicking a die-to-die interconnect fanout. Open and short testing is used to determine if die escape and fanout lines are shorted. Variations for this test structure include the number of die rows escaped, and it varies from one die row up to six die rows. Given the design rules for M2, four lines are escaped per row at 40-μm pitch, and a maximum of 24 die-to-die interconnects is assessed in a single test structure. Test points to analyze microvia ablation are shown in Fig. 6(b). Two-point probe tests are performed on microvias near the die corners after completing M1 SAP to determine if proper interconnection is made between the top routing layer and fine-line routing layer. Fully integrated 2.5-D routing test structures are shown in Fig. 6(c). Two variations on these fully integrated test structures are included to decouple dependence of chip-level assembly. Four-point probe tests at 1a-1b as well as 3a-3b are used to determine the yield of fine-pitch RDL and assembly. Test points 2a-2b bypass assembly yield to analyze the integration of fine lines and fine-pitch microvias. The TV design also includes assembly test structures decoupled from finepitch RDL processes to critically examine 2.5-D TCB yield. III. FABRICATION All TV samples are fabricated using a double-side process flow on mm 3 glass panels. This section describes a low-cost process scalable from 150 to greater than 500 mm panel size to achieve high-density RDLs at 40-μm bump pitch and below. Yield critical technologies included in the proposed panel-scalable process are then analyzed based on the aforementioned DFT structures. Contributing factors to reducing the fabrication costs in addition to potential economies of scale include the use of high-throughput packaging processes, low-temperature dry film polymers for build-up dielectrics, and high routing density to reduce layer count. A. Panel-Scalable Process Flow The process flow used to fabricate the 2.5-D glass interposer TV is summarized in Fig. 7. The first step in fabricating the Fig. 6. Test structures to assess yield of critical fabrication processes including (a) fine-line SAP by a unique comb structure that mimics a dieto-die escape routing structure, (b) fine-pitch microvia ablation, and (c) fully integrated 2.5-D routing test structures including fine-line SAP + fine-pitch microvia + fine-pitch chip-level assembly. fine-line routing layer is vacuum lamination of a dry thin-film interlayer dielectric (ILD) with inherent low surface roughness onto the glass panel, which has been treated with a silane layer to increase polymer adhesion. In doing so, the high degree of coplanarity and local surface roughness required for fine-line lithography is achieved. This is followed by the deposition of a seed layer. Seed layer deposition techniques employed

6 SAWYER et al.: DESIGN AND DEMONSTRATION OF A 2.5-D GLASS INTERPOSER BGA PACKAGE 557 Fig. 8. SAP fabrication results using an electroless copper seed layer after (a) dry film resist lamination, (b) electrolytic plating and resist strip, and seed layer etch. (c) Top view of panel. (d) Coupon cross section. Note that observations of discontinuous lines were required as a part of the DFT structures and do not indicate processing errors. Fig. 7. Panel-scalable process flow to fabricate a low-cost 2.5-D glass interposer. Fabrication processes (b) (e) detail a SAP with a novel seed layer etch required for high line density on M2. A similar SAP is repeated in process (g) to complete M1. include an electroless copper wet plating process and a Ti Cu physical vapor deposition (PVD), where an electroless process is preferred due to its direct compatibility with a double-side process flow. After seed layer deposition, fine-line SAP is performed. A dry thin-film photoresist is laminated and patterned using i-line projection lithography. The projection lithography system affords a circular exposure field at a diameter of approximately 100 mm with a mm2 high-resolution area with no demagnification. Fine-pitch RDL patterns are restricted to this high-resolution area in the panel layout. After lithography, electrolytic plating is used to form high-density traces followed by stripping of the resist layer. In addition to low surface roughness, seed layer etching is critical to realize a 6-μm pitch RDL. To improve fine-line yield, a differential spray etching process is used to remove the seed layer. Finepitch microvias are used to interconnect the top routing layer with the high-density layer. These microvias are formed by a panel-scalable excimer laser scan ablation technique following vacuum lamination of the second ILD (ILD1) using similar conditions as ILD0. To improve coplanarity and top routing layer yield, a hot press is implemented to planarize ILD1. The top routing layer is formed after via ablation using similar SAP conditions as the high-density routing layer. As a part of this SAP, electrolytic plating is used to fully fill the microvias. This is achieved by maintaining a blind microvia aspect ratio of less than one. Electrolytic plating optimization was performed to ensure dimpling and/or dishing does not occur in the via capture pad on M1. The glass interposer panel fabrication is completed after NSMD passivation and electroless nickel immersion gold (ENIG) surface finish. Using a high-resolution photoimageable thin-film dielectric enabled passivation of the fine-pitch substrate pads to prepare for chip-level TCB. B. Fine-Line SAP Fine-pitch RDL fabrication results using an electroless seed layer deposition SAP are summarized in Fig. 8. Mask compensation of μm was used to improve line shape after seed layer etch. Therefore, two mask variations to realize a 6-μm pitch RDL at 3-μm line were used including 4-μm line at 2-μm space and 3.5-μm line at 2.5-μm space. Mask compensation increases risks of resist collapse and/or delamination after development. Lithography results shown in Fig. 8(a) after resist development and plasma descum indicate no collapse or delamination in the photoresist layer. After electrolytic plating to form RDL traces, processing challenges exist when stripping the resist layer. This is due to the high 1.33 aspect ratio of the fine-pitch traces afforded using SAP and desired for reduced interconnect parasitics. Fine-pitch RDL after resist stripping is shown in Fig. 8(b) with no indication of resist residue. The final step in SAP is seed

7 558 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 4, APRIL 2017 Fig. 9. Fine-line SAP fabrication yield comparison using an electroless copper versus a sputtered Ti Cu seed layer. Test structure nomenclature on the horizontal axis indicates that all test structures included are substrate-only fine-line structures (i.e., SUB-NA-FL ). The first digit indicates test structure location on the coupon. The last two digits indicate the number of fine lines included in the die-escape comb structure (e.g., 02 indicates there are two die rows escaped where there are four lines escaped per row, or a total of eight lines). layer etching. While process steps to maintain 3-μm linewidth were taken including mask compensation and differential spray etch, 0.2-μm line narrowing is observed as indicated by the results in Fig. 8(c) and (d). Fine-line yield data shown in Fig. 9 indicate that seed layer etching proves to be the critical process step. With increasing line density, fine-line yield shows a distinctive rolloff from 0.90 to 0.60 when the number of interconnects increased from 12 to 16 traces in the test structure. Underetching was determined to be the root cause of failure upon panel inspection, which showed residual seed layer in high-density routing areas. This residual seed layer is due to copper anchoring during electroless copper plating. Panel cross sections reveal submicrometer anchors in the seed layer as shown in Fig. 8(d). These anchors are a result of a desmear step used as a part of the electroless deposition process. Desmear was shown to increase polymer surface roughness up to R z = 1.0 μm. Therefore, to remove anchors in the seed layer, a tradeoff in etching time exists. Complete removal of the seed layer results in overetching of fine lines. On the other hand, when the etching time is reduced, inadequate seed layer removal results in fineline shorting and in turn reduced yield. Modifying fine-line SAP to use a Ti Cu PVD seed layer improves yield as shown in Fig. 9. Titanium acts as an adhesion layer to the ILD, mitigating the need for desmear. As a result, filler materials are not removed from the underlying ILD, and low surface roughness necessary for fine-line yield is maintained. For each variation in fine-line test structures, a PVD seed SAP resulted in higher yield above 0.80 compared to an electroless seed SAP. C. Microvia Excimer Laser Ablation and Top Metallization Microvia fabrication was achieved using a XeCl excimer laser (λ = 308 nm) scan ablation process. To increase process throughput when scaling to large panel processing, a scan ablation technique is employed instead of a point-to-point laser ablation. The scan ablation method utilizes a quartz mask with sputtered aluminum openings to simultaneously ablate microvias over the entire mm 2 coupon area, which included a total of vias (7520 at 40-μm inline pitch and 7184 at 150-μm inline pitch). Optical inspection and profilometry data were used to confirm via opening and via side-wall angle greater than 80. As described earlier, a challenge in implementing a low-cost 2.5-D interposer technology is minimizing microvia capture pad size in order to increase interconnect density. Fig. 10(a) demonstrates the overlay accuracy achieved using the scan ablation process. The alignment process marker in the cutout of Fig. 10(a) represents five capture pad diameters ranging from18downto10μm. This process marker was included in the corner of each coupon and was used to confirm less than 2-μm overlay accuracy without alignment compensation during via ablation. When plating the top routing layer M1, fully filling the microvia without significant dimpling or dishing was considered critical for via-in-pad assembly yield. In scaling the RDL technologies included in the fabrication of this TV to multiple fine-line layers, fully filled via plating is critical to enable stacked microvia and further increase interconnect densities. Fig. 10(b) and (c) shows optical profilometry data obtained after M1 plating. Fig. 10(c) shows a micrograph of two capture pads included in one of the microvia DFT structures. Fig. 10(b) shows the two respective pad profiles indicating submicrometer topography at the top of the pad. Therefore, plating conditions are sufficient for via-in-pad assembly. Using DFT structures shown in Fig. 6(b), microvia yield was determined. Since a two-point probe method was used, a pass condition for any given DFT structure is considered R < 5. Increased resistance is expected due to parasitic trace and contact resistance. An average panel yield of 0.88 was observed based on this test condition. IV. ASSEMBLY Sequential pick-and-place thermocompression bond with copper pillar and a post-applied capillary underfill is used for 2.5-D chip-level assembly at 56-μm bump pitch and 100-μm die spacing. The assembled die is mm 3 with a four-row 80-/40-μm staggered pin-out at the die periphery and a 150-μm full array interior pin-out (5456 total bumps). On-chip copper RDL patterns are intended for electrical daisy chain connectivity tests only. The bump stack-up is 17/3/16 μm Cu/Ni/SnAg with a 28-μm bump diameter. The following describes the 2.5-D panel-level assembly process and results on 100- and 300-μm thick glass panels. A. 2.5-D Chip-Level Assembly After completing glass interposer panel fabrication as shown in Fig. 7, bonding areas are treated using an acetone and isopropyl alcohol (IPA) clean, and a prebake is applied. Directly prior to die assembly, a no-clean flux is applied at the bonding site, and the panel is placed on the assembly

8 SAWYER et al.: DESIGN AND DEMONSTRATION OF A 2.5-D GLASS INTERPOSER BGA PACKAGE 559 Fig. 11. (a) and (b) Sequential pick-and-place TCB of 10 mm 10 mm die at 100-μm die gap followed by (c) dual-dispense capillary underfill and (d) time zero electrical open and short testing. Fig. 10. (a) Representative blind microvia drill alignment across panel, (b) optical profilometry data after SAP2, and (c) substrate pads for chip-level assembly and course escape routing structures on M1 layer. stage, which is kept at T = 70 C in stand-by. Chiplevel assembly is then carried out according to the process flow shown in Fig. 11. The first die is picked and placed using a mm 2 flat tool head, and stage temperature is increased to T = 120 C directly prior to and during bonding. Thermocompression bond of the first die is carried out where the tool head temperature is ramped at 6 K/s to T = 390 C. After a t = 3-s nominal dwell time, the tool head is cooled to T = 70 C at 6 K/s. A constant bond force of F = 6 N is applied throughout the heating profile. The second die is assembled using similar TCB process conditions at a 100-μm die gap. This is a nominal die gap distance as die alignment and electrical die-to-die interconnect length is ultimately determined using complementary fiducials on the coupon and die. Die assembly is checked prior to underfill dispense using test structures routed on M1 and die RDL layers only. After TCB is confirmed by open/short testing, bonding areas are treated using an acetone and IPA clean. The assembled panel is then placed on a hot plate at T = 90 C prior to underfill dispense. Underfill dispense volume is optimized to prevent overburden in the die gap. Also, to mitigate the risk of underfill voiding, a dual-point dispense technique shown in Fig. 11(c) is used where a dot underfill dispense is applied at opposing die edges. Die assembly is completed after a postcure at T = 165 C for t = 1.5 h.

9 560 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 4, APRIL 2017 Fig. 13. Completed 2.5-D glass interposer panel after fine-pitch TCB chiplevel assembly depicting fine-line die-to-die daisy chain test structure yield map. Yield map shows average yield based on coupon location. Fig D chip-level assembly results at 56-μm pitch (80-/40-μm pinout) with cross-sectional views. (a) Chip-level assembly viewing die gap. (b) Chip-level assembly viewing fine-line routing layer. (c) Via-in-pad die assembly detail. B. Demonstration of 2.5-D Chip-level Assembly on Glass Interposer Fine-pitch 2.5-D assembly on a 100- and 300-μm thick glass interposer with a high-density RDL fabricated using lowcost processes was demonstrated. Fig. 12(a) and (b) shows assembled coupon cross sections where Fig. 12(a) is looking from the coupon edge toward the 2.5-D die gap and Fig. 12(b) is viewing inward from the die gap toward the high-density routing layer. Inspecting the 2.5-D die gap indicates that the postapplied capillary underfill flows into the gap without overburden. Furthermore, the detailed micrograph of the finepitch solder joint in Fig. 12(c) indicates that a good chip-level interconnect is formed with minor solder depletion. This solder depletion is due to ENIG overplating, which is a result of palladium poisoning of ILD during M1 SAP. Line narrowing of the high-density traces is observed in Fig. 12(b) similar to the results observed after fine-line SAP in Fig. 8(d). Detailed cross sections confirm high-accuracy microvia ablation and fully filled via plating with no apparent dimpling or dishing. After completing panel-level 2.5-D assembly, time zero electrical yield was measured across three panels. The test sample size included: 1) one 300-μm-thick panel fully populated with a total of eight assembled coupons; 2) one 300-μm-thick panel partially populated with a total of seven assembled coupons; and 3) one 100-μm-thick quarter-panel with two assembled coupons. Two test structure variations were analyzed including: 1) die corner daisy chain (two structures per coupon) and 2) fine-line die-to-die daisy chain (four structures per coupon). Test structure 1) includes routing on M1 and die RDL only and is used to assess TCB yield. Test structure 2) is representative of a die-to-die interconnect and assesses integration of the advanced interposer fabrication and assembly processes described. The pass condition for each test structure was a daisy chain resistance R < 50. An elevated pass condition is used based on coupon cross sections indicating solder depletion and line narrowing, which may increase chip-level interconnection resistance. One coupon on panel 2) exhibited 1.00 yield for all test structures considered, indicating successful demonstration of fine-pitch RDL and chip-level assembly for 2.5-D die integration on a low-cost glass interposer. The average yield of test structure 1) for the 17 coupons tested was indicating good 2.5-D TCB despite solder depletion. Test structure 2) results are summarized in Fig. 13 by average yield based on coupon position. Panels considered for the reported time zero yield analysis used an electroless SAP. Therefore, overetching of interconnects during seed layer removal on M2 as indicated in Fig. 9 is considered the yield limiting process. V. CONCLUSION In this paper, the design and demonstration of a 2.5-D glass interposer BGA package TV capable of meeting all

10 SAWYER et al.: DESIGN AND DEMONSTRATION OF A 2.5-D GLASS INTERPOSER BGA PACKAGE 561 system requirements to maximize bandwidth per unit watt signal power per unit dollar cost is described. The focus of this paper is the analysis of advanced SAP and chip-level assembly processes to provide interconnect density comparable to silicon at shortest interconnect length using the following: 1) low-cost double-side SAP to fabricate a 6-μm pitch RDL; 2) panel-scalable excimer laser scan ablation to fabricate RDL via at 40-μm inline pitch; 3) panel-level TCB 2.5-D die assembly at 56-μm bump pitch and 100-μm die gap. Routing studies performed show that these RDL processes are capable of achieving a line density δ = 100 lines/mm. Up to die-to-die interconnections can be achieved at this line density and bus width w = 25 mm using the same number of signal routing layers as silicon. Specific RDL structures were designed for tests during the double-side fabrication process. Panel-level tests indicated that the removal of the electroless copper seed layer during SAP is critical to fine-line yield. Optimizing SAP etch time or implementing a PVD SAP was shown to improve 6-μm pitch RDL yield beyond Tests also indicated that fine-pitch microvias were fabricated at less than 2-μm overlay accuracy without drill alignment compensation, and demonstrated the microvia stack-up can be scaled further to increase routing density. Furthermore, electrolytic plating of microvias demonstrated fully filled via capable of via-in-pad assembly, and stacked via when scaling the RDL technologies discussed to multilayer high-density routing. Thermocompression bond 2.5-D chip-level assembly was performed on 100- and 300-μm-thick glass at high yield above 0.80 on multiple panels. Failure analysis using cross section revealed that solder depletion due to ENIG overplating. Chip-level assembly can be improved with optimized palladium strip after SAP. Fully integrated fine-pitch RDL and 2.5-D chip-level assembly tests indicated up to 1.00 yield, and thus demonstrates a low-cost 2.5-D glass interposer to achieve interconnect density comparable to silicon. Analysis of each of the aforementioned glass interposer technologies using DFT structures indicates that seed layer etching optimization during fine-line SAP was critical to increase high-density interconnect yield. Therefore, the 2.5-D glass interposer BGA package described in this paper has great potential to provide the dieto-die bandwidth required in next generation HPC systems at a maximum BWF. ACKNOWLEDGMENT The research results described are a part of industry consortium program at Georgia Tech Packaging Research Center. The authors would like to thank all the consortium member companies and supply chain partners in supporting this research effort. REFERENCES [1] B. Bottoms, Maintaining the pace of progress as we approach the end of Moore s law: New materials, new processes, new architectures, in Proc. Int. Symp. Microelectron., 2015, pp. S1 S57. [2] K. Saban, Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency, Xilinx, San Jose, CA, USA, White Paper WP380 (v1.2), [3] N. Kim, C. Shin, D. Wu, J. Kim, and P. Wu, Performance analysis and optimization for silicon interposer with through silicon via (TSV), in Proc. Conf. SOI, Oct. 2012, pp [4] K. Oi et al., Development of new 2.5D package with novel integrated organic interposer substrate with ultra-fine wiring and high density bumps, in Proc. Electron. Compon. Technol. Conf. (ECTC), May 2014, pp [5] M. Ishida, APX (Advanced Package X) Advanced organic technology for 2.5D interposer, presented at the Electron. Compon. Technol. Conf. (ECTC), Orlando, FL, USA, May 2014, pp [6] M. Deo, Enabling next-generation platforms using Altera s 3D system-in-package technology, Altera, San Jose, CA, USA, Tech. Rep. WP , [7] D. C. Hu, Y. P. Hung, Y. H. Chen, R. M. Tain, and W. C. Lo, Embedded glass interposer for heterogeneous multi-chip integration, in Proc. Electron. Compon. Technol. Conf., May 2015, pp [8] V. Sukumaran et al., Design, fabrication, and characterization of ultrathin 3-D glass interposers with through-package-vias at same pitch as TSVs in silicon, IEEE Trans. Compon., Packag., Manuf. Technol., vol. 4, no. 5, pp , May [9] Q. Xian, P. M. Raj, V. Smet, and R. Tummala, Direct SMT interconnections of large low-cte interposers to printed wiring board using copper microwire arrays, IEEE Trans. Compon., Packag., Manuf. Technol., vol. 5, no. 11, pp , Nov Brett M. D. Sawyer received the B.S. degree in electrical engineering from Old Dominion University, Norfolk, VA, USA, in 2011, and the M.S. degree from the Georgia Institute of Technology, Atlanta, GA, USA, in 2014, where he is currently pursuing the Ph.D. degree in electrical engineering. He joined the 3-D Systems Packaging Research Center, Georgia Institute of Technology, in This work has applications mainly in high performance computing modules including wide I/O logic-memory and 400 GbE CDFP to provide cloud services to mobile devices. His current research interests include the design and demonstration of a 2.5-D glass interposer package to achieve 1-TB/s dieto-die and 400-Gb/s off-interposer bandwidths. Yuya Suzuki received the B.S. and M.S. degrees in applied chemistry from the University of Tokyo, Tokyo, Japan, in 2005 and 2007, respectively. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA, USA. He joined Zeon Corporation, Tokyo, in 2007, as a Research Engineer. He is currently with the 3-D Packaging Research Center, Georgia Institute of Technology. His current research interests include the development of glass interposer and passive embedded RF module using low loss polymer material, and polymer synthesis, polymer processing, and organic-inorganic hybrid materials. Ryuta Furuya received the B.S. and M.S. degrees in physics from the University of Tokyo, Tokyo, Japan, in 2010 and 2012, respectively, with a focus on star formation processes. He joined USHIO Inc., Yokohama, Japan, in 2012, and is currently with the 3-D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA, as a Visiting Engineer. His current research interests include the development of projection lithography process for large-scale panel-based interposer technology, and the projection lithography optics, chip-to-chip optical interconnect, and energy harvesting.

11 562 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 4, APRIL 2017 Chandrasekharan Nair received the bachelor s degree in polymer engineering and technology from the Institute of Chemical Technology, Mumbai, India, in 2013, with a minor in chemical engineering. He is currently pursuing the Ph.D. degree in materials science and engineering with the 3-D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA, under the guidance of Prof.R.Tummala. As a Graduate Research Assistant in the Low Cost Glass Interposer Program, he was involved in the reliability evaluation of novel polymer dielectric materials and processes to build next-generation redistribution layer for panel scale interposers/high density packages. His current research interests include polymer-metal interfaces, package substrate reliability studies, and polymer characterization. Ting-Chia Huang received the master s degree in material science and engineering from National Taiwan University, Taipei, Taiwan, in 2012, with a focus on solder interfacial reaction and electromigration. He is currently pursuing the Ph.D. degree with the 3-D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA, conducted by Prof. R. Tummala. As a Graduate Research Assistant in Interconnections and Assembly Program, he was involved in the development of off-chip interconnections with thermocompression bonding for fine pitch and high reliability, including the scopes of solder-capped microbumps, solder-liquid interdiffusion (SLID) bonding, preapplied underfill process development, and finite element analysis for stress management. He is also the first inventor of the patent Metastable Interconnections Structure for ultrafast SLID bonding. His current research interests include metallurgical reactions, packaging reliability, and finite-element modeling. Kadappan Panayappan received the bachelor s degree from Anna University, Chennai, India, in 2006, the master s degree from IIT Kahragpur, Kahragpur, India, in 2008, and the Ph.D. degree from The Pennsylvania State University, State College, PA, USA, in He is a Research Engineer with the 3-D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA, focusing on electrical design. His current research interests include signal and power integrity, power delivery networks, antennas, highspeed interconnects, and computational electromagnetics. Venky Sundaram received the B.S. degree from the Indian Institute of Technology (IIT) Mumbai, Mumbai, India, and the M.S. and Ph.D. degrees in materials science and engineering from the Georgia Institute of Technology, Atlanta, GA, USA. He is the Director of Research and Industry Relations with the 3-D Systems Packaging Research Center, Georgia Institute of Technology. He is the Program Director for the Silicon and Glass Interposer industry consortium with more than 25 active global industry members. He is a globally recognized expert in packaging technology and a Co-Founder of Jacket Micro Devices, an RF/wireless startup acquired by AVX. He has authored more than 100 publications and holds more than 15 U.S. patents. His current research interests include system-on-package technology, 3-D packaging and integration, ultrahigh-density interposers, embedded components, and systems integration research. Dr. Sundaram was a recipient of several best paper awards. He is the Co-Chairman of the IEEE Components, Packaging, and Manufacturing Technology Technical Committee on High Density Substrates and is on the Executive Council of International Microelectronics and Packaging Societies as the Director of Education Programs. Vanessa Smet received the B.S. and M.S. degrees in applied physics from the École normale supérieure Paris-Saclay, Cachan, France, and the University of Paris XI, Orsay, France, and the Ph.D. degree in electronics from the University of Montpellier 2, Montpellier, France, in 2010, focusing on power cycling reliability of IGBT power modules in harsh environment. She was a Post-Doctoral Researcher with the Tyndall National Institute, Cork, Ireland, where she was involved in novel high-temperature high-power die-attach solutions for power switches with Ag-CNTs composites and microbga assembly. She is currently an Associate Research Professor and the Program Manager for the Interconnections and Assembly Industry Program with the 3-D Systems Packaging Research Center (PRC), Georgia Institute of Technology, Atlanta, GA, USA. At PRC, she provides leadership to develop and demonstrate new interconnection and assembly technologies beyond solders for advanced 2.5-D and 3-D packaging, as well as highpower applications, with a focus on manufacturability and technology transfer to industry. She has coauthored over 30 journal and conference publications and two patents with others pending. Her current research interests include power electronics, finite element modeling, 3-D integration, interconnection and assembly processes, SLID / TLP bonding, all-cu interconnections, lowtemperature bonding, and reliability. Rao Tummala (M 88 SM 90 F 93 LF 16) received the B.S. degree from the Indian Institute of Science, Mumbai, India, and the Ph.D. degree from the University of Illinois at Urbana Champaign, Urbana, IL, USA. He is a Distinguished and Endowed Chair Professor and a Founding Director of NSF ERC with the Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA, pioneering Moore s Law for System Integration. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering the first plasma display and multichip electronics for mainframes and servers. He has authored about 500 technical papers, holds 74 U.S. patents, and inventions. He has also authored the first modern Microelectronics Packaging Handbook, the first undergraduate textbook Fundamentals of Microsystems Packaging, and the first book introducing the system-on-package technology. Prof. Tummala was a recipient of many industry, academic, and professional society awards, including Industry Week s Award for improving U.S. competitiveness, the IEEE s David Sarnoff, the IMAPS Dan Hughes, the Engineering Materials from ASM, and the Total Excellence in Manufacturing from SME. He is also a recipient of the Distinguished Alumni Awards from the University of Illinois at Urbana Champaign, the Indian Institute of Science, and Georgia Tech. He was the President of the IEEE Components, Packaging, and Manufacturing Technology and the International Microelectronics and Packaging Societies and is a member of the National Academy of Engineering. In 2011, he received the Technovisionary Award from the Indian Semiconductor Association and the IEEE Field Award for contributions in electronics systems integration and cross-disciplinary education.