THE continuous increase of data-intensive smart mobile

Transcription

1 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 1, JANUARY Design and Demonstration of Power Delivery Networks With Effective Resonance Suppression in Double-Sided 3-D Glass Interposer Packages Gokul Kumar, Srikrishna Sitaraman, Jonghyun Cho, Venky Sundaram, Joungho Kim, Member, IEEE, and Rao R. Tummala, Fellow, IEEE Abstract Ultrathin 3-D glass interposers with throughpackage vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D interposers provide wide-i/o channels for high signal bandwidth (BW) between the logic device on one side of the interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30-µm thin, 3-D double-sided glass interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30- and 100-µm thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D interposer PDN structure can be Manuscript received March 15, 2015; revised June 1, 2015 and August 11, 2015; accepted August 11, Date of publication November 22, 2015; date of current version January 15, Recommended for publication by Associate Editor M. Cases upon evaluation of reviewers comments. G. Kumar, S. Sitaraman, and V. Sundaram are with the Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA USA ( gokul.kumar@gatech.edu; srikrishna@gatech.edu; vs24@mail.gatech.edu). J. Cho and J. Kim are with the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon 34141, Korea ( jonghyun.cho@kaist.ac.kr; joungho@ee.kaist.ac.kr). R. R. Tummala is with the Department of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA USA ( rao.tummala@ece.gatech.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCPMT effectively designed to meet the target impedance guidelines for high-bw applications, providing a compelling alternative to 3-D-IC stacking with the TSVs. Index Terms 3-D interposers, glass interposers, logic memory bandwidth, power delivery, through-package-vias, TSVs. I. INTRODUCTION THE continuous increase of data-intensive smart mobile applications demand an exponential growth in logic-tomemory bandwidth (BW) from 5 GB/s today to an estimated GB/s in the next decade [1], [2]. However, the reducing size of devices necessitates that such a need must be achieved with: 1) low power consumption; 2) ultraminiaturized form factor; and 3) low cost. Consequently, such progress is targeted to be accomplished through the 3-D stacked ICs (3-D-ICs) comprising of a logic die and a high-bw memory-stack, interconnected by through-silicon-vias (TSVs) with wide I/O channels ( ). This approach enables the shortest wire-length, highest I/O density, and reduced powerconsumption [3], [4]. While the TSV-based 3-D ICs provide several revolutionary benefits, they face certain drawbacks such as: 1) the need for the expensive TSVs in the logic die [5], [6]; 2) thermal-management of the logic die within the stack [7]; 3) lack of testability of the logic-memory stack to estimate a known-good-die stack [8]; and 4) the need for new wafer-based TSV manufacturing infrastructure [9]. To overcome these challenges, a simpler approach called the 3-D interposer package was proposed by Georgia Tech [10] to achieve the same BW as 3-D-IC stacks without the need for TSVs in the logic die. Such a configuration, as shown in Fig. 1, allows the integration of logic and memory dies separately on either side of an ultrathin double-sided interposer, with TPVs at the same I/O density as TSVs in 3-D- ICs. There has been significant progress with the fabrication of ultrathin glass substrates to enable the high-speed formation and metallization of ultrafine-pitch TPVs [11]. Glass is an excellent insulator with a dimensionally stable, smooth low-profile surface; thus enabling very low signal loss and coupling [12], and high I/O density similar to TSVs in Si. Furthermore, glass substrates can be processed on large panels and eventually from roll-to-roll processing, resulting in an estimated lower cost by a factor of 5 10 over wafer-based back end of line (BEOL) silicon interposers [13], [14]. Moreover, unlike the conventional interposers that require an additional IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 88 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 1, JANUARY 2016 Fig. 1. Schematic comparison of (a) 3-D-ICs with TSVs and (b) 3-D interposer method with glass TPVs at the same density and interconnect length as TSVs. Fig. 2. PDN challenges in 3-D BGA glass interposers. organic package for interconnection to the system board, a 3-D glass interposer package could be attached directly onto the printed wiring board (PWB) through standard solderball interconnections. With such properties, glass is proposed to be a better substrate material for 3-D interposer packages than organic and silicon. In addition to enabling high logic-to-memory BW, this unique 3-D interposer concept promises many advantages that include design flexibility, testability, thermal management, and extendability to multidie applications. Despite its many advantages, the 3-D interposer structure introduces design challenges in achieving low-impedance PDN as shown in Fig. 2. Power-ground (PG) planes on doubleside glass substrates generate multimode cavity resonances due to its high resistivity properties similar to organic packages. In addition, the placement of logic or memory dies on the underside of the package decreases the area available for ball grid array (BGA) interconnections between the package and the board. This leads to a reduction in the number of P/G BGAs at the center when compared with a 2-D glass package with fully populated area-array of BGAs. Hence, power delivery path in the 3-D package is dominated by lateral inductance of the P/G planes, which increases the overall P/G loop inductance, as shown in Fig. 2. Furthermore, the placement of land-side decoupling capacitors on the glass package is also restricted due to the double-side arrangement of the dies. Thus, there are two major factors affecting power integrity in 3-D interposer packages: 1) electromagnetic (EM) cavity-resonances due to the presence of P/G planes in the PDN network and 2) parasitic inductance due to lateral power delivery paths. These factors lead to the increased magnitude and number of resonant peaks in the PDN impedance profile, potentially resulting in rapid voltage fluctuations at high current densities, and increased simultaneous switching noise (SSN). Consequently, careful PDN design is necessary to ensure high BW in 3-D glass interposers. P/G plane resonances due to high-q substrates and techniques to mitigate the same have been extensively studied in the past decade for organic packages [15], [16]. A preliminary investigation of these effects with glass substrates was reported in [17]. More recently, the resonances in glass interposers were analyzed and compared with silicon and organic interposers [18]. The effects of signal discontinuity on substrate resonances were analyzed through multilayer finite difference method modeling [19]. These results indicate that resonance suppression in glass interposers is more challenging than in silicon, where the relatively higher conductivity of Si (10 20 S/m) reduces the resonance magnitude due to the associated high loss. The signal and power integrity in glass interposers with a large number of signal I/Os using through via transitions have been studied and compared with those in silicon interposers [20]. Based on this analysis, the SSN was identified as a major design challenge in glass interposers. The PDN design techniques to improve the signal return-path, including the placement of discrete decoupling capacitors and ground vias were investigated in [21]. However, further analysis specific to double-sided 3-D glass interposers is required to determine the impact of increased resonant peaks on power integrity. Previous studies on the impact of reduced P/G BGAs on PDN design showed a corresponding increase in the PDN loop inductance [22]. Variation in BGA placement also contributed to a 5 15% increase in the overall PDN impedance [23], [24]. Hence, it becomes critical to study the increased inductive impedance attributable to the 3-D interposer structure. The design and demonstration of double-sided packages with lateral power delivery has been traditionally focused on board level design [25]. Based on this approach, organic feedthrough interposers having a 3-Gbps channel with 50 μm-pitch flip-chip connections were developed for integrating a memory stack with the logic die [26], [27]. Recent studies have focused on the PDN design of double-sided organic packages with six redistribution layer layers having a 512 wide I/O memory interface to achieve an aggregate peak BW of 256 GB/s [28] [30]. The package IR drop and PDN inductance ( ph) for eleven different power supply rails were quantified. In addition to organic 3-D interposers, silicon interposers-based 3-D SiPs have been proposed to meet the requirements for high routing density [31], [32]. PDN impedance and simultaneous switching output noise characteristics of a 3-D Si interposer with a 4-K TSV channel have been reported [33]. The antiresonance peak of overall- PDN impedance was extracted at 80 MHz, and a phaseclocking scheme was implemented to reduce the switching current noise. The prospect of panel-based polysilicon with thick organic liners, as a low-loss substrate for 3-D interposers, has also been reported [34]. The authors previously per-

3 KUMAR et al.: DESIGN AND DEMONSTRATION OF PDNs WITH EFFECTIVE RESONANCE SUPPRESSION 89 Fig. 3. Simplified model of 3-D glass BGA interposer PDN with centrally depopulated BGA array (3-D PDN). formed a comparative analysis of the resonance characteristics of 3-D interposers using different substrate materials [35]. Suppression techniques including the use of coaxial vias within the glass substrates were also examined [36]. This paper goes beyond previous studies to present the modeling, design, fabrication, and characterization of power delivery networks, to achieve high BW in ultrathin double-sided 3-D glass interposers. The first measured comparison of PDN impedance between 2-D and 3-D glass substrates is also presented. The impedance characteristics are investigated at chip, package, and board-levels. The placement of high-density capacitors embedded within the glass interposer is analyzed to suppress resonances at mid-frequencies from 0.1 to 1 GHz. A PDN stack-up is introduced with P/G plane pairs across each build-up in a four-metal-layer glass interposer, to achieve 10 reduction in the inductive impedance. The impact of design variations on the self-impedance profile is evaluated for variations in die placement, stack-up definition, and the placement of decoupling capacitors. In addition to the 3-D interposers, the techniques presented in this paper can also be applied to the PDN design of single chip 2-D packages and multichip glass interposers. The rest of this paper is organized as follows. Section II investigates the PDN impedance of 3-D glass interposers by combining individual P/G planes modeled using 3-D EM solvers. The change in resonances due to the double-sided 3-D interposer structure, and with the addition of on-chip PDN is evaluated. The impact of resonance suppression techniques on the design of 3-D glass packages is reviewed in Section III. Section IV reports the fabrication and electrical characterization of 3-D interposer PDN using glass substrate test vehicles. Section V presents the summary and conclusion. II. INVESTIGATION OF 3-D GLASS INTERPOSER POWER DELIVERY RESONANCES The 3-D interposer package provides the PDN design advantages over organic and BEOL interposers with: 1) a unified entity for interposer and package PDN; 2) increased density of package P/G TPVs and chip-level C4 interconnections compared with organic packages; 3) the ability to integrate on-package decoupling capacitors that require higher temperature processing than possible with organic interposers; Fig D glass interposer package stack-up and P/G plane port locations. and (d) thick P/G planes (5 8 μm) compared with silicon interposers, on a thin package core (20 μm) to minimize resistive and inductive impedance. Still, the presence of P/G resonances poses a fundamental challenge in achieving a low impedance PDN, which leads to associated power and signal integrity problems. In addition, careful design of highdensity I/O signals with through via transitions is necessary to minimize the resonances due to return path discontinuity. This section investigates the self-impedance (Z11) profile of double-sided 3-D glass interposer power delivery network (3-D PDN) and thoroughly examines the P/G resonances as the critical step toward clean power delivery. In this paper, the term 2-D PDN was used to denote a glass interposer PDN with fully populated BGA array. The 3-D PDN denoted the glass interposer PDN with centrally depopulated BGA array. The basic block diagram for a 3-D PDN is shown in Fig. 3, which consists of three parts: 1) package P/G planes with lateral traces; 2) TPVs; and 3) decoupling elements. P/G planes form the basis of the glassinterposer PDN, since the inductances of the large number of parallel P/G TPVs have negligible parasitics. The magnitude of total self-impedance (Z11) was generated by interconnecting separate multiport P/G 3-D EM models with their corresponding parasitic interconnections [35]. The spatial port locations and package stack-up used for full wave simulation of the multiport glass interposer P/G planes is presented in Fig. 4. The interposer size of mm 2 was chosen to study the 3-D PDN self-impedance and the resonance modes. The P/G planes were located in the inner two-layers

4 90 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 1, JANUARY 2016 TABLE I PROPERTIES OF INTERPOSER PACKAGE MATERIALS FOR SIMULATION AND FABRICATION Fig. 6. Comparison of 2-D versus 3-D glass interposer PDN without on-chip and PWB PDN. Fig. 5. Self-impedance for on-chip grid, glass interposer package, and PWB P/G planes from [35]. across the core to provide mechanical stability. Copper planes having a thickness of 10 μm were used in this paper. The study of PDN resistance to dc was not focused on, due to the small value of the plane resistance (IR-drop) similar to organic packages. The electrical properties of materials used in the simulation and fabrication of the glass interposer packages are tabulated in Table I. The simulated self-impedance observed at the center of on-chip grid, glass interposer, and PWB P/G planes are presented in Fig. 5. It can be seen that 30-μm glass interposer with P/G planes had the lowest impedance. The effective permittivity of the P/G plane cavity was computed based on the method presented in [18]. Since the microwave modes are determined by the properties of the P/G cavity, it is possible to select polymer materials having the required thickness and electrical properties to achieve the desired resonance frequencies. In this simulation, the TM 21 mode was observed at the center. The glass interposer P/G plane capacitance and the plane inductance were extracted from the value of the first series resonant frequency. This study was extended to evaluate the self-impedance of a 2-D and 3-D PDN without the effect of on-chip P/G grid and PWB. The schematic of the simulation and the results are shown in Fig. 6. The PDN simulations for different PDN configurations were performed in Agilent ADS after combing the multiport 3-D-EM models with lumped parasitic values. Parasitic inductances were added to the port locations based on the total number of parallel BGA connections for each configuration represented by M (700 pairs) and N (300 pairs). The multiport glass package model was then grounded at port locations based on BGA configuration. For instance, the 3-D-PDN configuration was attached to the board level represented by ideal ground with reduced number of P/G BGAs (N) due to the placement of the die as shown in the schematic from Fig. 6. The interaction between the P/G plane cavity and the lateral trace generated much larger antiresonant peaks: 180 for 3-D PDN versus 5.6 for 2-D PDN. Additional loop inductance was also observed due to the reduction in the total number of BGAs. In addition, the first antiresonant frequency in the 3-D PDN was shifted to a lower frequency (6.2 GHz). This caused the overall core-pdn BW to be reduced by 2 GHz at the interposer due to the proposed double-sided approach. Hence, meticulous suppression of PDN resonances and appropriate signal routing is necessary to suppress SSN. However, the parasitic inductance of the lateral trace was smaller than the P/G planar capacitance, leading to high-impedance peaks only at frequencies beyond 6 GHz. The differences between higher order modes were negligible at very high frequencies beyond 15 GHz. The self-impedance (Z11) of the overall system as seen from center of the on-chip P/G grid was simulated by combining multiport 3-D EM models of hierarchical PDN elements from Fig. 5. The analysis was performed from die model through C4, package P/G planes, BGAs, and terminating at the board P/G planes. The simulation schematic used to perform the overall-pdn analysis are shown in Fig. 7. The PDN configurations of 2-D and 3-D interposers were estimated

5 KUMAR et al.: DESIGN AND DEMONSTRATION OF PDNs WITH EFFECTIVE RESONANCE SUPPRESSION 91 Fig. 7. Self-impedance simulation of system PDN. Fig. 10. Comparison of die placement schemes. Fig. 8. Die + interposer package + PWB comparison of 2-D versus 3-D PDN. demand from the on-chip core-pdn at such frequencies is negligible, this result suggests that the impact of BGA reduction on overall core-pdn system impedance is minimal. However, suppression methods are still necessary at all frequencies in order to meet the target impedance guidelines. Fig. 9. Effect of on-chip PDN on system-level self-impedance. based on variation in the number of package-pwb port connections. The system PDN was observed to be the sum of its individual P/G elements. Resonances were observed for the 3-D-PDN configuration near 7.3 GHz, as shown in Fig. 8, which created high impedance antiresonant peaks. The impedance comparison before and after the addition of on-chip (die) PDN is shown in Fig. 9. The resonant peaks in the interposer + PWB PDN were directly correlated with the high-impedance peaks observed in the overall-pdn as shown in Fig. 9. However, the magnitude of the self-impedance observed at the on-chip location (die + interposer + PWB) was reduced by 4 when compared with the interposer + PWB PDN. This effect was attributed to the high value of on-chip impedance at frequencies beyond 4 GHz, which dominated the overall-pdn profile. Since the transient current III. PROPOSED RESONANCE SUPRESSION TECHNIQUES In this section, three effective design techniques to suppress power plane resonances across a wide frequency range are proposed and verified. The first method analyzes the PDN impedance profile based on variations in the interposer BGA arrangement due to die placement. The second method examines the selection and placement of discrete and embedded decoupling capacitors within the glass substrates. The final method introduces a new package stack-up for 3-D interposers having four power delivery layers with two plane pairs across the thin-film build-up to achieve 10 reduced inductive impedance. A. 3-D Interposer Die Configuration The impact of self-impedance from two alternate BGA arrangements based on die-placement was compared, as shown in Fig. 10, without the on-chip P/G grid and the PWB. The port assignment locations and number of P/G BGA pairs for each configuration are also detailed. The first variation (type c in Fig. 10) was designed to have the same number of P/G BGAs as a 2-D interposer with full BGA array (type a in Fig. 10). Such a configuration can be achieved by employing finer-pitch BGAs or an increased interposer size. By increasing the BGA pitch in the 3-D PDN, the impact of lateral PDN path on the PDN profile can be studied, without changing the number of BGAs. The second variation (type d from Fig. 10)

6 92 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 1, JANUARY 2016 Fig. 11. Decap placement in 3-D interposers. was designed to allow access to center of the interposer by splitting the bottom die into two smaller dies while having a reduced number of BGAs compared with the 2-D interposer. This split die approach to 3-D PDN facilitates to study the impact of changing the number of P/G BGAs. The high-impedance antiresonant peak observed in 3-D PDN was suppressed effectively using the proposed approaches. The magnitude of resonance suppression using split die configuration (type d) was much larger than using the finer-pitch 3-D PDN (type c) approach. Thus, the lateral trace inductance had a much larger impact on the self-impedance profile compared with the inductance of parallel BGAs. Hence, the use of multiple smaller dies to facilitate placement of P/G BGAs at the center of the interposer, minimizes the IO-PDN resonances at the package level; than using a single large die. This technique is effective in reducing the antiresonant peaks above 5 GHz. However, inductive impedance below 5 GHz cannot be suppressed by this method due to the inherent package parasitics. B. Selection and Placement of Discrete and Embedded Decoupling Capacitors The selection and placement of decoupling capacitors to reduce the PDN inductive impedance is a critical element in PDN design. This section evaluates the effect of decoupling capacitors on the PDN impedance of 3-D glass interposers. Three locations for on-package decoupling capacitors are shown in Fig. 11. The land-side placement of discrete capacitors at the underside of the package is restricted due to the presence of the die and the BGAs. Surface mount technology (SMT)-based discrete capacitors in 3-D interposers are ineffective at higher frequencies greater than 0.1 GHz due to their longer power delivery path and high equivalent series inductance (ESL), as shown in Fig. 11. Therefore, the embedded decoupling capacitors using component or thin-film technologies [37], [38] are most suitable to provide effective high-frequency decoupling. The ESL-limitations of discrete decoupling capacitors at higher frequencies in glass interposers is shown in Fig. 12. The simulations were performed using a signal and power integrity tool SI-wave. As an example, the self-impedance profile of the 3-D interposer PDN was simulated for the placement of decoupling capacitors with size Smaller size Fig. 12. Comparison of SMT-type decoupling capacitors. discrete capacitors with lower-esl (example: 0402 and 0201) could be used to suppress the higher frequency resonances. However, the loop-inductance due to placement restrictions from double-side die attachment still restricts the effectiveness of low-esl discrete decoupling capacitors at higher frequencies beyond 1 GHz. Different capacitor values of 1 nf, 82 pf, and 1.2 pf were chosen to study the decoupling impact at multiple frequencies. The capacitors were mounted on SMT-compatible copper pads located at two locations 2.5-mm inward from the edge of two nonadjacent sides of the interposer. Capacitors having a value of 1 nf was found to be effective in reducing PDN impedance up to 0.1 GHz. However, the effect of 1.2-pF SMT capacitor was not observed on the PDN measurement, due to its small value and high resonance frequency, which was superseded by the test structure inductance. To address these placement challenges, the integration of embedded capacitive materials has been explored in glass substrates. These materials can be processed at higher temperatures due to the inorganic nature of glass, similar to silicon interposers. The uniform placement of 1 nf embedded and SMT-type decoupling capacitors across a glass package is examined in Fig. 13. While both the embedded and SMT-type capacitors provided resonance suppression at frequencies below 0.1 GHz, embedded capacitors were observed to provide lower inductive impedance up to 1 GHz. Hence, the embedded capacitors can be employed as a miniaturized and more effective alternative to discrete SMT-type capacitors for 3-D interposer decoupling applications [37]. C. 3-D Interposer Package P/G Stack-Up The optimization of P/G planes in a glass interposer stack-up was studied to improve power integrity. This approach has been widely researched [39], since it provides distributed capacitance very close to the die, with low ESL and without additional space requirements. In addition, the multiple power or ground layers in ultrathin glass interposers can be interconnected using multiple parallel TPVs and blind vias having very low effective inductances. A schematic view of the substrate cross section and the location of TPVs employed in this paper are shown in Fig. 14. The P/G plane

7 KUMAR et al.: DESIGN AND DEMONSTRATION OF PDNs WITH EFFECTIVE RESONANCE SUPPRESSION Fig. 13. capacitors. Fig. 14. Comparison between embedded and SMT-type decoupling Fig Self-impedance comparison of four metal layer PDN. PDN setup for four metal layer P/G. Fig. 16. Self-impedance comparison of 3-D PDN of package stack-up with ideal PWB. stack-up was chosen to be symmetrical to minimize the warpage. The loop inductance of the PDN is reduced by connecting planar in multiple locations. Two types of core and build-up polymer thicknesses are explored for a glass core of thickness 30 μm: 17.5 and 5 μm ZIF. In addition, glass substrate having a thickness of 100 μm, laminated with polymer of thickness 17.5 μm was also analyzed to determine the impact of glass core thickness on the PDN impedance profile. The self-impedance profiles simulated at the center of the top metal layer for different P/G configurations are shown in Fig. 15. The proposed four-metal-layer P/G planes had 10 lower impedance than two-metal-layer stack-up, across all frequencies under consideration. Among the different four-metal layer stack-up variations, the magnitude of antiresonant peaks was suppressed in the scenario with glass core having a thickness of 30 μm (type c in Fig. 15), when compared with the glass with a thickness of 100 μm core (type b in Fig. 15) due to additional capacitance between M2 and M3 metal layers. However, for both glass thicknesses with build-up thickness of 17.5 μm, similar series resonance frequency (type a in Fig. 15) were observed, which is attributed to the identical planar capacitance between M1 M2 and M3 M4 in both cases. This study was extended as shown in Fig. 16, to compare the self-impedance profile of complete system PDN, for twometal and four-metal P/G stack-up of 3-D PDN by assuming ideal PWB and Voltage regulator module (VRM) behavior. The proposed four-metal P/G planes were proved to reduce the magnitude of the high-impedance peak in 3-D interposers from 180 to 0.9, providing effective mitigation of P/G resonances in 3-D interposers. While the overall impedance magnitude of four-metal P/G planes was 10 lower at all frequencies under consideration, an additional parallel resonance was observed at lower frequencies (few GHz) due to the interaction of the lateral inductance of the planes with the capacitance between the build-up metal layers (M1 M2). This effect was further examined in Fig. 17, which compares the impedance profiles of four-metal layer 2-D and 3-D PDN. These resonances can be minimized by optimizing the placement of the P/G TPVs that are used to interconnect the planes. The use of thinner build-up layers (1 5 μm) was also shown to provide complete suppression of P/G resonances across a wide-frequency range. A comparison between the different PDN resonance suppression techniques that were investigated in this paper is

8 94 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 1, JANUARY 2016 TABLE II S UMMARY OF R ESONANCE S UPPRESSION T ECHNIQUES Fig. 17. variation. Self-impedance comparison of 3-D PDN build-up thickness Fig. 19. Stack-up of (a) 100-μm four metal layer and (b) 30-μm two metal layer glass. IV. T EST V EHICLE FABRICATION AND C HARACTERIZATION Test vehicles were fabricated on a 150 mm 150 mm glass substrate, using panel-based double-side processes [11] to study the PDN impedance profile of the proposed glassbased 3-D interposer. The glass core was laminated with a 17.5-μm-thick ZIF polymer. The polymer layer acts a stress buffer layer and also improves the handling [11]. Electrolytic plating was used to achieve a copper thickness of 8 10 μm. Following the fabrication of the substrate, measurements were performed using a vector network analyzer with 250-μm-pitch probes, after short-open-load-through calibration. A two-port self-impedance measurement technique was used to achieve milliohm-scale accuracy [40]. Fig. 18. Comparison of 3-D interposer resonance suppression techniques. A. Measurement of Power-Ground Plane Self-Impedance shown in Fig. 18. It can be seen that using various design methods, PDN resonances in 3-D interposer can be completely suppressed, and thereby improving the PDN BW. The different methods are summarized in Table II. To characterize the self-impedance of P/G planes in the glass interposer, two stack-up configurations were employed: 1) a glass core of thickness 100 μm, having four metal layers and 2) an ultrathin glass core of thickness 30 μm, having

9 KUMAR et al.: DESIGN AND DEMONSTRATION OF PDNs WITH EFFECTIVE RESONANCE SUPPRESSION 95 Fig. 20. Top view of (a) 100-μm glass test vehicle and (b) 30-μm glass test vehicle showing port locations. Fig. 21. Measured self-impedance (Z11) for 17 mm 17 mm P/G planes across 100-μm glass. two metal layers. The dimensions of the interposers were 17 mm 17mmand10mm 10 mm, respectively. The schematic cross section of the stack-up for each configuration is shown in Fig. 19. The P/G planes were fabricated on either side of the polymer-laminated glass core containing TPVs. The details of the individual P/G plane coupons and port locations are shown in Fig. 20. The sample was probed on the top metal layer (M1) as shown in Fig. 20(a) using pads connected to the planes through blind vias and TPVs. The self-impedance (Z11) measured at the center of the 17 mm 17 mm P/G planes, across the 100-μm-thick glass is plotted in Fig. 21. The mode resonances were in agreement with the simulation results. The shift in the first series resonance of the measured impedance can be attributed to variation of the metal thickness and that of the dielectric layers during fabrication. Overall, there was good correlation between the simulated and measured responses. The magnitude of the mode-resonant peaks in the measured results was suppressed due to the contact resistance of the probe pads. P/G planes of dimensions 10 mm 10 mm were fabricated using ultrathin glass having a thickness of 30 μm; to demonstrate the effects of change in interposer stack-up, on the PDN self-impedance. The self-impedance and transfer impedance (Z21) measured at ports located near the edge of the P/G planes, are shown in in Fig. 20(b). This was used to study the overall plane impedance. These results are shown in Fig. 22. There was excellent correlation between the measured and simulated responses for both plots. The capacitance and inductance of the PDN were lower owing to the smaller size of the planes, leading to a shift of the mode-resonances to higher frequencies. The improved suppression in this case occurs due to the thickness reduction between the P/G layers, when compared with the previous 100-μm-thick glass. The effect of P/G plane size variation in glass substrates was studied in Fig. 23. The measured self-impedance of three Fig. 22. Measured (a) self (Z11) and (b) transfer (Z21) impedance for 10 mm 10 mm P/G planes across 30-μm glass. different substrate sizes were compared with the ports located near 0.5 mm inside the central edge. A smaller interposer size (7.5 mm 7.5 mm) was added to this comparison based on the 30-μm-thick glass stack-up. The smaller size (7.5 mm 7.5 mm) of the interposer resonates at a much higher frequency compared with larger interposers, due to the change in resonance cavity dimensions. This technique is different from the layer thickness reduction in the previous example. However, there is also a reduction in the total plane capacitance with smaller size P/G planes, similar to the observation in the previous example.

10 96 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 1, JANUARY 2016 Fig. 23. Comparison of measured self-impedance (Z11) for P/G planes of multiple sizes across 100 and 30-μm glass. Fig. 24. Cross section of SMT decoupling capacitor placement on P/G planes in 100-μm glass interposer. Fig. 26. Measured self-impedance (Z11) comparison of mm 2 P/G planes with decoupling capacitors. 100-μm-thick sample. Two capacitors were mounted on each pad to reduce the ESR, and were connected to P/G planes using TPVs. The cross section of the decoupling capacitor after mounting is shown in Fig. 24. The measurement was performed at the center of the plane, with the capacitor SMT pads located 2.5 mm away from the edge of the planes, as shown in Fig. 25. This location was chosen in order to represent a 3-D-PDN configuration with a bottom mounted die, which restricts the placement of the land side capacitors near the center of the interposer. The self-impedance with and without decoupling capacitors is compared in Fig. 26. The capacitors effected decoupling at frequencies below 1 GHz. However, at 1.4 GHz, a new high-impedance peak was created due to parallel resonance between the package P/G plane capacitance and the combined ESL of the capacitors, mounting pads, blind vias, and TPVs. The 1.2-pF capacitors did not suppress high frequency resonances due to the ESL and the large trace length between the point of mounting and the center probe. Thus, SMT-type decoupling capacitors were not effective in reducing the inductive impedance at gigahertz frequencies, where additional high-impedance peaks are generated in 3-D interposers. This indicates that the placement of decoupling capacitors must be carefully designed for 3-D glass interposers. Fig. 25. Decoupling capacitor placement on P/G planes (a) top view and (b) probe arrangement. B. Resonance Supression With Discrete Decoupling Capacitors To verify the impact of decoupling capacitors on resonance suppression, four SMT-type decoupling capacitors (2 1nF and pf) were mounted on the top layer of the C. Characterization of 2-D- and 3-D-PDN Impedance Test coupons having BGA pads on the M4 metal layer were designed on 100-μm-thick glass substrates, to compare the self-impedance of 2-D and 3-D glass package PDN. In both cases, the 17 mm 17 mm planes were modified to have an array of BGA pads at a pitch of 500 μm. The top view of the 2-D- and 3-D-PDN P/G plane coupons and BGA locations are shown in Fig. 27. The 2-D interposer was designed with a BGA array having a total of 730 P/G BGAs. Of these, 170 P/G BGAs located at the center of the interposer provided a direct PDN path to the PWB. These P/G BGA pads located within the 10 mm 10 mm area were removed to represent the 3-D interposer PDN schematic, resulting in 560 P/G BGA connections.

11 KUMAR et al.: DESIGN AND DEMONSTRATION OF PDNs WITH EFFECTIVE RESONANCE SUPPRESSION 97 Fig. 27. (a) 2-D and (b) 3-D interposer PDN design with bottom view. was modeled using multiport full-wave 3-D EM simulations. Additional resonances were observed near 7.3 GHz, due to the interaction of the increased lateral inductance with the resonant cavity. These high-impedance peaks in the PDN profile of 3-D interposer systems were observed to be mitigated due to the domination of the on-chip capacitance at gigahertz frequencies. Nevertheless, suppression methods were necessary to meet the target-impedance guidelines and reduce SSN. Three primary design techniques to address this problem were proposed and studied. Placing low-esl decoupling capacitors was effective in reducing impedance within the GHz range. Providing central P/G connections using more than one die at the underside of the glass interposer was most effective to suppress the high-impedance resonance peaks beyond 5 GHz. In addition, the magnitude of the inductive impedance was reduced by over 10 through a four-metal layer P/G plane structure. 30-and 100-μm-thin glass test vehicles were fabricated and characterized to demonstrate the validity of the modeling and analysis results. The first measured comparison of PDN impedance between 2-D and 3-D glass substrates was also presented with excellent modelto-hardware correlation. In summary, this paper demonstrated power integrity in ultrathin glass substrates with TPVs to enable a simpler approach for achieving high I/O high BW compared with 3-D-ICs with TSVs. REFERENCES Fig. 28. Measured self-impedance of 2-D glass package and 3-D interposer. In order to simulate the effects of an ideal VRM and PWB and extract the effective impedance as seen from on-chip PDN, all the BGA pads were shorted using sputtered copper having thickness of 1 3 μm. The characterization for both PDN scenarios is shown Fig. 28. The 3-D interposer PDN exhibited an overall increase in inductive impedance when compared with the 2-D scenario due to the lateral inductive path. In addition, a new high-impedance peak occurred at 7.4 GHz, which directly correlates the 3-D-PDN simulation results. This impedance peak was not prominent in 2-D-PDN configuration due to reduced inductance arising from the presence of central P/G interconnections exactly under the center (on-chip) probing location on the other side of the substrate. The high-impedance peak in 3-D PDN was not observed at frequencies below 7 GHz due to the small value of the lateral trace inductance. Hence, the 3-D-PDN structure can meet the target impedance profile for core-pdn design without significant impact, due to negligible current requirement at gigahertz frequencies. V. CONCLUSION This paper studied the design and demonstration of PDN resonances and effective suppression techniques in ultrathin and double-sided 3-D glass BGA interposer packages for high-bw applications. A 17 mm 17 mm 3-D interposer PDN [1] P. Stanley-Marbell, V. C. Cabezas, and R. P. Luijten, Pinned to the walls Impact of packaging and application properties on the memory and power walls, in Proc. Int. Symp. Low Power Electron. Design (ISLPED), Aug. 2011, pp [2] H. Vuong. (2013). Mobile Memory Technology Roadmap. [Online]. Available: _Forum_May_2013.pdf [3] K. Fukuoka et al., Challenges of design and packaging for 3D stacking with logic and DRAM dies, in Proc. Int. Conf. Electron. Packag. (ICEP), Apr. 2014, pp [4] J.-S. Kim et al., A 1.2 V 12.8 GB/s 2 Gb mobile wide-i/o DRAM with I/Os using TSV based stacking, IEEE J. Solid-State Circuits, vol. 47, no. 1, pp , Jan [5] J. West, Y. S. Choi, and C. Vartuli, Practical implications of via-middle Cu TSV-induced stress in a 28 nm CMOS technology for wide-io logicmemory interconnect, in Proc. Symp. VLSI Technol. (VLSIT), Jun. 2012, pp [6] D. H. Kim, S. Mukhopadhyay, and S. K. Lim, TSV-aware interconnect length and power prediction for 3D stacked ICs, in Proc. IEEE Int. Interconnect Technol. Conf. (IITC), Jun. 2009, pp [7] P. Leduca et al., Challenges for 3D IC integration: Bonding quality and thermal management, in Proc. IEEE Int. Interconnect Technol. Conf., Jun. 2007, pp [8] H.-H. S. Lee and K. Chakrabarty, Test challenges for 3D integrated circuits, IEEE Des. Test Comput., vol. 26, no. 5, pp , Sep./Oct [9] C. A. Palesko, E. J. Vardaman, and A. C. Palesko, Cost trade-off analysis of PoP versus 3D TSV, in Proc. IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [10] G. Kumar, T. Bandyopadhyay, V. Sukumaran, V. Sundaram, S. K. Lim, and R. Tummala, Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications, in Proc. IEEE 61st Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2011, pp [11] V. Sukumaran et al., Design, fabrication, and characterization of ultrathin 3-D glass interposers with through-package-vias at same pitch as TSVs in silicon, IEEE Compon., Packag., Manuf. Technol., vol. 4, no. 5, pp , May [12] M. Lee, J. Cho, J. Kim, J. Kim, and J. Kim, Noise coupling of through-via in silicon and glass interposer, in Proc. IEEE 63rd Electron. Compon. Technol. Conf. (ECTC), May 2013, pp

12 98 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 1, JANUARY 2016 [13] B. K. Wang, Y.-A. Chen, A. Shorey, and G. Piech, Thin glass substrates development and integration for through glass vias (TGV) with copper (Cu) interconnects, in Proc. 7th Int. Microsyst., Packag., Assembly Circuits Technol. Conf. (IMPACT), Oct. 2012, pp [14] C.-H. Chien et al., Process, assembly and electromigration characteristics of glass interposer for 3D integration, in Proc. IEEE 64th Electron. Compon. Technol. Conf. (ECTC), May 2014, pp [15] J. Lee, A. C. W. La, W. Fan, L. L. Wai, and J. Kim, Effect of decoupling capacitor on signal integrity in applications with reference plane change, in Proc. 53rd Electron. Compon. Technol. Conf., May 2003, pp [16] J. Fan, M. Cocchini, B. Archambeault, J. L. Knighten, J. L. Drewniak, and S. Connor, Noise coupling between signal and power/ground nets due to signal vias transitioning through power/ground plane pair, in Proc. IEEE Int. Symp. Electromagn. Compat. (EMC), Aug. 2008, pp [17] T. Bandyopadhyay, Modeling, design, and characterization of through vias in silicon and glass interposers, Ph.D. dissertation, Dept. Elect. Comput. Eng., Georgia Inst. Technol., Atlanta, GA, USA, [18] Y. Kim, K. Kim, J. Cho, J. Kim, V. Sundaram, and R. Tummala, Analysis of power distribution network in glass, silicon interposer and PCB, in Proc. IEEE Int. Symp. Electromagn. Compat. (EMC), Aug. 2014, pp [19] V. Sridharan, M. Swaminathan, and T. Bandyopadhyay, Enhancing signal and power integrity using double sided silicon interposer, IEEE Microw. Wireless Compon. Lett., vol. 21, no. 11, pp , Nov [20] B. Xie and M. Swaminathan, Modeling and analysis of SSN in silicon and glass interposers for 3D systems, in Proc. IEEE 21st Conf. Elect. Perform. Electron. Packag. Syst. (EPEPS), Oct. 2012, pp [21] J. Cho, Y. Kim, J. Kim, V. Sundaram, and R. Tummala, Analysis of glass interposer PDN and proposal of PDN resonance suppression methods, in Proc. IEEE Int. 3D Syst. Integr. Conf. (3DIC), Oct. 2013, pp [22] C. M. Smutzer, B. K. Gilbert, and E. S. Daniel, Practical limitations of state-of-the-art passive printed circuit board power delivery networks for high performance compute systems, in Proc. 17th IEEE Workshop Signal Power Integrity (SPI), May 2013, pp [23] W. L. Lee, H. N. Low, and H. Shi, Investigation to effectiveness of design factors for FPGA package PDN networks, in Proc. 11th Electron. Packag. Technol. Conf. (EPTC), Dec. 2009, pp [24] C.-H. Lin, C.-C. Wang, and H.-Y. Wang, System power integrity impact by package power/ground balls assignment and decoupling capacitors, in Proc. Asia-Pacific Symp. Electromagn. Compat. (APEMC), May 2012, pp [25] M. Yamada, M. Nishiyama, T. Tokaichi, and M. Okano, Packaging technology for the NEC ACOS system 3900, in Proc. 42nd Electron. Compon. Technol. Conf., May 1992, pp [26] Y. Kurita et al., A novel SMAFTI package for inter-chip wide-band data transfer, in Proc. 56th Electron. Compon. Technol. Conf., 2006, pp [27] Y. Kurita et al., Vertical integration of stacked DRAM and high-speed logic device using SMAFTI technology, IEEE Trans. Adv. Packag., vol. 32, no. 3, pp , Aug [28] W. Beyene et al., Signal and power integrity analysis of a 256-GB/s double-sided IC package with a memory controller and 3D stacked DRAM, in Proc. IEEE 63rd Electron. Compon. Technol. Conf. (ECTC), May 2013, pp [29] D. Secker, M. Ji, J. Wilson, S. Best, M. Li, and J. Cline, Co-design and optimization of a 256-GB/s 3D IC package with a controller and stacked DRAM, in Proc. IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [30] X. Liu, M. Li, D. Mullen, J. Cline, and S. K. Sitaraman, Design and assembly of a double-sided 3D package with a controller and a DRAM stack, in Proc. IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [31] P.-J. Tzeng et al., Process integration of 3D Si interposer with doublesided active chip attachments, in Proc. IEEE 63rd Electron. Compon. Technol. Conf. (ECTC), May 2013, pp [32] A. Sakai et al., PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations, in Proc. 2nd IEEE CPMT Symp. Jpn., Dec. 2012, pp [33] L. Li et al., Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration, in Proc. IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [34] V. Sundaram, Q. Chen, Y. Suzuki, G. Kumar, F. Liu, and R. Tummala, Low-cost and low-loss 3D silicon interposer for high bandwidth logicto-memory interconnections without TSV in the logic IC, in Proc. IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [35] G. Kumar et al., Power delivery network analysis of 3D double-side glass interposers for high bandwidth applications, in Proc. IEEE 63rd Electron. Compon. Technol. Conf. (ECTC), May 2013, pp [36] G. Kumar et al., Coaxial through-package-vias (TPVs) for enhancing power integrity in 3D double-side glass interposers, in Proc. IEEE 64th Electron. Compon. Technol. Conf. (ECTC), May 2014, pp [37] S. Gandhi, S. Xiang, P. M. Raj, V. Sundaram, M. Swaminathan, and R. Tummala, A low-cost approach to high-k thinfilm decoupling capacitors on silicon and glass interposers, in Proc. IEEE 62nd Electron. Compon. Technol. Conf (ECTC), May/Jun. 2012, pp [38] G. Kim et al., Package embedded decoupling capacitor impact on core power delivery network for ARM SoC application, in Proc. IEEE 64th Electron. Compon. Technol. Conf. (ECTC), May 2014, pp [39] H. Kim, B. K. Sun, and J. Kim, Suppression of GHz range power/ground inductive impedance and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs, IEEE Microw. Wireless Compon. Lett., vol. 14, no. 2, pp , Feb [40] I. Novak, Probes and setup for measuring power-plane impedances with vector network analyzer, in Proc. DesignCon, 1999, pp Gokul Kumar received the B.E. degree from Anna University, Chennai, India, and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA. He developed glass interposers for the research consortia with the 3-D Systems Packaging Research Center, Atlanta, during the Ph.D. degree under the guidance of Prof. R. R. Tummala. He was with Qualcomm MEMS Technology, San Jose, CA, USA, as an Interim Engineering Intern, in His current research interests include the design and development of glass, silicon, and organic interposers for 3-D system integration. Srikrishna Sitaraman received the B.E. degree in electronics and communications engineering from Anna University, Chennai, India, in 2010, and the M.S. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2012, where he is currently pursuing the Ph.D. degree with the 3-D Systems Packaging Research Center under the guidance of Prof.R.R.Tummala. He was with Intel Corporation, Phoenix, AZ, USA, as a Packaging Engineering Intern, in His current research interests include modeling, design, and demonstration of ultraminiaturized high-performance wireless LAN radio frequency packages using 3-D organic and glass substrates. Jonghyun Cho received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2008, 2010, and 2013, respectively. He held a post-doctoral position with KAIST until He is currently with the EMC Laboratory, Missouri S&T, Rolla, MO, USA, as a Visiting Assistant Research Professor. His research is focused on de-embedding and sensitivity analysis. His current research interests include signal and power integrity issues for chip-package-printed Circuit Board systems.

13 KUMAR et al.: DESIGN AND DEMONSTRATION OF PDNs WITH EFFECTIVE RESONANCE SUPPRESSION 99 Venky Sundaram received the B.S. degree from IIT Bombay, Mumbai, India, and the M.S. and Ph.D. degrees in materials science and engineering from the Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA. He is currently the Director of Research and Industry Relations with the 3-D Systems Packaging Research Center, Georgia Tech. He is the Program Director of the low-cost glass interposer and packages industry consortium with more than 25 active global industry members. He is a Globally Recognized Expert in packaging technology and the Co-Founder of Jacket Micro Devices, Decatur, GA, USA, an RF/wireless start-up acquired by AVX. He has authored 100 publications and holds over 15 patents. His current research interests include system-on-a-package technology, 3-D packaging and integration, ultrahigh-density interposers, embedded components, and systems integration research. Dr. Sundaram has received several best paper awards. He is the Co-Chairman of the IEEE CPMT Technical Committee on High Density Substrates and is in the Executive Council of the International Microelectronics Assembly and Packaging Society as the Director of Education Programs. Joungho Kim (A 04 M 08) received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in He joined the Memory Division, Samsung Electronics, Suwon, Korea, in 1994, where he was involved in gigabit-scale DRAM design. In 1996, he moved to the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently a Professor with the Department of Electrical Engineering and Computer Science. In addition, he has given more than 105 invited talks and tutorials in academia and related industries. In particular, his major research topic focuses on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3-D semiconductor packages, system-in-package, and system-on-a-package. He has authored or co-authored over 230 technical papers in refereed journals and conference proceedings. His current research interests include modeling, design, and measurement methodologies of hierarchical semiconductor systems, including high-speed chips, packages, interconnections, and multilayer printed circuit boards. Dr. Kim received the Annual Faculty Outstanding Academic Achievement Award from KAIST in Since 2002, he has been the Chair or Co-Chair of the Electrical Design of Advanced Packaging and Systems Workshop. He is an Associate Editor of the IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY. Rao R. Tummala (F 93) received the B.S. degree from the Indian Institute of Science, Bangalore, India, and the Ph.D. degree from the University of Illinois at Urbana Champaign, Champaign, IL, USA. He was an IBM Fellow, pioneering the first plasma display and multichip electronics for mainframes and servers. He is currently a Distinguished and Endowed Chair Professor, and the Founding Director of the National Science Foundation Engineering Research Center with the Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA, pioneering Moore s law for system integration. He has authored about 500 technical papers, the first modern book entitled Microelectronics Packaging Handbook, the first undergraduate textbook entitled Fundamentals of Microsystems Packaging, and the first book entitled Introducing to System-on-Package Technology, and holds 74 patents and inventions. Prof. Tummala is a member of the National Academy of Engineering, and was the President of the IEEE Components, Packaging, and Manufacturing Technology Society and the International Electronic Packaging Society. He has received many industry, academic, and professional society awards, including the Industry Week s Award for improving U.S. competitiveness, the IEEE s David Sarnoff Award, the IMAPS Dan Hughes Award, the Engineering Materials Award from ASM, and the Total Excellence in Manufacturing Award from SME. He received the Distinguished Alumni Awards from the University of Illinois at Urbana Champaign, the Indian Institute of Science, and Georgia Tech. In 2011, he was a recipient of the Technovisionary Award from the Indian Semiconductor Association and the IEEE Field Award for contributions in electronics systems integration and cross-disciplinary education.