DUE TO the increasing need for cost-effective and multifunctional

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1 178 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 1, JANUARY 2008 Analysis and Modeling of Hybrid Planar-Type Electromagnetic-Bandgap Structures and Feasibility Study on Power Distribution Network Applications Ki Hyuk Kim, Member, IEEE, and José E. Schutt-Ainé, Fellow, IEEE Abstract A unified 1-D analysis model of hybrid planar-type electromagnetic-bandgap (EBG) structures is developed. Based on the analysis results, three types of hybrid design methods to reduce the cutoff frequency of the EBG structures are discussed, and design equations for their noise suppression bandwidths are derived. In order to simulate switching noise characteristics of the hybrid planar-type EBG structures, 2-D circuit level models are developed and experimentally verified. With the developed circuit-level models and CMOS active switching devices, feasibility studies on the power distribution network design using the hybrid EBG structures are conducted. The hybrid EBG structure with series lumped chip inductors shows efficient noise suppression characteristics in both the frequency and time domains; however, it has potential limitations because of its generation of higher switching noise voltages depending on power supply connection configurations. Index Terms Electromagnetic bandgap (EBG), power distribution network (PDN), simultaneous switching noise (SSN), system-in-package/system-on-package. I. INTRODUCTION DUE TO the increasing need for cost-effective and multifunctional electronic components, integration schemes using system-in-package or system-on-package technology have been widely researched [1]. One of the critical design issues of such high-density systems is the reduction of noise coupling between neighboring functional blocks, e.g., noisy digital and sensitive analog/rf circuits in the same system. In addition, continuous device scaling results in the reduction of supply voltage levels and corresponding noise margins, as a result, the intra-noise coupling in the digital block also degrades the performances of the digital circuit. Inductive simultaneous switching noise (SSN) generated by the digital circuits can propagate through both the on-chip and the package/printed circuit board (PCB) level substrates. However, fundamental mechanisms of the noise propagations are quite different; the noise signal in the on-chip substrate propagates through resistive paths of the substrate, and the sources of the package/pcb level noise coupling are cavity resonant modes of the power distribution network (PDN) on the substrate. The PDN forms the rectangular cavity resonator, which has two parallel metal patches and four magnetic sidewalls [2]. In the Manuscript received May 24, 2007; revised September 8, The authors are with the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL USA ( khkim@emlab.uiuc.edu; jschutt@emlab.uiuc.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TMTT vicinity of the resonant frequencies, vertical transitions of the noisy signals such as time varying power/ground via pins and vias of high-speed signals excite the cavity resonator structure and create standing waves. Such electromagnetically coupled noise signals can be minimized using a gapped-/island-type PDN [3], a resistive termination method [4], and efficient bypassing techniques such as shorting vias and capacitive walls [5]. However, their practical implementations are limited by the multiple power supply requirements, narrow operating bandwidths, and large number of additional passive components. Several mushroom- and planar-type electromagneticbandgap (EBG) structures are proposed to suppress the cavity resonant modes and the noise signal propagations on the package/pcb substrate [6] [9]. However, it is difficult to design the EBG structures, which have low cutoff frequency and wide stopband characteristics because of the low inductances of the vias/bridges and the low capacitances of the patches. Recently, several planar-type EBG structures have been proposed to reduce the cutoff frequency, and most of the efforts are focused on increasing bridge inductances between patches by extending the lengths of the microstrip line bridges [8], [9]. Two hybrid planar-type EBG structures were also proposed; one increases the patch capacitances by using lumped chip capacitors [10], and the other increases the bridge inductances by using lumped chip inductors [11]. In this paper, a 1-D analysis of the hybrid planar-type EBG structures is conducted, and three types of hybrid EBG structure design methods to reduce the cutoff frequency are discussed. Noise suppression bandwidths for various enhanced hybrid planar-type EBG structures are derived using this analysis. In Section III, 2-D circuit-level models of the hybrid planar-type EBG structures are developed in order to include distributed effects of the EBG structures and co-simulate with actual digital and analog/rf circuits. Accuracies of the developed simulation models are experimentally verified by comparing the simulated -parameter responses with the measured data. A feasibility study of the application of the hybrid planartype EBG structures to the design of the PDN is conducted in Section IV. 16-bit CMOS output drivers are co-simulated with the hybrid cutoff frequency-enhanced EBG PDN in both the frequency and time domains. Not only the noise suppression characteristics, but also the noise generation characteristics of the PDNs are discussed in order to explore the SSN characteristics of each hybrid EBG structure /$ IEEE

2 KIM AND SCHUTT-AINÉ: ANALYSIS AND MODELING OF HYBRID PLANAR-TYPE EBG STRUCTURES AND FEASIBILITY STUDY ON PDN APPLICATIONS 179 where is the width of the microstrip line and is equal to 0.2 nh/mm. also varies depending on the physical implementation of the bridges. Typical values for, which is the largest when implemented using the lumped chip inductors are less than 0.3 pf for inductance in the nH range [14], while typical values for are in the range of nh including the inductances of the via [15], which is calculated using (5) [16] as follows: Fig. 1. Schematics of 1-D hybrid planar-type EBG PDN and corresponding equivalent circuits. II. 1-D ANALYSIS OF HYBRID PLANAR-TYPE EBG STRUCTURES A. Description of 1-D Hybrid Planar-Type EBG Structures Fig. 1 shows schematics of the th unit cell of the 1-D hybrid planar-type EBG structure and corresponding lumped equivalent-circuit models including all hybrid components and parasitics. The lumped circuit approximation is valid for metal patches with a width of less than one-tenth of the guided wavelength in the patches. Components within the dotted rectangle correspond to the th unit cell of the EBG structure, where and are the center-to-center and gap distance between two neighboring metal patches, respectively, is the width of the rectangular metal patches, and is the height of the dielectric substrate. The th unit cell consists of half of the th patch, one bridge, and half of the th patch. and are the inductance and capacitance of each metal patch, respectively, is the gap capacitance between metal patches, and and are the parasitic series capacitance and the inductance of the bridge, respectively. and are the capacitance and parasitic inductance of the lumped chip capacitors, respectively. The values of and are calculated using the following quasi-static equations [12]: where and are the permittivity and permeability of free space, respectively, and is the relative dielectric constant of the substrate. Equation (3) is used to calculate the gap capacitances between the patches [8] and [13] is equal to the inductance of the microstrip lines between the patches or that of the lumped chip inductors depending on the physical implementation of the bridges. The inductance of the microstrip lines per unit length is given by (1) (2) (3) (4) where is the diameter of the via in millimeters and is equal to 0.2 nh/mm. It is important to note that the capacitance ratios of and are very small for typical package/pcb structures, which have large patch width and low substrate thickness. B. Frequency Response of 1-D Planar-Type EBG Structures The image parameter method [12] is used to analyze the frequency responses of the 1-D hybrid planar-type EBG structure. The image impedance of the EBG structure is given by where and (5) (6a) (6b) (6c) (6d) The previous two capacitance ratios are used to derive the noise suppression bandwidths of the hybrid planar-type EBG structures. Noise suppression bandwidth is defined as the difference between the low-pass cutoff frequency ( ) and the high-frequency limitation of the EBG structures. The derived equations show that s are only dependent on the values of ( ),, and. Therefore, there are three different hybrid design methods to reduce the cutoff frequency of the planar-type EBG structures, and the derived and high-frequency limitations of each hybrid planar-type EBG structure are summarized in Table I. It is important to note that the EBG structure used in method 3 has an additional passband due to the parallel resonance of and, which limits the noise suppression bandwidth, and that the first resonant frequency of the EBG structure used in method 4 is lower than those of other EBG structures because of its high dielectric constant. The maximum noise suppression level,, is derived using a periodic -stage pi-type equivalent model, which

3 180 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 1, JANUARY 2008 TABLE I NOISE SUPPRESSION BANDWIDTHS OF CUTOFF FREQUENCY-ENHANCED HYBRID PLANAR-TYPE EBG STRUCTURES consists of the shunt and series and (7) where is the number of unit cells and. Impedance mismatches between the unit cells are not considered in the derivation. In order to predict the dispersive behavior of the hybrid planar-type EBG structures, the unit cells of each structure are analyzed using parameters [13], which is given by Fig. 2. First passband of dispersion diagram for hybrid planar-type EBG structures with parameters b =13:7 mm, g =1:3 mm, h =0:4 mm, " =4:4, C =0:103 pf, and L =1nH. (a) Using method 2 with variable of L. (b) Using method 3 with variable of C. are as follows: (9) (10) where and are the effective phase constant of the unit cell and the phase constant of the patch, respectively, and and (8) Fig. 2(a) and (b) shows the first passband of the dispersion diagram for the hybrid planar-type EBG structure using method 2 with a variable of and that for the hybrid planar-type EBG structure using method 3 with a variable of, respectively. In both cases, it is shown that, by increasing, the cutoff frequency of the hybrid planar-type EBG structure is effectively reduced and the cutoff frequencies of each structure from the dispersion diagram are in good agreement with the calculated values using (7b) and (7c).

4 KIM AND SCHUTT-AINÉ: ANALYSIS AND MODELING OF HYBRID PLANAR-TYPE EBG STRUCTURES AND FEASIBILITY STUDY ON PDN APPLICATIONS 181 Fig. 3. Schematics and corresponding equivalent-circuit models for building blocks of hybrid planar-type EBG structures. (a) Patch. (b) Gap and bridge. (c) Lumped chip inductor. (d) Lumped chip capacitor. Synthesized EBG structure: (e) using method 2 and (f) using method 3. III. CIRCUIT-LEVEL MODELING OF HYBRID PLANAR-TYPE EBG STRUCTURES 2-D equivalent-circuit models of the planar-type EBG structures are developed in order to include their distributed effects and co-simulate the hybrid planar-type EBG structures with the digital and analog/rf circuits. A commercial circuit-level simulator, Spectre from Cadence Design Systems Inc., San Jose, CA, is used in this study. Fig. 3(a) (d) shows the schematics and equivalent-circuit models for the metal patch (width ), gap and bridge between patches (distance ), lumped chip inductor, and lumped chip capacitor, respectively. They are basic building blocks of the hybrid planar-type EBG structures. Every EBG structure using one of the design methods shown in Table I can be synthesized with those building blocks, e.g., the EBG structure using method 2 consists of an array of metal patches and the gap with lumped chip inductors, while the EBG structure using method 3 consists of an array of metal patches with lumped chip capacitors and the gap between the patches. Fig. 3(e) and (f) shows the 2-D circuit level simulation models of the EBG structures using methods 2 and 3, respectively. The details of the equivalent-circuit models are explained as follows. A. Circuit-Level Modeling of Metal Patches Fig. 3(a) shows the circuit-level model of the metal patch. Instead of the conventional merged plane models, the distributed plane models are used for the patch in order to describe the current voltage variations on the ground and power planes [17]. An array of RLC cells is used to model each patch, where is dependent of the guided wavelength in the substrate and, in this study, is equal to 10. The dielectric constant of the substrate is 4.4, the maximum analysis frequency is 6 GHz, and the size of the RLC cell is an approximate 1/20 of the guided wavelength at the maximum frequency. B. Circuit-Level Modeling of Gap Between Patches Fig. 3(b) shows the circuit-level model of the gap and the bridge between the patches. Nine-section distributed capacitors and a single-section inductor are used to model the gap capacitance and the inductance of the microstrip line bridge. In the case where the lumped chip inductor is used as the bridge, the inductor model of the microstrip line is replaced by the lumped chip inductor model in Fig. 3(c). Previous studies on planar-type EBG structures use (3) to calculate the gap capacitances [8], [13]; (3), however, was derived under the assumption that there is only a pair of patches without the ground plane [18]. This assumption is true for the mushroom-type EBG power plane without the ground plane because the metal patches are connected to the power plane through vias. However, in the case of the planar-type EBG structures, the presence of the ground plane reduces the value of. In [19], equations for the coupled microstrip lines are used to calculate the gap capacitances with the ground plane considered, and details of design formulas are found in [20]. Fig. 4(a) and (b) shows the calculated and simulated values of the gap capacitances for the planar-type EBG structures with the center-to-center distances of 15 and 30 mm, respectively. The thickness of the dielectric substrate vary from 0.4 to 1.6 mm with 0.4-mm steps, and the gap distances are 5%, 7.5%, and 10% of the patch widths. Equation (3) and the equations in [20] are used to calculate the gap capacitances, and Maxwell 2-D SV, a commercial 2-D quasi-static R, L, and C extractor from the Ansoft Corporation, Pittsburgh, PA, is used to numerically simulate the gap capacitances. Both of the analytic equations overestimate the gap capacitances, as shown in Fig. 4. The calculated gap capacitances using (3) is independent with the height of the dielectric substrate because the ground plane is not considered in the derivation of (3) [18]. Equations for the gap capacitances in [20] were obtained empirically with limited ranges of the physical dimensions that are applicable to microstrip lines. As a result, the calculated gap capacitances between the large width coupled patches are not accurate. As expected, the calculation

5 182 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 1, JANUARY 2008 TABLE II DESIGN PARAMETERS OF HYBRID PLANAR-TYPE EBG PDNS Fig. 4. Calculated and simulated values of gap capacitances. (a) a =15mm. (b) a =30mm. Fig. 5. EBG structure using method 2. (a) Fabricated PCB. (b) Simulated and measured js21j responses. errors are inversely proportional to the heights of the dielectric substrate. In this study, the numerically simulated gap capacitances are used to model. C. Circuit-Level Modeling of Lumped Chip Inductors and Capacitors First-order parallel LC and first-order series LC models are used to model the lumped chip inductors and lumped chip capacitors, respectively. The parasitic parallel capacitances of the lumped chip inductor and the parasitic series inductances of the lumped chip capacitor are calculated using their self resonant frequencies (SRFs) provided by the chip components vendors [14], [15]. Fig. 3(c) and (d) shows the circuit level of the lumped chip inductor and lumped chip capacitor, respectively. Fig. 6. Frequency-domain characteristics of hybrid EBG PDNs. (a) js21j responses of EBG PDN using method 2. (b) js21j responses of EBG PDN using method 3. D. Verification of Circuit Level Models for Hybrid Planar-Type EBG Structures The accuracy of the developed 2-D circuit level simulation models is experimentally verified. Fig. 5(a) shows the fabricated hybrid planar-type EBG structure using method 2 in Table I. The width of the patch and the gap distance between the patches are 13.7 and 1.3 mm, respectively. The thickness and dielectric constant of the substrate are 0.4 and 4.4 mm, respectively. Locations of two measurement ports are also shown in Fig. 5(a). Twelve 560-nH lumped chip inductors with 0.16-pF parasitic series capacitance are used as the bridges.

6 KIM AND SCHUTT-AINÉ: ANALYSIS AND MODELING OF HYBRID PLANAR-TYPE EBG STRUCTURES AND FEASIBILITY STUDY ON PDN APPLICATIONS 183 Fig. 7. Chip-PDN co-simulations. (a) 16-bit output drivers. (b) Input voltage waveforms with 500- and 2500-ps rise times. (c) Output voltage waveforms. (d) Transient short-circuit currents. (e) 2-D solid PDN. (f) Hybrid EBG PDN using method 2/method 3. Fig. 5(b) shows the measured and simulated frequency responses of the EBG structure and a 2-D solid plane pair, which has the same area as that of the ground plane of the EBG structure. The Agilent E8358A PNA series vector network analyzer (VNA) is used to measure the -parameters from 300 khz to 6 GHz. Solid lines and the crosses correspond to simulated and measured responses for the 2-D solid plane pair, respectively, while solid rectangles and open circles represent the same respective quantities for the EBG structure. The 2-D circuit level simulations accurately predict the measured responses of both of the EBG structures, except for the levels of the insertion loss. The calculated maximum insertion loss using (7) is 130 db, which shows a good agreement with the 2-D simulation results. The discrepancy in the noise suppression levels is due to the noise floor of the VNA. The measured, which is defined as a frequency where the responses start to decrease monotonically, is MHz, while the calculated and the simulated values are 99.4 and 99.5 MHz, respectively. In Fig. 5(b), the measured peak of the EBG structure at 5.14 GHz, corresponds to the resonant mode of the patches, which have an area of mm, while several resonant peaks of the 2-D solid plane pair correspond to the cavity resonant modes of the mm area patch. Basically, the hybrid planar-type EBG structures enhance the noise suppression bandwidth by reducing the width of the unit cells and, consequently, by moving the first resonant frequency higher [11] and [21]. IV. FEASIBILITY STUDY ON POWER DISTRIBUTION NETWORK DESIGN APPLICATION Previous studies on PDN design using EBG structures have considered only the noise signal suppression characteristics of the EBG structures by measuring insertion losses such as responses. Here, three different cutoff frequency-enhanced hybrid planar-type EBG structures using methods 2 4 are designed, and their feasibility for PDN application are studied using both the frequency- and time-domain simulations with the noise generation characteristics of the EBG structures considered by including CMOS active switching devices in the time-domain simulations. A. Noise Suppression Characteristics and EBG PDN Frequency-Domain Analysis We arbitrarily set the target cutoff frequency of the EBG PDNs to be 300 MHz, and the calculated circuit-level parameters of each EBG PDN using the derived equations in Section II are summarized in Table II. It is important to note that the dielectric constant of 269 in Table II is not a realistic value, moreover, the high dielectric constant with the same patch width of the patch results in lowered, which limits the noise suppression bandwidth of the EBG PDN. The first resonant frequency of that structure is only 668 MHz, and for such reasons, the EBG PDN using method 4 is excluded in this study. High dielectric constant embedded capacitors also have limited noise suppression bandwidths due to the same reason. The schematics and the 2-D circuit-level simulation models of each EBG PDN are shown in Fig. 3(e) and (f), and the locations of ports 1 and 2 are (5 mm, 5 mm) and (40 mm, 40 mm), respectively. Fig. 6(a) and (b) shows the simulated responses of the hybrid EBG PDNs using the 1-D and 2-D circuit-level models. The simulated s of the EBG PDN using method 2 are 269 MHz (1-D models) and 358 MHz (2-D models), respectively, while the simulated s of the EBG PDN using method 3 are 300 MHz (1-D models) and 270 MHz

7 184 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 1, JANUARY 2008 (2-D models), respectively. They show good correlations with the calculated value of 300 MHz using (7b) and (7c). The noise suppression bandwidth of the EBG PDN using method 2 is limited by the first resonant frequency of the patches, which is equal to 5.14 GHz. However, that of the EBG PDN using method 3 is limited by the parallel resonant frequency of and, which is equal to 1.18 GHz. The bandwidth of the passband is determined by the coupling factor between the parallel resonators, which is equal to plus. B. PDN Applications of Each EBG Structure Time-Domain Analysis In order to study the feasibilities of the PDN applications, the developed 2-D circuit level simulation models of the EBG PDNs are incorporated with 16-bit output drivers, which are designed using United Microelectronics Corporation (UMC) m digital CMOS technology, and are supposed to generate the SSN. Including the active circuits results in more realistic switching noise characteristics of the EBG PDNs because the noise generation characteristics are considered. Packaging related parasitic components such as pad capacitance and bond-wire or lead-frame inductance are not included in the simulations. Only parasitics of the PDN are considered. Fig. 7 shows the schematics of the chip-pdn co-simulation environments including: (a) the CMOS 16-bit output drivers, (b) the input voltage waveforms with 500- and 2500-ps rise times, (c) the output voltage waveforms, and (d) the short-circuit transient current waveforms, respectively. The input voltages with 500- and 2500-ps rise times result in the short-circuit transient currents with 106- and 735-ps rise times, which correspond to signal bandwidths of 3.3 GHz and 476 MHz, respectively. The output drivers are designed using CMOS inverters, which have dimensions of 80 m/0.13 m for pmos and 40 m/0.13 m for NMOS. VDD_SUPPLY and GND_SUPPLY stand for the locations of the VDD and GND connections between the dc power supply and the PDN, respectively, while VDD_CHIP and GND_CHIP are the locations of the VDD and GND connections between the PDN and the chip, which embed the CMOS 16-bit output drivers. By co-simulating the PDNs with the output drivers, the noise generation characteristics, as well as the noise suppression characteristics, can be analyzed. Three different types of PDNs are considered. Fig. 7(e) shows the schematics of the 2-D solid plane pair PDN and Fig. 7(f) shows the EBG PDN with the series lumped chip inductors (method 2) or the shunt lumped chip capacitors (method 3). The locations of all ports are also shown in Fig. 7(e). Fig. 8(a) (c) shows the generated (port 1) and propagated (port 4) noise voltages on the 2-D solid PDN, EBG PDN using method 2, and EBG PDN using method 3, respectively for 2500-ps rise time of the input voltages. The VDD_/GND_SUPPLY and VDD_/GND_CHIP connections are located in the same patch; specifically the VDD_/GND_CHIP connections are located at port 1 and the VDD_/GND_SUPPLY connections are located at (0 mm, 5 mm). The generated noise voltages during the transient times are similar to each other; however, the waveforms of the excited Fig. 8. Generated and propagated noise voltages with rise time of 2500 ps. VDD_/GND_CHIP and VDD_/GND_SUPPLY connections are located at the same patch. (a) 2-D solid PDN. (b) EBG PDN using method 2. (c) EBG PDN using method 3. noise voltages are quite different. Due to the wide bandwidth of the transient current, several resonant frequencies are excited, e.g., the excited frequencies of 416 MHz, 1.76 GHz, and 299 MHz correspond to the series resonant frequencies of the VDD_SUPPLY to GND_SUPPLY loop for the 2-D solid PDN, the EBG PDN using method 2, and the EBG PDN using method 3, respectively. In consequence, the wide stopband characteristics of the EBG PDNs are essential to suppress the propagation of the generated switching noise. The EBG PDN using method 2 generates the largest amplitude of switching noise voltage due to its inductive boundary conditions. The amplitudes of the excited noise voltage are dependent on the frequency components of the short-circuit currents and the input impedance at the VDD_/GND_SUPPLY connections. For brevity, only the propagated noise voltages at port 4 on each PDN are plotted. The noise voltage suppression ratios, which are defined as the ratio of the propagated noise voltage of the EBG PDN using method 2 or 3 to that of the 2-D solid plane PDN, are 11% for the EBG PDN using method 2 and 33.3% for the EBG PDN using method 3. The frequencies of the propagated noise voltages correspond to the passband frequencies of the EBG PDNs shown in Fig. 6(a) and (b). Notice that the

8 KIM AND SCHUTT-AINÉ: ANALYSIS AND MODELING OF HYBRID PLANAR-TYPE EBG STRUCTURES AND FEASIBILITY STUDY ON PDN APPLICATIONS 185 TABLE III SUMMARY OF NOISE GENERATION AND SUPPRESSION CHARACTERISTICS OF EBG STRUCTURES USING METHODS 2 AND 3 which are connected at other patches. This increases the effective inductance of the VDD_SUPPLY to VDD_CHIP path of the EBG PDN and corresponding switching noise voltage, which is given by (11) Fig. 9. Generated and propagated noise voltages with rise time of 500 ps. VDD_/GND_CHIP and VDD_/GND_SUPPLY connections are located at the same patch. (a) 2-D solid PDN. (b) EBG PDN using method 2. (c) EBG PDN using method 3. frequencies of the generated noise voltages at port 1 and the propagated noise voltages at port 4 are not identical because the frequencies of the generated noise voltages are dependent on the input impedances at the VDD_/GND_SUPPLY connections. Fig. 9(a) (c) shows the generated (port 1) and propagated (port 4) noise voltages on the 2-D solid PDN, EBG PDN using method 2, and EBG PDN using method 3, respectively for 500-ps rise time of the input voltages. Due to the narrow noise suppression bandwidth of the EBG PDN using method 3, the suppression noise voltage ratio is degraded to 76%. C. Drawback for Hybrid EBG PDN Using Lumped Chip Inductors It is important to note that if the VDD_/GND_SUPPLY and VDD_/GND_CHIP connections are not located in the same patch, then the increased inductance of the VDD_SUPPLY to VDD_CHIP path results in a large amount of switching noise. As shown in Fig. 7(d), the switching current waveforms have wide bandwidth of the frequency components, however, the EBG PDNs block not only the propagation of the switching noise voltages to other patches, but also the sourcing/sinking of the currents from the VDD_/GND_SUPPLY connections, where is the number of the switching gates, is the time derivative of the switching current, and,, and are the effective inductance of the VDD plane, that of the ground plane, and mutual inductance between them of the EBG PDN, respectively. The increased inductance of the VDD_SUPPLY to VDD_CHIP path is a potential limitation of the EBG application to the PDN designs and the hybrid EBG PDN using the lumped chip inductors are only applicable to package designs. Previously published planar-type EBG structures [8], [9] have the same limitations due to the bridge inductances. Table III summarize the switching noise generation and suppression characteristics of EBG structures using method 2 and method 3. V. CONCLUSION In this paper, a 1-D analysis model of the hybrid planar-type EBG structures is developed. Based-on the analysis results, design equations, which define the noise suppression bandwidth of EBG structures, are derived and three different hybrid design methods to reduce the cutoff frequency of the EBG structures are discussed. 2-D circuit-level simulation models are also developed and experimentally verified. Using the developed 2-D circuit-level simulation models, two types of cutoff frequencyenhanced EBG structures are co-simulated with CMOS 16-bit output drivers to study on the feasibilities of the PDN applications. The hybrid EBG PDN using the lumped chip inductors shows efficient noise suppression characteristics in both the frequency and time domains. However, the increased effective inductance between the power supply and active circuits when they are not connected in the same plane results in considerable switching noise voltages, which are potential limitations for the application of PDN design. REFERENCES [1] R. R. Tummala, SOP: What is it and why? A new microsystem-integration technology paradigm-moore s law for system integration of miniaturized convergent systems of the next decade, IEEE Trans. Adv. Packag., vol. 27, no. 2, pp , May 2004.

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Symp., Chicago, IL, Aug. 2005, pp Ki Hyuk Kim (M 05) received the Ph.D. degree in electronics engineering from Korea University, Seoul, Korea, in From 2001 to 2005, he was with Solid Technologies Inc., Seoul, where he was involved in research and development on mobile communication equipments for (W)CDMA and Wibro, as a member of the research and development staff. He is currently with the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, where he is a Post-Doctoral Researcher. His research interests are in the design of mixed-signal/rf integrated circuit and board-level high-frequency systems using system-in-package (SiP)/system-on-packagae (SoP) technology. José E. Schutt-Ainé (S 86 M 86 SM 98 F 07) received the B.S. degree in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, in 1981, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign (UIUC), in 1984 and 1988, respectively. Upon graduation, he joined the Hewlett-Packard Technology Center, Santa Rosa, CA, as an Application Engineer involved with microwave transistors and high-frequency circuits. In 1983, he joined UIUC, and then joined the Electrical and Computer Engineering Department as a member of the Electromagnetics and Coordinated Science Laboratories where he currently specializes in the study of signal integrity for high-speed digital and high-frequency applications. He has been a consultant for several corporations. His interests span the spectrum from microwave measurements to the generation of computer-aided design (CAD) tools for electronic systems. Dr. Schutt-Aine was the recipient of several research awards including the 1991 National Science Foundation (NSF) MRI Award, the 1992 National Aeronautics and Space Administration (NASA) Faculty Award for Research, the 1996 NSF MCAA Award, and the 2000 UIUC National Center for Superconducting Applications (NCSA) Faculty Fellow Award. He currently serving as Editor-in-Chief of the IEEE Transactions on Advanced Packaging.