UNEXPECTED through-silicon-via (TSV) defects may occur

Transcription

1 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 36, NO. 10, OCTOBER Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs Young-woo Lee, Hyeonchan Lim, and Sungho Kang, Senior Member, IEEE Abstract After the 3-D stacking, 3-D-ICs based on through-silicon-vias (TSVs) must be inspected for any TSV defects such as resistive open or bridge defects. In some research studies, several effective testing techniques have been developed such as parallel or serial test architectures, which measure the voltage across a single TSV with a comparator. However, in the current test architectures, hardware overhead and test time are proportional to the number of TSVs. In this paper, we propose a new unified test architecture for screening of TSV defects in 3-D-ICs. Depending on the number of assembled TSVs, the proposed grouping-based test architecture can effectively reduce the cumulative test time and hardware overhead without compromising the test quality. Index Terms 3-D-ICs, resistive open defects, resistive TSV-to-TSV bridge defects, through-silicon-via (TSV). I. INTRODUCTION UNEXPECTED through-silicon-via (TSV) defects may occur during the TSV manufacturing or the die stacking processes, which degrade the electrical performance of TSVs [1]. Many researches have focused on effective post-bond test techniques and design-for-testability (DFT) solutions to improve the quality and yield of 3-D-ICs [2] [5]. Post-bond testing is carried out in stacked devices with more than two layers. The post-bond test detects TSV or device functional defects caused by TSV misalignments, high temperatures, or high pressures after the stacking process [6], [7]. The post bond test is very important because a single defective layer in the 3-D-IC will invalidate the entire stack and whole stacked layers are completely discarded [8]. For this reason, testing TSVs is essential for quality assurance and to improve the mass production yields [9], [10]. The number of TSVs in 3-D-ICs is expected to increase continuously. The test time and hardware overhead of previous test architectures for testing TSVs are linearly proportional to the number of TSVs in the 3-D-ICs. For 3-D-ICs, efficient test methodologies have to be developed to minimize the test cost [11]. The online fault tolerance technique [2] provides the faster test time by dividing TSVs into groups in order to solve the linear growth of the test time in proportion to the number of TSVs. However, the hardware overhead cost is high in case of many TSVs with linear growth. The 1-D virtual TSV array (row-based test method) may help to solve those problems, as proposed in [3]. However, this test structure is Manuscript received February 21, 2016; revised June 2, 2016 and August 24, 2016; accepted September 8, Date of publication September 20, 2016; date of current version September 14, This work was supported by the National Research Foundation of Korea through the Korea Government (MSIP) under Grant 2015R1A2A1A This paper was recommended by Associate Editor N. Nicolici. (Corresponding author: Sungho Kang.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul , Korea ( roberto@soc.yonsei.ac.kr; lhcy92@soc.yonsei.ac.kr; shkang@yonsei.ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCAD only available when the BIST structure is implemented in 3-D-ICs. Furthermore, both previous works [2], [3] cannot detect TSV-to-TSV bridge defects. In contrast, our new the 2-D grouping-based TSV test architecture is designed to overcome these shortcomings and it enables lower hardware overheads. The new test architecture is based on the voltage divider structure for post-bond testing that detects TSVs with resistive open and bridge defects. There are two representative TSV test architectures based on the voltage divider structure: parallel test architecture (simultaneous testing of all TSVs in parallel) [4] and serial test architecture [5]. Both test architectures are to test the resistance-related delays across TSV in 3-D-ICs, which can characterize the resistance of the specific TSV for yield improvement during the silicon debugging and can be used as a part of at-speed test to guarantee timing specifications of 3-D-ICs. The parallel test architecture has four major problems that impede its efficiency: 1) long test time; 2) high hardware overheads; 3) high peak current consumption; and 4) inability to detect TSVto-TSV bridge defects if more than two TSVs are shorted together. To solve these drawbacks, the serial test architecture is developed. The serial test architecture differs from the parallel test architecture in two main ways. First, the comparator that measures the TSV voltages is shared across the TSVs in order to reduce hardware overheads. Second, the flip-flops that transfer the test results of the TSVs are used as a sequential pulse-transfer role for sequentially turning on the pmos and nmos transistors. It can reduce the peak current consumption and identify TSV-to-TSV defects. However, the total test time of [5] is doubled from the original test time of [4] because the reference voltage of the comparator differs between resistive open and TSV-to-TSV bridge defects. In summary, some major problems still remain to be solved, such as the linearly increasing test time and the large hardware overhead with an increasing number of TSVs. II. PROPOSED TEST ARCHITECTURE This section introduces our new 2-D grouping-based test architecture for inspecting resistive open and bridge defects of TSVs in 3-D-ICs. It provides a faster test time and lower hardware overheads among test architectures based on the voltage divider structure, without compromising test quality. A. Motivation According to [7], the TSV manufacturer said that fast and sensitive Cu leak/migration, Cu Void, and TSV-to-TSV open/short detection method should be developed in order to sustain good yield and quality for mass production. Furthermore, both total test time and total hardware overhead of the previous works are greatly affected by the number of TSVs, which would likely lead to higher test costs. Therefore, the TSV test methodology should satisfy the following constraints. 1) The increase of the total test time and the hardware overhead should be small as the number of TSVs increases. 2) The TSV test coverage includes not only a resistive open defects but also TSV-to-TSV bridge defects c 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 1760 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 36, NO. 10, OCTOBER 2017 Fig. 1. Concept of the grouping-based structure. (a) Serial test architecture. (b) Grouping-based test architecture. 3) The peak current consumption should be reasonable for mass production. 4) The TSV test architecture should be available without the implementation of the BIST. In order to overcome the limitations of the previous works, we propose a novel test architecture based on the voltage divider structure by devising a 2-D architecture and satisfying all of the above-mentioned constraints. The proposed test architecture can be used in practice since it can be used with the automatic test equipment (ATE) by grouping the 2-D TSV array; row and column, respectively. B. Concept of the Grouping-Based Structure This new test architecture groups the TSVs in a virtual matrix using a vertically and horizontally partial parallel test method. Fig. 1 conceptualizes the virtual matrix structure of 100 TSVs in the grouping-based test architecture. The size of the n n virtual matrix depends on the number of TSVs; N = n n, wheren is the number of TSVs. For 100 TSVs, a virtual matrix is required. Each TSV is sequentially placed in one cell of the virtual matrix table. Next, progressing from top to bottom, all TSVs in one row of the matrix are measured in parallel. In this way, the TSVs are tested line-by-line rather than individually. After completing the horizontal line group tests, the columns are sequentially tested from left to right. Consequently, the proposed test architecture requires 20 clocks to test 100 TSVs ten each for the horizontal and vertical lines. This configuration reduces the time of testing 100 TSVs to 20% that of the previous test architecture [4], [5]. In contrast to [4], the grouping-based test architecture can detect TSV-to-TSV bridge defects under any condition. First, suppose that TSV1 and TSV2 are shorted together as shown by a red marker in Fig. 1(b). Both TSVs locate in the first row and consecutive columns of the virtual matrix. Therefore, the bridge defect will not be detected in the horizontal line group testing (group 1), but will be detected in the first vertical line group testing (group 11). C. Grouping-Based Test Architecture The physical design of the proposed test architecture is based on the virtual matrix structure of Fig. 1. Fig. 2 is a block diagram of the proposed test architecture with 100 TSVs. The test modeling of TSVs with resistive open and bridge defects is identical in the proposed and serial test architectures. pmos transistors are employed as the voltage driver, and pmos and nmos transistors provide the voltage divider for each TSV; both operate in the same way as described in [5]. However, beyond the voltage divider, the proposed test architecture entirely differs from the established test architectures. The pulsetransfer flip-flops enable the single-voltage divider of the selected TSV in [5], but enable the voltage dividers of all TSVs in the selected line group in the proposed test architecture. This means that during one period of the test clock, the pulse-transfer flip-flops selectively turn on voltage dividers of the selected line group together. This new method drastically reduces the number of flip-flops. In contrast, the number of shared comparators is slightly increased, compared to [5]. This increase is necessary to reduce the test time of simultaneously detecting the resistive open and bridge defects, which have different reference voltages, and hence, require two different comparators. Moreover, while the previous test architecture [5] employs one shared comparator for all TSVs, the proposed one automatically assigns independent shared comparators to all TSVs of the selected group, respectively. Outputs of shared comparators reach the XOR and NAND gates in parallel. The XOR gate inspects the resistive open and TSV-to-TSV bridge defects of single TSVs in the selected line group, and the NAND gate flags any TSV-to-TSV bridge defect as a fail. The proposed test architecture also decreases the total test time by merging the results of the selected line groups. All XOR and NAND gate outputs of each TSV in the selected line group are summarized into a single group result by the n-input AND gate (forming an n n matrix). The merge result is classified as a pass or a fail. The merge result fails when an open defect is detected in a horizontal line test or when a TSV-to-TSV bridge defect is detected in any line test. In a vertical line test, all open defects are ignored and the result is automatically passed, because open defects should have been detected in the horizontal line test and duplicating the analysis would needlessly increase the total test time. However, this merging does not degrade the diagnostic resolution because a failed merge result is automatically decompressed by using the flexible parallelto-serial circuit. A failed merge result activates the parallel-to-serial circuit transition and delays the free running test clock (Clk). The single TSV result of the selected line group is sequentially sent to the pad in the next test cycle (ClkB). The Clk is delayed until the single TSV result of the selected line group has been conveyed to the pad. III. EXPERIMENTAL RESULTS AND ANALYSIS In this section, the proposed test architecture is evaluated and compared with the previous test architectures based on the voltage divider structure via simulation experiments. To compare the hardware sizes of the proposed and previous test architectures as the number of TSVs increases, we employed the synthesis tool Synopsys Design Vision (Nangate 45 nm Open Cell Library). Moreover, the test time of the proposed test architecture depends on the number of TSV defects. The test time was obtained by simulating the fault model experiment 10,000 times, for a given number of TSVs. Lastly, to verify the functionality of the proposed test architecture, the voltage profile of the TSVs (V tsv ) from the TSV resistance change (R tsv ) and the peak current consumptions of the 837 TSVs were simulated by HSPICE. The experiments are conducted on a 45 nm gate library with predictive technology model transistor models [12].The usedtsvandfet specifications in the HSPICE simulation were extracted from published data [5]. In addition, we assume the following two conditions which are the same constraints as described in [5]. The first constraint is that the maximum wire length between the voltage dividers and the shared comparator is less than 10 mm. The other one is the shared comparator can be connected with up to 512 TSVs. A. Simulation Results of Changing the TSV Resistance Fig. 3(a) and (c) present the voltage profiles (V tsv )oftsv1and TSV2 among the 837 TSVs, varying the TSV resistance (R tsv ) and the

3 LEE et al.: GROUPING-BASED TSV TEST ARCHITECTURE FOR RESISTIVE OPEN AND BRIDGE DEFECTS IN 3-D-ICs 1761 Fig. 2. Proposed test architecture with 100 TSVs. Fig. 3. V tsv waveform with 837 TSVs for different R tsv and R bridge. (a) Voltage profiles of a resistive open defect (TSV1, TSV2). (b) Detailed V tsv as functions of R tsv. (c) Voltage profiles of a resistive TSV-to-TSV bridge defect (TSV1, TSV2). (d) Detailed V tsv as functions of R bridge. between-tsv resistance (R bridge ), respectively. TSV1 and TSV2 are tested together in the first row, but separately in the first and second columns, respectively. Assuming that TSV1 and TSV2 are shorted together, their voltages will be consistent in the first row test, which does not detect actual R bridge value [Fig. 3(c)]. Therefore, the first row test returns a pass result. However, the bridge defect between

4 1762 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 36, NO. 10, OCTOBER 2017 TABLE I COMPARISON OF HARDWARE OVERHEADS AS FUNCTIONS OF N Fig. 5. Comparison of total test times as functions of the number of TSVs. Fig. 4. of TSVs. Comparison of total hardware sizes as functions of the number TSV1 and TSV2 is detected in the first and second column tests. Fig. 3(b) and (d) shows the detailed waveforms of the selected TSVs in Fig. 3(a) and (c), respectively. The reference voltages of the two shared comparators are selected by the user and should be different. The appropriate reference voltage of upper and lower comparators can be determined by changing R bridge and R tsv, and the used reference voltage of the fail conditions in this simulation was 0.91 V (R bridge 10 k ) and 0.27 V (R tsv 500 ), respectively. As described in [5], the minimum resolution of the reference voltages is also V and the proposed test architecture can also support the TSV delay test up to 262,144 TSVs (i.e., ) with the same resolutions of ps under the same constraints [5]. B. Comparison of Hardware Overheads The hardware overhead of the proposed test architecture is significantly lower than that of the previous works [4], [5]. The numbers of used components, mathematically calculated as proportions of the number of TSVs, are listed in Table I. The total hardware overhead of the previous works is proportional to O(N), where N is the number of TSVs. Unlike the previous works, the overhead of the proposed test architecture is a square root function of N, O( N). Fig. 4 shows the synthesis results which is computed as the equivalent gate count of 2-input NAND gates determined by Synopsys Design Vision. Relative to the previous works [4], [5], the hardware overhead of the proposed test architecture begins reducing for 27 and 76 TSVs, respectively. However, in real 3-D-ICs, 76 TSVs is a very small number. Consequently, the proposed test architecture becomes more advantageous as the number of TSVs increases. C. Comparison of Total Execution Test Time The test time of the previous works is linearly proportional to the number of TSVs. For example, the test time of 100 TSVs in the serial test architecture is 2 (100 the test clock period), where the factor of 2 accounts for the testing of open and TSV-to-TSV bridge defects. In contrast, our proposed test architecture completes the testing of 100 fault-free TSVs in 20 the test clock period (ten clock periods for the vertical, ten for the horizontal line groups). However, the test time of the proposed test architecture depends on the test failure numbers of the horizontal and vertical line groups. Fig. 6. Comparison of peak current consumption with 837 TSVs. Therefore, we simulated the expected test times in a faulty model experiment. Ten thousand simulations were implemented in the C computer language. According to [13] and[14], the TSV failure rate is relatively high varying from 0.005% to 5% in current TSV technology. The used probabilities of resistive open and TSV-to-TSV bridge defects were both assumed as 0.5% (giving a 1% probability of TSV defects, as described in [2]). Fig. 5 plots the test times as functions of the number of TSVs. The purple (circle markers) and green (triangle markers) lines in Fig. 5 plot the test time under a fault-free TSV condition and a 0.01 defect probability condition in the proposed test architecture, respectively. The greatest time reduction was obtained in simulations of the fault-free TSVs. At a 1% probability of TSV defects, the time performance of the proposed one deteriorated by comparing the optimistic test case, but the test time still remained below 30% (relative to [5]) up to 1,000 TSVs. The performance of the test clock can be degraded by shared group comparators. The worst test clock period under the maximum wire length constraints is 25 ns for testing 262,144 TSVs (i.e., ) as referred to [5], and the test clock can be improved by adjusting the size of the n n matrix. D. Comparison of Peak Current Consumption The peak current consumption is related to the direct current path from VDD to GND, when all transistors of both the driver and voltage divider are turned on. Fig. 6 compares the peak current consumption of 837 TSVs configured by various test architectures. The peak current consumption of [4] linearly increases with the value of N, where N is the number of TSVs. In contrast, the previous work [5] turns on a single-voltage divider in each test clock period, and hence, consumes the lowest peak current. The grouping-based test architecture turns on vn voltage dividers per clock period. The maximum current output of the device power supply (DPS) in ATE depends on the type

5 LEE et al.: GROUPING-BASED TSV TEST ARCHITECTURE FOR RESISTIVE OPEN AND BRIDGE DEFECTS IN 3-D-ICs 1763 current consumption for mass production, the proposed test architecture reduces the cost of testing TSVs in 3-D-ICs. Consequently, our proposed test architecture enables a superior unified TSV testing for resistive open and bridge defects in 3-D-ICs. This method is expected to contribute to the testing and handling of large numbers of TSVs in future 3-D-ICs. REFERENCES Fig. 7. Comparison graph of test architectures. of the DPS instruments, but there is a perceived tradeoff between the peak current and the number of channels. In general, a DPS with a high pin count is applicable for current outputs below 800 ma. In [5] with 837 TSVs, the maximum peak current consumption is approximately 3.28 ma. However, as the TSVs in [5] are tested oneby-one, the maximum peak current consumption is independent of N, and need not be considered. In contrast, when the value of N reaches approximately 604 TSVs, the peak current consumption of [4] begins exceeding the maximum DPS current output. Therefore, the test cost of [4] is expected to be quite high because a DPS with a high pin count cannot be applied to a device with 837 TSVs. The peak current consumption of the proposed test architecture is reasonable (requiring ma for 837 TSVs and maximizing at 165,649 TSVs). In addition, if the value of N exceeds it, the maximum current output can be doubled by merging two DPS channels. IV. CONCLUSION The number of TSVs in 3-D-ICs has been steadily increasing, and this trend is expected to continue. Verifying TSVs by existing test architectures may become increasingly expensive because the test times and hardware overheads are linearly proportional to the number of TSVs. To alleviate these problems, we proposed the new 2-D grouping-based TSV test architecture based on the voltage divider structure. Our proposed test architecture is the most efficient of the examined architectures, as described in Fig. 7. By reducing the test time and hardware overheads while maintaining an appropriate peak [1] M. Cho, C. Liu, D. H. Kim, S. K. Lim, and S. Mukhopadhyay, Pre-bond and post-bond test and signal recovery structure to characterize and repair TSV defect induced signal degradation in 3-D system, IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 11, pp , Nov [2] Y. Zhao, S. Khursheed, and B. M. Al-Hashimi, Online fault tolerance technique for TSV-based 3-D-IC, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 8, pp , Aug [3] Y.-J. Huang et al., A built-in self-test scheme for the post-bond test of TSVs in 3D ICs, in Proc. IEEE VLSI Test Symp., Dana Point, CA, USA, 2011, pp [4] F. Ye and K. Chakrabarty, TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation, in Proc. IEEE Design Autom. Conf., San Francisco, CA, USA, 2012, pp [5] H. Sung, K. Cho, K. Yoon, and S. Kang, A delay test architecture for TSV with resistive open defects in 3-D stacked memories, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 11, pp , Nov [6] E. J. Marinissen, Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access, in Proc. IEEE Asia Pac. Conf. Circuits Syst., Kuala Lumpur, Malaysia, 2010, pp [7] C. Y. Lee, S. Kim, H. Jun, K. W. Kim, and S. J. Hong, TSV technology and challenges for 3D stacked DRAM, in IEEE VLSI Technol. Symp. Tech. Dig., Honolulu, HI, USA, 2014, pp [8] E. J. Marinissen and Y. Zorian, Testing 3D chips containing throughsilicon vias, in Proc. IEEE Int. Test Conf., Austin, TX, USA, 2009, pp [9] H.-H. S. Lee and K. Chakrabarty, Test challenges for 3D integrated circuits, IEEE Design Test Comput., vol. 26, no. 5, pp , Sep./Oct [10] I. Loi, S. Mitra, T. H. Lee, S. Fujita, and L. Benini, A low-overhead fault tolerance scheme for TSV-based 3D network on chip links, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, San Jose, CA, USA, 2008, pp [11] Z. Gong and R. Rashidzadeh, TSV extracted equivalent circuit model and an on-chip test solution, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 35, no. 4, pp , Apr [12] PTM. Arizona State Univ., Tempe, AZ, USA, Feb [Online]. Available: [13] Y. Chen, D. Niu, Y. Xie, and K. Chakrabarty, Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, San Jose, CA, USA, 2010, pp [14] C. Wang et al., BIST methodology, architecture and circuits for prebond TSV testing in 3D stacking IC systems, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 1, pp , Jan