Packaging Technology and Design Challenges for Fine Pitch Cu Pillar and BOT (Bond on Trace) using Thermal Compression Bonding

Transcription

1 Packaging Technology and Design Challenges for Fine Pitch Cu Pillar and BOT (Bond on Trace) using Thermal Compression Bonding MJ (Myung-June) Lee 1, Chew Ching Lim 2, Pheak Ti Teh 2 1: Altera Corporation, 101 Innovation Drive, San Jose, CA U.S.A. mjlee@altera.com, : Altera Corporation, Bayan Lepas, Penang, Malaysia cclim@altera.com ( ), ptteh@altera.com ( ) Abstract As copper (Cu) bump technology becomes more mature, it is gradually taking the place of the conventional solder base bump in flip chip interconnections. Especially, microbump using Cu-pillar bump has already become essential platform technology for devices requiring finer bump pitch less than 100µm down to 40~20µm. Several motivations that Cu bump brings over solder bump are the fine pitch scaling capability in package assembly process, superiority of mechanical endurance and electrical performance. Although the baseline packaging technologies using Cu bump for around 50µm bump pitch and smaller than 100mm 2 chip size has been in high volume production for many years, there are still many areas need further development to expand the technology envelop to finer pitch application and larger chip size i.e. less than 40µm multi-tier bump pads with larger than 400~600mm 2 die size. Comprehensive experimentation have been conducted to get optimum Cu pillar structure, package substrate design and the metal finish, thermal compression bonding process and the underfill method for finer pitch but larger chip size packaging. This paper will discuss about the technical findings and recommendation based on the lessons learned from the series of experimentation, experience from high volume production in both component manufacturing and board level surface mounting, including remaining challenges for achieving larger scale high density chip-onsubstrate application in future. 1. Introduction In order to fill the gap in the density between silicon and package, many innovative technologies are being developed and deployed continuously. Fine pitch micro-bump using Cu pillar technology provide a scaling solution with offering a path to high density chip-on-chip, and chip-on-substrate interconnection. A typical Cu bump is composed of Cu column (pillar) base and solder cap. A columnar Cu base can be a circular or ovular shape, and the solder cap, typically composed of a Tin/Silver (SnAg) solder alloy, is plated on top of the Cu column. Several motivating facts that drives Cu bump over solder bump are the superiority of mechanical endurance, electrical performance, and the manufacturability in package assembly for finer pitch devices. The mechanical durability of Cu helps to improve the bump reliability from joint fatigue failure. Decreasing the bump pitch triggers a higher risk of electro-migration by increasing the density of the electrical current and thermal energy in the flip chip interconnection using solder base bump, but the Cu bump is enough to compensate for the weakness of the solder bump. The finer pitch scaling capability of the Cu bump can also help to reduce the bump to bump short concern at the chip attach manufacturing process than solder bump. Subsequent gain through the use of Cu bump is compliance of full ROHS-6 requirements. The improvement in the package substrate manufacturing process and its technology development including the base material i.e. core and build up film have supported the wide range of high density scaling requirements, though volume processablity and the cost effectiveness are yet to be fully proved. In parallel, advanced packaging process technology have introduced newer methodology for bridging the silicon and substrate together. Thermal commpression bonding is one of the technology which covers the scaling limitation of the conventional mass reflow process, effectively. Technologis are out there, and those are all interrelated and interreacting, hence intergrating them all together often create unexperienced challenges. Altera Packaging R&D has taken the initiative and challenging on the integration of all those technologies over the last 3 years. Major assembly and substrate partners have invited to the development project. The primary objectives were to establish a platform technology for high density chip-on-substrate interconnetion with the well defined boundry condition, and a high volume manufacturing solution for cost effective SFF (small form factor) packaging and enabling package miniaturization by replacing wire bond with Cu pillar over the chip deisgned for wire bond. DFM (design for manufacturing) and DFR (design for relaibility) are the essential consideration to yield positive results at the end. This paper will discuss all of these challenges on package design, structure, and process technology: how to solve the deign complexity of a large number of IO within a tight space, how to engineer a Cu pillar structure, how to decide the structure of the micro-bump landing pad of the substrate and the surface finish, how to determine manufacturing friendly assembly process (i.e. TCNCP v. mass-reflow), and how to build robust component with customer s manufacturing process friendly.

2 2. Package Structure, Bumping and Assembly Process Flow Conventional FCBGA and chip scale fccsp packages consist of a silicon chip, bumps (solder or Cu pillar), capillary or molded underfill encapsulant, a thermal lid, an organic laminated substrate (Fig. 1). Fig. 1. FCBGA and fccsp Packages In order to put bumps on silicon chip, it is required to layer UBM (under bump metallization) over either Aluminum or Copper metal pad mainly for the component reliability and performance. Typical UBM stack comprises of two to four layers of certain metals, of which the most commonly used are Titanium, Copper, Tungsten, Palladium, and Nickel. The thickness of metal pad and each metal layer in UBM stack vary according to the silicon and bump design, as well as the product application. RDL (redistribution) using Cu traces is often used to apply Cu pillar bump for a silicon die designed for wire bonds. The typical structure and process flow of RDL, Bump and Assembly is shown in Fig. 2 and Fig. 3. Fig. 3-a. Process flow of RDL and Bump Fig. 2-a. Typical structure of Cu bump with RDL Fig. 3-b. Process flow of Mass reflow CUF vs. TCNCP Fig. 2-b. Typical stru\cture of Solder bump with RDL 3. Design Enablement Die design was a wire bond (WB) package friendly pad arrangement. Large die to package ratio limited the device the small form factor package (SFF). With the finer pitch cupillar technology advancement, the space limitation required for wire bonding has been enable Altera to provide SFF package solution to the customer.

3 3.1 Die level RDL design Original die was designed for wire bonding application. Hence, the bond pads were placed on the die periphery with multi-tier <60um pitch configuration. In order to apply the chip for SFF (small form factor) packaging using fine pitch Cu pillar, those bond pads need to be re-distributed to Cupillar assembly friendly pad pattern. It requires adding one pad redistribution layer (RDL) in between the additional two passivation layers. UBM (under bump metallization) layer is essential part for any type of bumping. The construction of these layers is shown in Fig.2-a. Following the WB pad modular pattern, the RDL design was designed in modular pattern as well, so that the length of the RDL routing could be consistent across the entire die. The result of the innovation has brought the benefit to device performance consistency and design cycle time efficiency. The original 3 rows peripheral WB pad arrangement has distributed into 4 rows peripheral cu-pillar pad arrangement in order to maintain IO, power and ground pad resource compare to original WB die. The die resource was arranged in the pattern with considering the routing friendly on the substrate design. IOs were segregated into 2 parts, half of the IOs arranged 1 st and 2 nd row of cu-pillar pad near to the die edge, while the other half of the IOs were arranged in 3 rd and 4 th row toward die center. Similar to the power nets, IO power (VCC1 and VCC2) were assigned to 1 st and 2 nd row, while Core power (VCC3) were assigned in 3 rd and 4 th row. The RDL routing and Cu-pillar bump assignment has shown in Fig. 4. also control solder spreading during assembly process. The structure of combination of BOT and isro with Flat-plug has shown in Fig. 5. Fig. 5. BOT design with Flat-plug isro design. As similar to planning done in the Cu-pillar assignment, substrate routing has segregated into 2 portions: Fan out for outer 2 rows pad, while fan in for inner 2 rows pad. This is to avoid to congestion on the substrate design for IO escape routing from the Cu-pillar pads. The fan out routing will have the via directly dropped on the assigned BGA balls, while the fan in routing will have via dropped on the empty area of package center area, using the bottom layer for trace routing to the assigned BGA balls. Fig. 6 illustrates the routing strategy on the substrate level. Fig. 4. IO modular routing pattern at RDL level 3.1 Package level substrate design The advancement of the substrate technology has enabled the substrate to design in smaller trace pitch of <40um. First, the bond on trace (BOT) has allowed fine pitch trace, <40um, in the substrate. More traces are able to escape from the cu-pillar bump area. Second, the isolate solder resist opening (isro) with Flat plug structure, which has individual opening to the contact point from bump to substrate pad instead of long opening on pad and its nearby trance in conventional solder resist opening design. The benefit of the isro with Flat Plug has by increasing the reliability of the package by protect trace from undercut and Fig. 6. Substrate level fan out and fan in routing strategy based on peripheral cu-pillar pad arrangement. 4. Packaging Experimentation 4.1 Test Vehicles, Variables, and Boundary conditions The objective of developing Fine Pitch Cu Pillar Technology is to establish a platform interconnection technology which can support wide range of existing and future products. Hence, it is very crucial to understand the boundary conditions of each variable (i.e. bump pitch, die size, package type, substrate structure, etc.) and the reaction among factors upfront. This is to ensure that the offering is an effective solution per specific design and application. In

4 conducting multiple experimentations in sequence, we have applied extended design rules for the test vehicles than the baseline design rules (Table I) already used for HVM production. This is to determine the technology extension. Table I. Baseline Design Rule in HVM Fig. 7-a. 12x16mm DC Substrate top metal layout Fig. 7-b. 10x10mm 28nm DC Substrate top metal layout Package body size: 27x27mm 2 and 35x35mm 2 FCBGA with build-up using 800um thick core (GX13/E679). Package type: Bare die, SPL (Single piece lid), and TCFCBGA (which is molded FCBGA, FCmBGA TM ). Silicon die: 1 metal layer daisy chain with 12x12mm 2 and 12x16mm 2, full stack 9 metal layer using 28nm node technology with 10x10mm 2 and 10x21mmm 2 (1x2 tiles of 10x10mm 2 ). The layout of the substrate top metal is shown in Fig. 7. The full stack die TV is to make sure we don t miss any critical reliability coverage from the 1 layer mechanical die TV. Die thickness: 500um and 780um have evaluated to understand any impact from warpage. Bump pad pitch: Staggered 30/60um in two row and tritier staggered 40/80um for DFM study. The Circular bumps are 30um in diameter with 40um height with thicker SnAg solder cap, and Ovular bumps are 20x45um UBM with 40-45um height with thinner SnAg cap (Fig. 8). Surface finish of package substrate: Immersion Tin (IT), Electroloss Nickel Electroless Palladium Immersion Gold (ENEPIG), Direct Immersion Gold (DIG), and Solder Coating and the cross-section of BOT are shown in Fig. 9. Fig. 8-a. Ovular Bump and the BOT on Immersion Sn Fig. 8-b. Circular bump and the BOT on Immersion Sn Table II. The factors and Variables in the Test Vehicles Fig. 9. Other Surface Finish and the Cross-section 4.2 Assembly Process TCNCP process for chip attach and underfill have been used for assembly due to the bump pitch of all TV are fine pitch. Typical TCNCP process is shown in Fig. 10.

5 Table IV. Bare-die FCBGA Package Warpage Trend Fig. 10. TCNCP process TCNCP process characterization is very important for each and every new product due to the different combination of die size, die thickness and Cu pillar bumps layout. This is essential to avoid reliability failure induced by improper manufacturing control. Good NCP coverage can be obtained by optimum NCP dispense pattern, volume, and bonding time and force. Visual inspection for checking the coverage and fillet height along die edge will be the first step. CSAM (Confocal Scanning Acoustic Microscopy) and/or X-ray is a non-destructive way of inspecting NCP void, while p-lap (parallel lapping) is a destructive test method. Good alignment of Cu pillar bonding on substrate trace is another important item, which can be checked through x-ray inspection. Often, x-section at each corner of dies is used for validating the off-set bonding. Lastly, checking solder wetting between Cu pillar and substrate trace is the most critical step in the characterization. X-section is one of method for checking solder wetting condition. Resistance measurement by electrical test prior x-section will be the ideal way to locate any bonding has micro-crack or discontinuity issue. Fig. 11. Example of NCP Dispense pattern, NCP coverage, NCP Fillet Height 4.4 High Temperature Warpage and SMT It is important to study high temperature warpage in order to support successful SMT at customer s manufacturing site. As previous study of the room temperature package warpage and coplanarity of body size 27mm and 35mm showed high warpage value, it indicated that such a large body package need more careful optimization in structure and material selection for successful SMT. This triggered a sub-study of high temperature warpage and SMT with the use of a relatively smaller package size of 11mm that passed Altera internal coplanarity spec. By using previous TV of 11mm package size with approximately <10x10mm 2 die size, a DOE is designed including the combination of 3 types of EMC, 3 types of substrate core, 3 different die thickness and 2 different mold cap thickness, as shown in Table V. Warpage model was built to simulate room temperature and high temperature warpage for the designed package BOM, and experimentation was also done to obtain the actual warpage data. Warpage simulation data and experimental data are summarized in Fig. 12. Table V. High Temperature Warpage DOE Factors 4.3. Package Warpage and Coplanarity Because the TV packages are large as 27mm and 35mm, it is important to understand the behavior of package warpage and BGA coplanarity. Bare-die FCBGA package warpage and BGA coplanarity data show significant impact from body size and die thickness (Table III and Table IV). Table III. BGA coplanarity per body size and die size/thickness Fig. 12. Warpage Simulation and Experimental Results

6 This study has showed that different package BOM combination yields different warpage results. Below is the general warpage trend exhibited by different BOM, and this can be served as a general guideline for BOM selection to produce lower warpage. EMC: EMC-E (worst) > EMC-F > EMC-G (best) (Note: EMC may change package warpage direction) Substrate Core: Sub-A (worst) > Sub-B > Sub-C (best) Die & EMC Thickness: Thicker, Better. (Note 1: Increasing die thickness in same EMC thickness shows insignificant warpage improvement) (Note 2: The warpage performance per each material and thickness combination may vary per package type) One of the package BOM combination that passed SPP-024A high temperature warpage spec (ie 100um) is then selected for SMT evaluation to examine board mount yield under different SMT condition. SMT evaluation is carried out at 260C, 270C and 280C peak reflow by using 4 mils & 5 mils stencils combined with round and square stencil opening. Meanwhile, PCB used is 1.0 mm thick, 4 layers, 12 up designed per IPC-9701 guidelines. Fig. 13 showed this package pass SMT evaluation with no solder bridging failure from all reflow conditions. Besides, there is no sign of opens or cold joints at solder balls on the package edges. 5. Findings and Lessons Learned 5.1 Substrate Design Surface Finish Electrolytic Sn or Ni/Au plating is common surface finish technology that have been qualified and being applied for HVM BOT packaging. However, these technologies could be good for the packaging using strip format substrate with wider bump pitch (i.e. larger than 50um inline), but are not suitable for the single unit format package with high density design (i.e. less than 50um bump pitch) due to tight DR and cost. Alternatively, Electro-less plating technology becomes more cost effective solution for the devices require fine bump pitch TCNCP and BOT. Hence, we have evaluated Immersion Sn, ENEPIG (Electro-less Nickel Electro-less Palladium Immersion Gold), DIG (Direct Immersion Gold), and Solder Coat surface finish as shown in Fig. 8 and Substrate Structure As it was already explained at the Section-3 Design Enablement, there are many challenges on the design and layout of the substrate for TCNCP application. Trench pattern solder resist opening is one of a common technic which can accommodate larger number of IO by utilizing limited space effectively. This pattern is shown in Fig. 14. Area Array Design Fine Pitch Perimeter Fig. 13. Warpage Simulation and Experimental Results 4.5 Reliability Tests All TV were subjected to the reliability stress tests per JEDEC Standard, as listed in table below. Besides, electrical Open/Short test and SAT (Scanning Acoustic Microscopy Test) were performed per each readout point, time=0 and 200/500/1000/1500 hours/cycles. Table V. Reliability test items and Conditions Fig. 14. Trench Pattern Solder Resist Opening for BOT of fine pitch perimeter micro-bumps 5.2 Findings-1: Open failure from Immersion Sn plated test vehicle Very obvious failure that we observed was open failure occurred at the interface between Cu-pillar and BOT trace. The failure might be initiated from the level-3 MRT, and propagated further during temperature cycles (Fig. 15). Most of failed pins are located at middle row on peripheral site. Larger body (35x35mm) and Thicker Die (780um) yielded higher open failure than smaller body (27x27mm) and thinner die (500um).

7 Fig. 15. FA of open failure at 500 TCB 5.3 Finding-2: Open failure from ENEPIG with Flat- Plug SR structure Flat Plug structure Flat-Plug SR is the structure that SR (solder resist) coated on pad (trace) side-wall and plugging gaps between pads (traces). NTK has developed this technology, which benefits preventing Cu undercut, excess electroless plating, NCP trap void at TCNCP process, and reinforce of pads (traces) adhesion. The structure and advantages of Flat-Plug are shown in Fig. 18-a and 18-b. Fig. 16. Commonality of location of open failures Fig. 16 explains that die tilt might cause insufficient solder joint at time zero and resulted in open failure after thermal cycles. Fig. 17 shows Cu undercut is prone to happen in the middle row of the trace, which might be proportioned plating time and or length of Cu pad. Fig. 18-a. Cross-section and Structure of ENEPIG with Flat-Plug Fig. 18-b. Advantages of Flat-Plug SR TM Structure Fig. 17. Cross section of Sn undercut Lesson learned Use of Immersion Sn as a surface finish for fine pitch device substrate has higher risk in micro-joint open failure due to Cu undercut and insufficient amount of solder volume for the bump to trace joint. Major difference in Electrolytic Sn plating and Electroless Immersion Sn plating is the thickness control per plating method. Electrolytic Sn plating is additive plating, so the thickness can be added over 3um without impacting Cu, while electroless immersion Sn plating is chemical substitution plating which replaces Cu. Therefore, thicker Sn plating thickness in Immersion Sn plating means there are more Cu undercut, which will results in more solder consumption in the micro-joint system, then end up yielding non-wetting (open failure) over thermal cycles. Mechanism of solder outflow on ENEPIG Even with the use of Flat-Plug SR TM structure with ENEPIG plating, we observed another obvious open failure at HTS (high temp storage). The open in the micro-joint happened due to the solder outflow over the ENEPIG surface, which results in insufficient solder. It was confirmed that the solder outflow is in proportion to the area of the ENEPIG bump landing pad. Fig. 19 illustrates the mechanism of the open failure. Fig. 19-a: Progress of solder outflow over MRT and HTS

8 Fig. 21. Design of isro BOT with Flat-plug Fig. 19-b: Solder outflow per landing pad area (ENEPIG) Lesson learned Changing the surface finish from Immersion Sn to ENEPIG for Cu-bump bond on trace was very effective. However, we have learned that the total area of bump landing pad should be limited within some range because the excellent wettability of ENEPIG with solder will consume extra amount of solder. We have been able to demonstrate the robustness of the isro with Flat-plug structure in both TCNCP manufacturability as well as the long term CPI reliability. The test vehicles used for the Altera Cyclone-V SFF technology qualification have passed 2000 cycles TCB and 1000 hours HTS and 96hours uhast with no failure so far. The actual cross-section of post 2000TCB is shown in Fig. 22. Fig. 23 shows the actual images of the Cu-bumps on chip and substrate top metal layer of the test vehicles evaluated. 5.4 DIG and Solder Coat Both DIG (Direct Immersion Gold) and Solder coat surface finish have demonstrated its good wetting with SnAg solder of Cu bump without Cu undercut. Though these two surface finish methods demonstrated good micro-joint interconnection and passed reliability tests, these options are yet to be favorable for production due to the limited supply chain and less cost competitive. The interconnection quality of post 500TCB is shown in Fig. 20 below. Fig. 22. X-section of post 2000TCB bond of isro-flat Plug Fig. 20. Cross-section of post 500TCB DIG and Solder coat 5.4 Finding-3: ENEPIG on isro pad with Flat plug structure Based on the lessons learned from multiple DOE, it is realized that the area of bump landing pad for BOT will need to be kept as small as possible to minimize the solder outflow. The Fig. 16 is an innovative practice of structuring isolate solder resist opening (isro) with Flat plug structure. The benefits of the isro with Flat Plug are not allowing Cu undercut but limiting very small amount of solder outspreading. The structure of isro with Flat-plug is shown in Fig. 21. Fig. 23. Actual substrate layer and Bump of CV-SFF TV 6. Conclusions and Actions moving forward These comprehensive development works have successfully demonstrated the robustness of the manufacturability and reliability of Cu-pillar micro-bump and TCNCP combining with isro and Flat-plug structure substrate. All the methodology and learning out of these series of experimentation will be able to help identify a cost effective packaging solution where fine pitch Cu-pillar bump is necessary, too. Eventually, the technology has applied for the successful launching of Altera Cyclone -V FPGAs with SFF packaging, and to be applied for future packaging technology. Several additional engineering validations have been conducted using larger die (400mm 2 ) and larger body size FCBGA packages. This was to extend the technology scale to higher bump density with larger die size and package body size. Team have observed multiple area need further

9 fine tuning with finer scale engineering such as warpage optimization from each material combination, chip attach and underfill method, substrate material i.e. core and buildup, layout structure optimization per package scale. Currently, this technology is one of major platform interconnection milestones of the company s future advanced but cost effective packaging roadmap i.e. 2.1D and Face-to-Face packaging with ultra-high density organic substrate. Acknowledgments This research is over 2 yearlong intensive engineering collaborating works among Amkor R&D, NTK, and Altera Package R&D, and over 1 year for New Product Engineering and Rollout within Altera. Special thanks go to Amkor Korea R&D team, and NTK Co., LTD, and Altera Penang Packaging and Reliability Group References 1. Yang-Gyoo Jung, Myung-June (MJ) Lee et al, Development of Large Die Fine Pitch Flip Chip BGA Using TCNCP Technology Electronic Components and Technology Conference, San Diego, CA, May JEDEC Solid State Technology Association. JESDC22- A104D 3. Myung-June (MJ) Lee et al, Packaging Technology and Design Challenges for Fine Pitch Micro-Bump Cu- Pillar and BOT (Direct Bond on Substrate trace) using TCNCP Method, IPC APEX EXPO, Las Vegas, NV, April 2014