Peripheral Flip Chip Interconnection on Au Plated Pads using Solder-Capped Cu Pillar Bumps

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1 Noma et al.: Peripheral Flip Chip Interconnection on Au (1/6) [Technical Paper] Peripheral Flip Chip Interconnection on Au Plated Pads using Solder-Capped Cu Pillar Bumps Hirokazu Noma*, Kazushige Toriyama*, Keishi Okamoto*, Keiji Matsumoto*, Eiji Ohno**, Hiroyuki Mori***, and Yasumitsu Orii* *IBM Research Tokyo, IBM Japan, Ltd., , Shimo-tsuruma, Yamato-shi, Kanagawa , Japan **Japan STG Laboratory, IBM Japan, Ltd., , Shimo-tsuruma, Yamato-shi, Kanagawa , Japan ***Japan STG Laboratory, IBM Japan, Ltd., 338, Enpukuji-cho, Muromachi-dohri, Oike Sagaru, Nakagyo-ku, Kyoto-shi, Kyoto , Japan (Received August 19, 2011; accepted November 21, 2011) Abstract Peripheral flip chip interconnection on gold plated pads would be required to assemble the chip with surface mount technology (SMT) because the gold pads are sometimes used for SMT. Chip Connection (C2) which uses solder-capped copper pillar bumps on the chip and uses reflow process is an attractive method for ultra fine pitch peripheral flip chip interconnection. 50 μm-pitch interconnection on gold plated pads was made with C2 and the shape of the solder joints was discussed. It was found from a mechanical analysis that the stress in low-k layer would be reduced when the solder did not wet on the sides of copper pillars on the chip. Direct immersion gold (DIG) surface treatment would be attractive for not only compatibility to assemble with surface mount components but also for chip-package interaction improvement. Keywords: Flip-Chip, Inter-metallic Compounds (IMC), Surface Tension, Contact Angle, Mechanical Analysis, Low-k Material, Chip-Package Interaction (CPI), Chip Connection (C2), Cu Post, Reflow 1. Introduction Chip Connection (C2) is an attractive method for ultra fine pitch peripheral flip chip interconnection.[1] A copper pillar and a solder bump are formed on aluminum pads on the chip. The surface of the pads on the substrate is Cu- OSP (Organic Solderability Preservative) and a pre-solder is not required. The flip chip assembly is performed using the reflow process, which is same as the surface mount technology. When C2 is used with surface mount technology where the pads may be gold, the surface of the pads for the flip chip assembly would also be the gold. Wettability of solder on gold would be better than that on copper. Therefore the solder on the copper pillar on the chip may wet too much along the pad on the substrate and the solder shape may be deformed. To analyze the concern, interconnection using C2 was made on a substrate whose surface of the pads were DIG, which can be applied to ultra fine pitch pads.[2, 3] To discuss the dependence of solder joint shape on the contact angle of solder on the pads, a calculation was performed. A mechanical analysis was performed to understand the dependence of reliability on the shape of solder joints. The stress in the low-k layer is discussed as well as the strain in the solder because chip-package interaction is one of the challenges in the advanced packaging development.[4, 5] 2. Experiments and Calculations 2.1 Solder wetting on pads on the substrate Interconnection was made with C2 on both Cu-OSP pads and DIG pads of the substrate to compare how the solder wets on the pads during reflow. The thickness of the DIG was 0.06 μm to keep enough thickness to prevent diffusion of gold into copper pads.[3] 50 μm-pitch test vehicles (TV) which are shown in Fig. 1 were used for the experiments. The solder resist opening is a slit window because an individual opening cannot be formed on the fine pitch pads.[1] The size of the copper pillar was 35 μm square and the width of the copper pad was 25 μm. The solder resist opening was varied as 150 μm and 300 μm. The wetting of solder will be stopped at the edge even when the wetting was excessive. A no clean flux was applied on the TV substrate, 95

Transactions of The Japan Institute of Electronics Packaging Vol. 4, No. 1, 2011 and the TV chip was mounted on the substrate, and the TV was put into reflow furnace in nitrogen atmosphere.

The cross section was performed both parallel and vertical aspects to the longer direction of pads. 2.

The solder shape in a static condition can be obtained in the method.

An example of the calculation is shown in Fig. 3. An ini- Fig. 1 Substrates of test vehicles (TV). tial shape of solder was set before the calculation as shown in Fig. 3 (a).

[1] Then, only the shape of solder was modified to reduce the surface energy and gravitational potential energy as shown in Fig. 3 (b).

2 Transactions of The Japan Institute of Electronics Packaging Vol. 4, No. 1, 2011 and the TV chip was mounted on the substrate, and the TV was put into reflow furnace in nitrogen atmosphere. Cross-sectional observations were performed to know the solder shape on the locations shown in Fig. 2. The cross section was performed both parallel and vertical aspects to the longer direction of pads. 2.2 Solder shape calculations The solder shape was calculated using Surface Evolver which is widely used software [6, 7] to discuss the shape of the solder theoretically. The solder shape in a static condition can be obtained in the method. Although there is a report on the calculation of a dynamic movement of solder during reflow,[8] such a calculation was not performed in this study for simplicity. An example of the calculation is shown in Fig. 3. An ini- Fig. 1 Substrates of test vehicles (TV). tial shape of solder was set before the calculation as shown in Fig. 3 (a). The shape of solder which is on two sides of the copper pillar was used as the initial shape based on our previous experiments.[1] Then, only the shape of solder was modified to reduce the surface energy and gravitational potential energy as shown in Fig. 3 (b). The chip position and the substrate position were fixed during the calculation. That is, the solder joint height which is the gap between the copper pillar on the chip and the pad on the substrate was fixed. Therefore, we need to perform various calculations to obtain the stable solder joint height based on the surface energy and gravitational potential energy. The solder joint heights were varied from 3 μm to 9 μm. 2.3 Mechanical analysis Mechanical analysis was performed in parallel with solder shape calculations to obtain strain of solder and stress in low-k layer. Three-dimensional models were used for the analysis as shown in Fig. 4 (a). A volume average is selected to compare the strain of solder among the models because the solder is meshed in tetrahedral shape.[9] Even though the shape of the mesh is a flat plate, the relative stress in low-k layer would be valid. The material properties used for the analysis are shown in Table 1.[10, 11] We performed a creep analysis using Norton s law for solder and the other materials are assumed to be elastic. The strain of solder and stress in low-k layer due to mismatch Fig. 2 Locations for cross section. (a) Birds-eye view of the model (Case 1). (a) Solder shape before calculation (initial condition). (b) Solder shape after calculation (obtained result). Fig. 3 Model for solder shape analysis. Solder joint height is the gap between copper pillar on a chip and pads on a substrate. (b) Cross-section view of the model (Case 1, 2, and 3). Fig. 4 Models for mechanical analysis. 96

Noma et al.: Peripheral Flip Chip Interconnection on Au (3/6) of Coefficient of Thermal Expansion (CTE) was obtained by putting shear displacement.

The shape of the solder was varied to three cases as shown in Fig. 4 (b).

The second case is that the solder wets on the pads of the substrate and does Table 1 Material properties for mechanical analysis. (a) Materials on which elastic analysis was used.

0 (b) Materials on which creep analysis (Norton s law) was used[11].

12 10 17 Solder at 80 deg.c 9.0 8.09 10 15 Solder at 140 deg.c 6.8 8.64 10 13 not wet on the sides of the pillar of the chip to form a small fillet (Case 2).

3 Noma et al.: Peripheral Flip Chip Interconnection on Au (3/6) of Coefficient of Thermal Expansion (CTE) was obtained by putting shear displacement. The displacement was determined based on the mismatch of CTE during the cooling down from the solidification point of solder to room temperature. The shape of the solder was varied to three cases as shown in Fig. 4 (b). The first case is that the solder wets on both pads of the substrate and two sides of the pillar of the chip to form a large fillet (Case 1). The second case is that the solder wets on the pads of the substrate and does Table 1 Material properties for mechanical analysis. (a) Materials on which elastic analysis was used. Material Coefficient of thermal expansion (CTE), GPa Young s modulus, ppm / deg.c Si SiO Cu Substrate[10] (b) Materials on which creep analysis (Norton s law) was used[11]. Norton s law is described as dε / dt = Aσ n, where ε is creep strain, t is time, A is creep constant, σ is stress, and n is creep index. Material n A, MPa/h Solder at 20 deg.c Solder at 80 deg.c Solder at 140 deg.c not wet on the sides of the pillar of the chip to form a small fillet (Case 2). The third case is that the solder wets on the pads of the substrate only where is right below the copper pillar of the chip and the fillet is not formed (Case 3). 3. Results and Discussion 3.1 Solder wetting on pads on the substrate The cross sectional photos of the joints are shown in Fig. 5. The contact angle on the top surface of the pads was obtained as 30 deg on Cu-OSP pads. The contact angle in other report varies largely due to the difference of soldering atmosphere and flux condition.[12, 13] When a solder ball and a copper plate were polished and cleaned to remove surface oxide and then heated in argon atmosphere without flux, the contact angle of the molten solder on the copper plate was about 50 deg.[12] On the other hand, when a solder ball was put onto a polished and cleaned copper plate and heated in air atmosphere using rosin mildly activated (RMA) flux, the contact angle was about 20 deg.[13] In our experiments, a no clean flux which has lower activity than conventional RMA flux was put onto copper pads with Cu-OSP and reflowed in nitrogen atmosphere. Therefore, we think that the contact angle obtained in our experiment is reasonable. The solder wetted widely on the DIG pads on the substrate. The wetting seemed like a halo [14] because the thickness was very thin. Although the thickness of the solder on the excessively wetted area was very thin, the solder volume of DIG samples around the copper pillar should be smaller than that of Cu-OSP samples. Such a Fig. 5 Cross sections of the solder joints (experimental). 97

4 Transactions of The Japan Institute of Electronics Packaging Vol. 4, No. 1, 2011 wide wetting is also reported on the solder connection on line-shaped pads whose surface is Electroless Nickel, Electroless Palladium & Immersion Gold (ENEPIG).[15] However, the degree of the wetting would be different because the material under the gold is copper in DIG, while the material under the gold is nickel in ENEPIG. The wetting of solder on DIG pads may be smaller than that on ENEPIG pads because of the larger diffusion constant of copper into tin ( m 2 /s at 200 deg.c) than that of nickel into tin ( m 2 /s at 200 deg.c).[16] More solder may be consumed by the pads to make IMC and less solder may wet along the pads in the case of DIG than the case of ENEPIG. We think that is the reason why the wetting was seemed like a halo and a too much wetting of solder was prevented in the case of DIG. 3.2 Solder shape calculations Solder shape calculations were performed on Cu-OSP samples using the contact angle obtained from Fig. 5. An example of the results is shown in Fig. 6. The calculated shape was similar to the experimental shape. It was found that the energy was the smallest (the most stable) when the solder joint height was 3 μm in the calculated range as shown in Fig. 7. The calculated results were not in agreement with the experimental results. The solder joint height was about 9 μm on all the conditions shown in Fig. 5, whose energy was not stable in the calculation. We think that the reason would be an inter-metallic compounds (IMC) formation. A scanning electron microscope (SEM) image of IMC is shown in Fig. 8. The shape of Cu 5 Sn 6 is rough and there is a large IMC on the chip side because a reflow to form the solder bump on the wafer was performed during bumping processes.[17] There would be some contact points where the IMC on the pillar on the chip and IMC on the pad on the substrate were touched during the reflow for flip chip joint. The touched IMC may keep the solder joint height in the large value. 3.3 Mechanical analysis The results of the mechanical analysis are summarized in Table 2. Ratios of each case compared to Case 1 are shown in the table. The strain in the solder was large in the case whose solder volume is small, which is in agreement with another report.[18] On the other hand, the stress in low-k layer decreased in the case whose solder volume is small. We think the reason is that the solder fillet which pulls the sides of the copper pillar in Case1 does not exist in Case2 and Case3. The solder joint made with C2 has excellent temperature cycle (TC) reliability.[1] If the solder volume was too small, a non-wet during reflow may occur when the warpage of the substrate was too large.[19, 20] Even though the reliability in solder joint and the non-wet should be considered, to reduce solder volume would be one of the solu- Fig. 6 Example of solder joint shape on Cu-OSP surface pad (calculated). The scales are common for (a), (b), and (c). Fig. 8 SEM image of solder joint (experimental). Table 2 Creep strain of solder and stress of low-k layer (calculated). Ratios of each case compared to Case 1 are shown. Case1 Case2 Case3 Fig. 7 Dependence of relative energy (surface energy and gravitational potential energy) on height of solder joint (calculated). Energy before bonding = 0. Von Mises creep strain of solder (volume average) Case1 = 1.00 Principal stress in low-k layer (maximum value) Case1 =

5 Noma et al.: Peripheral Flip Chip Interconnection on Au (5/6) tions to reduce stress in low-k layer. 3.4 Threshold solder volume to wet sides of copper pillar A smaller fillet which does not wet sides of pillars on the chip would be effective to protect low-k layer. Therefore, we calculated the threshold volume of solder to wet copper pillars in the TV which we used. The height of solder joint was fixed at 9 um in the calculation because the height of solder joint would be limited by the IMC formation as described in section 3.2. The results are shown in Fig. 9. To wet the sides of the copper pillars, the solder volume should be larger than the volume of hexahedron which is composed of bottom surface of the pillar and the top surface of the pad where the solder was wet. The area of the wet surface can be obtained from the contact angle. Thus, the threshold volume V was calculated by the following formulas. V = (h/6) (Ab + ab + 2(ab + AB)) (1) A = a + 2 (h / tanθ) (2) where h is the height of solder joint, a and b are the length of the side of copper pillar on the chip, A is the length of the wet surface on the pad on the substrate, B is the width of the pad on the substrate, and θ is the contact angle. The solder volume in the experiment is shown in a triangle in Fig. 9. The volume was above the threshold and the solder was wet onto the sides of pillars of the chip as shown in Fig. 5 which is in agreement in the calculation. Not only to reduce the solder volume but also to reduce contact angle would be effective to prevent wetting of solder onto the pillars on the chip. If the diffusion of gold into copper is in an acceptable level, DIG on pads on substrates would be attractive not only for compatibility to assemble with surface mount components but also for chip-package Fig. 9 Dependence of threshold volume of solder on contact angle (calculated). interaction improvement. 4. Summary Interconnection on a substrate whose surface of the pads were DIG was made with C2 using solder-capped copper pillar bumps on the chip and using reflow process. Calculations to discuss the solder shape and a mechanical analysis to understand the dependence of reliability on solder shape were performed. Following results were obtained. The solder wets widely on the DIG pads on the substrate, which results in small solder fillet around the pillar of the chip. To minimize solder fillet formation around the pillar of the chip can reduce stress in low-k layer. To prevent solder fillet formation, not only to reduce solder volume but also to reduce contact angle of solder on pads on the substrate is effective. If the diffusion of gold into copper is in an acceptable level, DIG would be attractive not only for compatibility to assemble with surface mount components but also for chip-package interaction improvement. References [1] Y. Orii, K. Toriyama, H. Noma, Y. Oyama, H. Nishiwaki, M. Ishida, and T. Nishio, Ultrafine-Pitch C2 Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps, Electronic Components and Technology Conference, pp , May [2] D. Kim, P. Bhimaraj, N. Watts, Y. Isao, C. Kumar, and Y. Xu, Evaluation of DIG (Direct Immersion Gold) as a New Surface Finish for Mobile Applications, Electronic Components and Technology Conference, pp , June [3] H. Noma, Y. Oyama, H. Nishiwaki, M. Takami, T. Takatani, K. Toriyama, and Y. Orii, Wettability and Reliability for Double-Sided Assembly with Chip Connection (C2) Flip-Chip Technology, Transactions of The Japan Institute of Electronics Packaging, Vol. 2, No. 1, pp , December [4] P. Brofman, IBM s Packaging Technology Roadmap and the Collaboratory approach to Advanced Packaging Development, International Conference on Electronics Packaging, pp. 1 6, April [5] G. Dubois, Chip-Package Interaction from a Low-k Materials Perspective, International Conference on Electronics Packaging, pp , May [6] K. A. Brakke, The Surface Evolver, Experimental 99

6 Transactions of The Japan Institute of Electronics Packaging Vol. 4, No. 1, 2011 Mathematics, Vol. 1, No. 2, pp , [7] S. C. Tower, B. Su, and Y. C. Lee, Yield Prediction for Flip-Chip Solder Assemblies Based on Solder Shape Modeling, IEEE Transactions on Electronics Packaging Manufacturing, Vol. 22, No. 1, pp , January [8] A. Shojiguchi and H. Ishida, Simulation of solder joint and warping of LSI packages, The Papers of Technical Meeting on Electronic Circuits, Institute of Electrical Engineers of Japan, Vol. ECT , pp , November 2010 (in Japanese). [9] R. Darveaux, Effect of simulation methodology on solder joint crack growth correlation, ASME Journal of Electronic Packaging, Vol. 124, pp , September [10] K. Okamoto, M. Kuzuno, and T. Nishio, Material Property Modeling by Using the Thermal Deformation Measurement System, International Conference on Electronics Packaging, pp , April [11] Q. Yu, Solder joint reliability analysis of assembled components using ANSYS, Mechanical CAE NEWS, Vol. 3, pp.13 15, September 2005 (in Japanese). [12] X. R. Zhang, Z. F. Yuan, H. X. Zhao, L. K. Zang, and J. Q. Li, Wetting behavior and interfacial characteristic of Sn-Ag-Cu solder alloy on Cu substrate, Chinese Science Bulletin, Vol. 55, No. 9, pp , March [13] M. F. Arenas and V. L. Acoff, Contact Angle Measurements of Sn-Ag and Sn-Cu Lead-Free Solders on Copper Substrates, Journal of Electronics Materials, Vol. 33, No. 12, pp , December [14] S. V. Sattiraju, B. Dang, R. W. Johnson, Y. Li, S. Smith, and M. J. Bozack, Wetting characteristics of Pb-free solder alloys and PWB finishes, IEEE Transactions on Electronics Packaging Manufacturing, Vol. 25, Issue 3, pp , July [15] R. Pendse, C. H. Cho, M. Joshi, K. M. Kim, S. H. Kim, SS. Kim, H. T. Lee, K. Lee, R. Martin, A. Murphy, V. Pandey, and C. Palar, Low Cost Flip Chip (LCFC): An Innovative Approach for Breakthrough Reduction in Flip Chip Package Cost, Electronic Components and Technology Conference, pp. 1 9, June [16] D. Toyoshima, K. Yasaka, T. Sakai, T. Akamatsu, N. Imaizumi, S. Sakuyama, and K. Uenishi, Influence of UBM Layers on Electro-migration Behavior of Micro-joints using Sn-Ag Solders, International Conference on Electronics Packaging, pp , April [17] Y. Orii, K. Toriyama, H. Noma, and K. Uenishi, Solder alloy observation and its reliability of ultra fine pitch peripheral flip chip interconnection with Cu post bumps, Microjoining and Assembly Technology in Electronics Symposium, pp , February 2011 (in Japanese). [18] R. D. Pendse, K. M. Kim, K. O. Kim, O. S. Kim, and K. Lee, Bond-on-Lead: A Novel Flip Chip Interconnection Technology for Fine Effective Pitch and High I/O Density, Electronic Components and Technology Conference, pp , May [19] H. Noma, K. Toriyama, and Y. Orii, Effects of warpage and underfill material on assembly and reliability of System-in-Package, Microelectronics Symposium, pp , September 2008 (in Japanese). [20] V. D. Khanna and S. M. Sri-Jayantha, Methodology for Predicting C4 Non-Wets During the Chip Attach Process, Electronic Components and Technology Conference, pp , June

Introduction of IMS Technology for Advanced Solder Bumping on Wafers / Laminates

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