Adapted Assembly Processes for Flip-Chip Technology With Solder Bumps of 50 µm or 40 µm Diameter

Transcription

1 Adapted Assembly Processes for Flip-Chip Technology With Solder Bumps of 50 µm or 40 µm Diameter Rainer Dohle, Senior Member, IEEE 1*, Florian Schüßler 2, Thomas Friedrich 1, Jörg Goßler 1, Thomas Oppert 3, and Jörg Franke 2 1 Micro Systems Engineering GmbH, D Berg, Schlegelweg 17 2 Universität Erlangen-Nürnberg, Lehrstuhl für Fertigungsautomatisierung und Produktionssystematik, D Nürnberg, Nordostpark 91 3 PachTech GmbH, Am Schlangenhorst 15-17, D Nauen * Corresponding author, rainer.dohle@mse-microelectronics.de, , Abstract The further miniaturization of electronic packages is driven by a large variety of applications with high requirements on pitch and form factor. This will be conducive to higher I/O-counts and a reduction of the solder bump size. In this work, new cost-efficient solder bumping and adapted assembly technologies for the processing of flipchips with a pitch of 100 µm (as well suitable for a pitch of 60 µm) and solder ball diameters of 40 µm or 50 µm, respectively, were demonstrated. The wafer bumping has been realized using a highly efficient wafer level solder sphere transfer process. This technology uses a patterned vacuum plate to simultaneously pick up all of the preformed solder spheres, optically inspect for yield, and then transfer them over to the wafer at once. Initially the flip-chips have been assembled automatically on special BT- and FR4-material using reflow soldering and high performance underfill that has been subject of in-depth investigations. Through this, the long term reliability of the lead free solder joints could be increased significantly on state-of-the-art subtractive printed circuit boards (PCBs) with solder mask. But we found, that a solder bump size of 50 µm seems to be the technological limit when tested according to MIL- STD883G, method , condition B. That is why we investigated the use of alternative substrates for chips with 40 µm solder bumps as well. For cost efficiency reasons, all processes investigated base upon standard processes of the surface mount technology, but are adapted to the requirements of highly miniaturized components. Our results of the reliability tests will be discussed. Additionally, an analysis of the failure mechanism will be presented. Introduction The aim of the experimental study presented in this paper was the bumping of flip-chips with 100 µm pitch and solder spheres of 40 µm or 50 µm, respectively, in diameter, the structuring of FR4- and BT-substrates with the necessary fine pitch structures, and the assembly of the dies using standard production equipment. This makes the process chain from wafer bumping to flip-chip assembly and underfill very cost efficient and flexible even for small quantities. Due to size reduction and cost saving potential, flipchip technology has gained importance in the field of highly miniaturized electronic devices. The oldest bumping technique still in industrial use, called C4 (Controlled Collapse Chip Connection), using evaporated solder, was developed by IBM [1], [2]. Specific bumping processes have been established in recent years. Common methods for applying solder onto the semiconductor wafer are for example stencil printing [3], solder jetting [4], electroplating [5], and C4NP [6]. The most important requirements for bumping are a high yielded, fast and cost efficient process as well as, in many cases, low tooling costs. Stencil printing (followed by reflow of the solder paste) is a very productive process. For the bump sizes considered in this paper it is not well suited, however. Solder jetting is appropriate for prototypes with medium size solder bumps. Commonly used for high bump counts per wafer and extremely fine pitches is the electroplating process. Due to the complex processes and mask manufacturing, the electroplating bumping technology is very expensive, especially for small wafer quantities. The most critical cost factor of the C4NP process is the use of molds, since these impact directly the per wafer bumping costs. Therefore is the C4NP process too expensive for small wafer quantities. Wafer Bumping Process The wafer bumping has been realized using the highly efficient and flexible wafer level solder sphere transfer process, also known as gang ball placement that is described in detail in [7]. The wafer level solder sphere transfer tool can integrate several of the most necessary operations when depositing solder volumes on wafer level, like flux coating, solder reflow, inspection and rework processes, but can be configured to expand and complement the existing equipment and processes. The main process steps of the bumping technology are shown in figure 1. Characteristic for this process is that all solder spheres needed for one wafer are transferred to the wafer in one single process step. This is realised with a patterned vacuum stencil with openings corresponding to the UBM on the wafer. The tool is placed over and then lowered down to the sphere reservoir. After that, vacuum is applied to selectively pick up the solder spheres (1).

2 After inspection for missing and extra spheres, the tool is aligned to the wafer (2). By lowering the stencil to the wafer, the solder spheres are brought in contact with the wafer surface (3) on which flux has been pre-applied. After turning off the vacuum and raising the tool follows the reflow of the solder spheres. SnAgCu alloy and are placed on a NiAu UBM realized in an electroless nickel process. Each row has a different passivation opening for solder spheres measuring between 60 µm (first row), 50 µm (second row), 40 µm (third row), and 30 µm (fourth row). The I/O-count is dependent on the solder sphere size for example 360 I/Os for 40 µm spheres, 368 I/Os for 50 µm spheres. 277 dies are placed on one wafer making it per wafer 99,720 I/Os or 101,936 I/Os, respectively for 40 µm spheres or 50 µm spheres, respectively. In order to detect failures during the reliability tests, each die has a circumferential daisy chain structure. Figure 1. Steps for wafer bumping [Courtesy of PacTech GmbH] As yet with this technology it was possible to place solder spheres of 60 µm in size with high yields [8], [9]. For the placement of 50 µm and 40 µm solder spheres the process itself has been not modified, since the placement accuracy for tool to wafer of 15 µm is sufficient. By this, the technology can be still considered a standard process for wafer bumping. However, for the placement of 50 µm and 40 µm solder spheres the stencil quality and the solder sphere handling had to be improved in order to secure sphere pick up and release. Sequential solder sphere placement techniques are described elsewhere [10], [11]. Substrate layout and structuring It was the aim of the substrate structuring, that standard processes of the subtractive PCB technology can be used. After etching and application of the solder mask, a NiAu surface finish has been applied to the copper circuitry. The layout of the test coupons used in this study is shown in figure 3. This layout is well adapted to new routing-efficient interconnect structures for fine pitch applications described in [35] that help reduce substrate layer count and complexity. Figure 3. Layout of the test PCB with solder mask The flip-chip and PCB structures are realized in a way that one layout can be used for chips with 60 µm, 50 µm, 40 µm, or 30 µm solder spheres. A daisy chain connection is integrated for each of the ball sizes and each chip can be connected for online measurements during reliability testing. Considerations regarding the flip-chip packaging architecture can be found elsewhere [12]. Figure 2. Chip with 50 micron solder spheres at the second row and 40 micron solder spheres at the third row, respectively The silicon die has a thickness of 0.8 mm and a side length of 10 mm. The solder spheres are made of a

3 Figure 4. BT PCB with solder mask. The second row from top is for chips with 40 µm solder spheres, the third row is for solder spheres with 50 µm solder spheres In addition to the PCB experiments, thin film ceramic has been used in order to overcome limitations of the structure quality due to the subtractive PCB process used for our test coupons, especially the negative effect of the solder mask (see chapter reliability issues). Figure 6. View in the assembly machine (Datacon 2200 apm) with PCB (6 chips per test specimen) Underfill Process Due to the heterogeneous material mix of the silicon die, the solder and the substrate material, a large CTE mismatch is inevitable. In order to absorb the thermal stress induced into the solder joints, underfill is used. The underfill technology can be divided into capillary flow and no flow processes. With the used capillary flow process, the epoxy is applied after reflow soldering. The underfill flows underneath the die using the capillary effect. The flow rate and homogeneity of the underfill process is highly dependent on the gap size, the filler particle size, and the existence of residues of flux from the reflow process. Underfill flow prediction models with consideration of the effects of substrate surface, temperature-dependent underfill viscosity on flow time, flow front shape and void formation during the underfill process can be found elsewhere [13]-[19]. We used standard curing of the underfill in a batch process. Figure 5. Ceramic test coupon. The shown thin film structures are for the assembly of chips with 40 µm solder spheres Flip-Chip Assembly Besides the necessity of manufacturing very fine pitched bumps in order to cope with steady miniaturization, the production processes for assembling the flip-chips onto the substrates were improved as well. Assembly machines used in high throughput production lines have to meet the needed placement accuracy as well and the vision systems have to detect the highly miniaturized bumps with high reliability. We used a Datacon 2200 apm machine with a placement accuracy of ± 10 3s. Figure 7. Flip-chip 10 mm by 10 mm in size on BT PCB (with underfill)

4 Results Assembly Yield The following table summarizes the assembly yield of some of our experiments with PBCs: Table 1. Assembly yield with PCBs Solder ball diameter 50 µm Yield after reflow 90 % Yield after underfill 90 % 40 µm 50 % 30 % We found, that the thickness of the solder mask of about 18 micron, the tolerances of the openings in the solder mask, and the tolerances of the solder mask registration are major drawbacks for a high assembly yield. Figure 8 shows a cross section of a flip-chip with 50 µm solder spheres on a FR4 PCB. The solder mask (not clearly visible) causes the irregular shape of the solder bumps. Figure 9 shows a cross section of a flip-chip with 40 µm solder spheres on a FR4 PCB. The tolerance of the solder mask registration causes the misalignment and irregular shape of the solder bumps. Due to the mentioned drawbacks we observed a technological limit for flip-chip assemblies employing PCBs in current state-of-the-art subtractive technology at about 50 µm solder bump size. That is why we investigated flip-chip assemblies with ceramic substrates as well. The following table shows the assembly yield of our experiments with thin film ceramic: Table 2. Assembly yield with thin film ceramic Solder ball diameter 40 µm Yield after reflow 80 % Yield after underfill 80 % The low tolerances of the thin film structures have been conducive to a reasonable yield. Instead a solder mask, unwettable metal prevents the flow of the solder away from the solder pad. Figure 10. Cross section of a test coupon with a chip with 40 µm solder spheres on thin film ceramic, showing the daisy chain structure (top: substrate, bottom: chip) Figure 8. Cross section of a test coupon with a chip with 50 µm solder spheres on a FR4 PCB (top: chip, bottom: PCB) Figure 11. SEM image of a cross section of a flip-chip with 40 µm solder spheres on thin film ceramic (magnification 2700x). The filler material of the underfill is visible at the left and the right side (top: chip with UBM, bottom: substrate) Figure 9. Cross section of a test coupon with a chip with 40 µm solder spheres on a FR4 PCB (top: PCB, bottom: chip) Reliability Issues One of the main reliability concerns in the flip-chip technology when using the highly miniaturized components on substrate level is the large mismatch of the coefficient of thermal expansion (CTE) between silicon

5 die and PCB. This thermal mismatch causes stress/strain in the solder joints. Various studies on solder joint reliability describe in detail simulation models and practical experiments. According to [24], the solder joint geometry has a highly significant influence on long term stability of the interconnections. Important parameters are the stand-off height and the contact angles of the solder joints on die and substrate side. To equalize the large thermal expansion mismatch, underfill material is used in order to improve the reliability of the interconnections. Although some of the already mentioned influencing factors become less significant if underfill is applied, new possible influences appear, for instance the size of voids in the underfill [16]. As subsume, the key factors that influence the long term reliability of the interconnections are named in [17]: The geometry of the solder joint, the underfill material, and the dimensions and the layout of the die. The following table shows some of the reliability tests we performed: Table 3: Reliability tests Test 1 Voltage between two daisy chains 85 C/85% r. h., 3V Test 2 Life test, with 85 C/85% current through r. humidity, the daisy chain 100 ma Test 3 Temperature -55 C / cycling +125 C Test 4 Steady state life dry heat +125 C / 1000 h EIA/JESD22- A101-B EIA/JESD22- A101-B MIL-STD 883G, Meth , C. B MIL-STD 883G, Meth Figure 12 shows the results of the life test with current flow through the daisy chain. Details can be found in the literature [20]-[23]. The PCB test coupons with the selected underfill passed this test. resistance between adjacent daisy chains for at least 2000 hours. Figure 13. Test with a voltage of 3 V between two daisy chains at 85 C/85% relative humidity Figure 14 shows a SEM image of a solder contact between PCB and chip after 2000 temperature cycles between -55 C and +125 C. No cracks are visible. The EDX investigation revealed that there is still ductile solder material between the intermetallic layers adjacent to chip and PCB metallization. [27] Figure 12. Life test at 85 C/85% r. h. with a current flow of 100 ma through the daisy chain (BT PCB) Figure 13 shows the results of the migration test, where a voltage between two daisy chains is applied. The selected underfill guaranties the required isolation Figure 14. SEM image of a cross section of a flip-chip (bottom) with 50 µm solder bumps on a BT PCB (top) after 2000 temperature cycles -55 C/+125 C (magnification1800x). The irregular shape of the solder bump is caused by the solder mask Figure 15 shows the temperature cycling results for flip-chips with 40 µm solder balls on PCBs made from BT according to MIL-STD 883G, Method 10108, Condition B. Figure 16 shows the temperature cycling results for flip-chips with 40 µm solder balls on thin film ceramic according to MIL-STD 883G, Method , Condition B. No interruptions of the daisy chain could be observed.

6 Failure rate [%] Failure rate in dependence on the number of temperature cycles (chips with 50 micron solder bumps on BT PCB) Number of temperature cycles -55 C/+125 C Figure 15. Failure rate of flip-chips with 50 µm solder bumps on BT PCBs in dependence on the number of temperature cycles -55 C/+125 C (n=14) Failure rate [%] Failure rate in dependence on the number of temperature cycles (chips with 40 micron solder bumps on thin film ceramic) Number of temperature cycles -55 C/+125 C Figure 16. Failure rate of flip-chips with 40 µm solder bumps on thin film ceramic in dependence on the number of temperature cycles -55 C/+125 C (n=18) Discussion The interruptions of the daisy chain of chips with 50 µm solder bumps on PCB, that occur before 1000 temperature cycles can be considered as early failures. The reason for those early defects could be traced back to PCB tolerances, especially of the solder mask registration. The slightest variation from the nominal dimensions of the opening in the solder mask and their position leads to solder joints of irregular shape which is conducive to an uneven strain distribution in the solder joints causing an early failure. The openings in the thick solder mask are prone to voids that have a negative impact on reliability of the assembly. The results obtained with BT PCBs and High-T G FR4 PCBs were very similar. The lack of a thick solder mask at the thin film ceramic substrates and the very precise structuring of the circuitry are very advantageous for yield and underfill application: The larger gap between chip and substrate surface guarantees a perfect flow of the selected high performance underfill. No voids could be found. Additionally, the low CTE mismatch between the flip-chip and the inorganic substrate material is beneficial for the reliability of the solder connections Conclusions In this work, detailed experimental study has been carried out to assess the assembly processes for flip-chips with 50 µm solder spheres or 40 µm solder spheres, respectively. Flip-chip assembly of bumped chips and underfill process have been demonstrated. Additionally, package level reliability test results for flip-chips with 50 µm solder bumps and 40 µm solder bumps have been presented. Some important results are summarized as follows: 1. A flip-chip assembly technology is demonstrated for chips with 50 µm and 40 µm solder spheres, respectively, using organic PCBs. 2. PCBs in state-of-the-art subtractive technology impose currently restrictions to further miniaturization of solder bump size and pitch. 3. Assembly and underfill processes of flip-chips with 40 µm solder spheres on thin film ceramic were also studied and it was found that the yield and reliability results can be improved significantly as compared with organic substrates. 4. The flip-chip assemblies have passed the reliability tests in terms of thermal cycling tests, high temperature storage, and 85 C/85% relative humidity tests with applied current or voltage, respectively with good results when using appropriate underfill. 5. The failure mechanisms for partly low yield and early failures have been identified, what helps to increase the assembly yield and to prevent early failures in prospective experiments. The innovations in flip-chip technology will help meet the demands of packaging for next generation medical applications [34], mobile applications [35], and millimeter-wave applications [36], [37]. Acknowledgments This work is result of a collaboration project between Micro Systems Engineering, GmbH, PacTech GmbH, KSG Leiterplatten GmbH, and the University of Erlangen- Nuremberg (Institute for Manufacturing Automation and Production Systems). The authors would like to thank Mr. Georgi Georgiev (KSG) for supplying the PCBs, Mr. Bernd Burger and Mr. Andreas Wirth for performing of the reliability tests and cross sectioning of samples, and Professor Marek Gorywoda (University of Applied Sciences Hof) for the SEM/EDX investigation. This research and development project is funded by the German Federal Ministry of Education and Research (BMBF) within the grant 02PG236X and managed by the Project Management Agency Karlsruhe (PTKA). The authors are deeply grateful for this support and are responsible for the contents of this publication.

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