SURFACE FINISH FOR ELECTRONIC PACKAGING WITH LEAD-FREE SOLDERS. Abstract

Transcription

1 ~ ~ SURFACE FINISH FOR ELECTRONIC PACKAGING WITH LEAD-FREE SOLDERS PDF- I. V. Kadija J. A. Abys AT&T Bell Laboratories 600 Mountain Avenue Murray Hill, NJ Abstract Current trends in the preservation of our environment are forcing the electronic industry to seriously consider lead-free solders. In a variety of options such as Tin alloys with Indium, Bismuth, Silver, Zinc and others, the issues of their functional performance involves their solderability to the substrate. Clearly, good fatigue characteristics, tensile strength, ductility, adequate melting temperature and acceptable material cost may not be utilized if the solder requires aggressive fluxes or its "spreadability" is inadequate. Thus, a lead-free solder applied on a substrate engineered for good solderability becomes a viable packaging tool. We have tested a variety of multilayer finishes developed at AT&T for applications on PWBs and MCMs and established that they can be successfully utilized in lead-free soldering processes. In this paper, we discuss experimental details and solderability results with some of the viable lead-free solders. 553

2 1 INTRODUCTION Both the PWB and the multi-chip module (MCM) substrates play a critical role in electronic packaging. These substrates are under market pressures for increased performance while reducing their space, volume and weighp3. Under such circumstances, the economy of materials used in their fabrication, and the fbnctional performance of their building blocks have become increasingly demanding. Naturally, with the reduction of the bulk materials, the surface finish of the components plays an increasingly more important role. PWB technology is moving towards surface mount (SMT) and chip-on-board (COB) applications from the more conventional packaging processes such as through-hole mounting. By eliminating through-holes and in some instances the first level packaging (involving wirebonding, encapsulation and numerous plating steps over the components to be attached to the PWB), the packaging process has become more efficient. Both of the above techniques, SMT and COB, offer considerable space savings and increase the packaging density. In the absence of an established technology for high density PWB substrates, the industry is utilizing MCMs with an increasing rate. In such a market environment, the MCMs play an increasingly more important role. MCMs utilize, in most practical applications, a combination of PWB, Hybrid Circuit and other advanced processing techniques typically reserved for IC fabrication. MCMs are smaller in size than the PWBs and as such allow for a better control of the manufacturing process. In many instances, this entails applications of laser imaging, plasma etching, vapor depositions, etc. Similar to the advanced printed wiring boards, MCM processes also involve multiple parts attachment and wirebonding, soldering or brazing. In these steps as well as for the ultimate attachment into the electronic device, the surface finish of the MCM plays a very important role. In order to meet an increasing demand for improved performance in packaging, we have introduced a multilayer finish, PallaTechO MLS, which was demonstrated to meet the most stringent requirements4-5 for wirebonding and solderability. Currently, the inquiries from the market are indicating an increasing interest for lead-free solders in electronic 554

3 7 packaging. In response to this trend, we have more recently tested our finishes for compatibility with lead-free solders, commercially available and developmental materials. BACKGROUND INFORMATION In order to assemble various fbnctional active and passive parts electronic packaging typically entails several attachment and connecting procedures. These include wirebonding, soldering, encapsulation and die-attach. Of these, the most critical are the wirebonding and the soldering steps. The following is a brief description of some issues that must be addressed when designing a finish to meet high reliability wirebonding and solderability requirements. Wirebonding usually takes place the early stage of the assembly. Typically, a die is attached to the substrate by special solders or epoxy glues. This step is followed by wirebonding which may include some precleaning steps to secure the integrity of the bonds. From the perspective of solderability of the finish all of the above steps such as die-attach, cleaning and wirebonding are relevant. Epoxy glue used in die-attach processes can contaminate leads and pads designed for the soldering step. Furthermore, the cleaning step used to remove an organic contaminant from the bumps designed for wirebonding, although beneficial to wirebonding, may be damaging to the solderability of the rest of the parts exposed to the cleaning step. Some of the cleaning steps may involve oxygen plasma cleaning. The wirebonding procedure by itself is also a thermal procedure. Depending on the type, thennosonic or thennocompressive, and on the speed of operation the parts may be exposed to a range of temperatures for several minutes. This thermal aging has an effect on solderability of the parts and it must be taken into account in the process and part design. A well designed finish must maintain the wirebond quality through the packaging procedure. In most assembly operations additional thermal treatment of the parts takes place after the wirebonding step, including soldering andor brazing at elevated temperatures. The wirebond must maintain its hnctionality regardless of these thermal 555

4 treatments. The interdiffision at the bond interface which naturally occurs during thermal excursions should not be damaging to the wirebond strength. Soldering is being applied in most manufacturing and assembly operations at the end of a series of packaging procedures which involve some of the above cited strong environmental effects. Thus, the finish of the parts must be solderable not only as plated but also following the adverse environment conditions. Our multilayer finishes have been designed to meet these adverse packaging conditions. Our PallaTechO MLS (Au) multilayer finish was demonstrated to remain wirebondable and solderable following drastic environmental effects such as Oxygen Plasma treatments applied in surface mount technology over the advanced printed wiring boards. The kind of universal finish capability offered by such multilayer finishes as PallaTechO MLS would be convenient if extended throughout the various packaging processes including the lead-free solders. With the advent of a variety of lead-free solders designed to meet various packaging requirements, we have initiated a series of tests of our multilayer finishes to establish their hnctionality with such solders. Lead-free solders options are numerous798. However, for substrates such as PWBs and MCMs with polymedmetal laminates the solder melting temperature and operating temperatures must be limited to avoid permanent damage to the substrate. This restriction reduces the lead-free solder options to lower temperature alloys such as SnBi, SnAg and SnInZn. Multilayer finishes are typically composed of palladium and palladium alloys. These have already demonstrated their exceptional performance in leadframe packaging applications4.5. A hyper-thin layer of soft gold may be utilized to even hrther enhance their performance. We have applied both the palladium only and the palladium with thin gold top layer in this performance evaluation. The following are the substrate, multilayer finishes, solders and fluxes utilized in this study. Substrate. FR-4 Epoxy laminate, 60 mils thick, with 1.4 mil copper on two sides. The coupons were 1" by 6" panels, each with three preforms of solder/flux applied at 1.5 inches distance. 556

5 Finish # Nickel Pd Strike" PdNi (80/20)* Pd* Au (soft plate) *Proprietary plating chemistries described elsewhere. Control finish was imidazol coated copper. d-free Solders SnBi and SnX Control solder SnPb (60/40) Fluxes R-nonactivated rosin flux and RMA, mildly activated rosin flux Multilayer finishes have been developed and are currently utilized by the industry following standard testing. These usually involve MIL-STD-883, Methods 2003 and The two test methods are utilized to veri@ the two main properties required in soldering processes i. e. good quality surface coverage and timely surface coverage required for efficient manufacturing. In the course of solderhnterface interaction study an initially more information test is the spreadbility test. In this, solder preforms are applied to the coupons with the surface finish together with the choice of flux. The samples are then placed in the furnace with the appropriate temperature and atmosphere, held for a determined time and withdrawn for evaluation of characteristic features obtained during soldering melting and interaction with the finish. Test temperature is determined by the type of solder utilized. The duration of the test is typically 1-5 minutes. 557

6 RESULTS AND DISCUSSION Photographs 1 through 6 show the spreadability test results obtained with SnPb (60/40, 23 5OC operating temperature) and SnBi (200OC operating temperature) solders with RMA flux. Photographs 1-3 are samples of SnPb applied to the three finishes: #1, #2 and the control sample. Clearly, all samples show good spreadability and a smooth finish. Multilayer finishes show somewhat better spreadability than the imidazol coater copper. CONCLUSIONS Advanced electronic packaging including PWBs and MCMs demands a multihnctional capability from the finish utilized in interconnect manufacturing. Clearly, a copper finish alone, while solderable, it is not wirebondable even if corrosion resistance is improved by organic inhibitors. Furthermore, interaction with encapsulants and other packaging materials does not provide lasting fimctionality over bare copper. Cleaning steps, which are in most instances mandatory, while removing organic or inorganic contaminants are usually detrimental to bare copper. Under such circumstances, some noble metal finishes must be utilized. In this work, palladium multilayer finishes have been demonstrated to have efficient solderability with selected lead-free solders. Thus, in addition to having superior hnctionality for wirebonding, cleaning and encapsulation, these finishes have acceptable solderability with lead-free solders, a combination of characteristics that are needed today in advanced packaging. 558

7 REFERENCES 1. R.R. Tummala and E. J. Rymaszewski: Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, C. W. Eichelberger, et. al., Increasing Functionality, A 3D Packaging Technology is Applied, Advmed Pack aging. Vol. 4, NO. 2, 1995, p E. Bert, Meeting the Challenges of PCMCIA Card Fabrication, Plectronic Packarring Production, Vol. 35, No. 4, 1995, p I.V. Kadija, et. al., Solderability Characteristics of Palladium, Palladium-Nickel, Hard and Soft Gold Electrodeposits, Proc. AEsF - Int, June 22-25, 1992, Vol J. A. Abys, et. al. US Patent No. 5,360,991 (1994) Japanese Patent Application, H , Filed July 29, I. V. Kadija, et. al., Thin Multilayer Palladium Coatings for Semiconductor Packaging.. Applications, Part I-Solderability, Platxng & Su&ce Finish ins, February, 1995, p J. S. Hwang, Overview of Lead-Free Solders for Electronics and Microelectronics, Proc. of the Surface Mount International Conference, San Jose, CA, August 28, M. T. McCormack and S. Jin, The Design and Properties of Pd-Free Solder Alloys, L sf Elect ronic Maten '&, In Press. 559

8 ... Figure 1: Spreadability Test, SnPb(60/40) on Palladium multilayer finish #l 560

9 Figure 2: Spreadability Test, SnPb(60/40) on Palladium multilayer finish H2 561

10 562 Figure 3: Spreadability Test, SnPb(60/40) on imidazol coated Copper

11 Figure 4: Spreadability Test, SnBi(42/58) on Palladium multilayer finish

12 564 Figure 5: Spreadability Test: SnBi(42/58) on Palladium multilayer finish #2

13 . Figure 6: Spreadability Test: SnBi(42/58) on imidazol coated Copper 565

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