Automatic Package and Board Decoupling Capacitor Placement Using Genetic Algorithms and M-FDM

Transcription

1 June th 2008 Automatic Package and Board Decoupling Capacitor Placement Using Genetic Algorithms and M-FDM Krishna Bharath, Ege Engin and Madhavan Swaminathan School of Electrical and Computer Engineering Georgia Institute of Technology

2 Outline Is there ife in ASICs in the era of nanometer designs? l The Power argument Multiple-supply voltages Multiple-threshold voltages Voltage Islands Fine Grained, Coarse Grained eakage control Pushing ASIC performance with power neutral techniques 2

3 Competition: the problem with configurable fabrics What do you put on there : IP blocks, Memories, Datapaths, top-level logic Compounded by the problem of IP on chip. Gets even worse by all the options you want to consider to minimize power: Multiple voltages Multi-thresholds Voltage Islands Coarse Grain, Fine Grain eakage 3

4 The Power arrgument: exploiting ASICs Multi Vdd Multi threshold Voltage Islands With headers/footers Their application is very design specific. How many voltage islands, what size, what header/footer, how many lowvt gates etc.. Difficult to capture in configurable fabrics. ead to very interesting physical design problems 4

5 Flexible physical Design approach for dual-supply voltage design 5

6 Generic Voltage Island Power Grid 6

7 Fine grained voltage islands 7

8 Physical Design for Ultra--low leakage The same concept can be used to control leakage current with F/H cells in SOC designs 8

9 Voltage Island Power Issues Power Islands design Pros Reducing switching power dissipation Saving Standby component of power dissipation Cons More complicated with respect to static timing, Power planning and routing Floorplaning 9

10 Basic Data Structure Each core for individual islands Move two core each other Possibility of merging them each other ead to lower cost ower over head for level shifter 0

11 Integrated Floorplanning Chip level floorplanning Trying arrange the compatible islands in adacent position by cost function Island level floorplanning Applying to each newly merged island The composing cores inside the merged islands egalizing the newly generated floorplan

12 Solution Perturbation Island split move Split up into a set of islands Island voltage change move Voltage island support two or more legal supply voltage Voltage level switched to one of its legal voltages Multi-island voltage change move All the islands which supports li will be assigned to voltage li 2

13 Island Merging Chip level floorplanning The islands that are compatible are likely to be placed in adacent position Two high power consumers and heater dissipater can not be placed each to relief the heat and power issue. 3

14 Reliability-Aware SoC Voltage Islands Partition and Floorplan 4

15 Soft Error Rate (SER) & Component Reliability evel (CR) Characterization of component reliability level for a particular node: Soft error rate: Component reliability level: 5

16 Soft Error Rate (SER) & Component Reliability evel (CR) (cont.) Component reliability level for a macro cell Chip reliability level 6

17 Reliability-aware SoC voltage Island Partition Algorithm Penalty function: 7

18 Z Broadband Decoupling with Multiple Decoupling Capacitors Multiple decoupling capacitors with resonance at different frequencies are used for broadband decoupling However cross resonances (or anti resonances) occur and are undesirable Response is a function of placement Z target Of all possible combinations of decaps and corresponding placements, only a small fraction will satisfy specs C C2 C3 Frequency Automatic placement can be accomplished using an optimization engine 8

19 Single Plane Pair Case: Finite Difference Scheme Helmholtz wave equation: 2 2 t k u dj z Finite difference mesh using square cells (mesh size h) h At boundary, homogeneous Neumann condition is used (open circuit) A five-point approximation is applied to the aplace operator k d d t 2 2 dx dy d C h d 2 For lossless case, wave equation reduces to ui, ui, ui, ui, 4ui, Cui, I 0 This gives rise to an equivalent circuit 9

20 Single Plane Pair Case: Equivalent Circuit Representative equivalent circuit Unit cell model Number of nodes increases as O(w 2 ) where w is the linear dimension Overall admittance matrix size can be large What about solution efficiency? 20

21 Multilayer Finite Difference Method (M-FDM) Inductance matrix in multilayer unit cells An inductive loop is formed between each pair of planes However, each inductive loop is with reference to a local ground representing a return current path Shift reference nodes of each plane pair to the common ground Cross-sectional view of 3-layered package Plane Plane 2 Plane 3 Plane Plane 2 Plane 2 Plane 3 2

22 Inductance: Equivalent Circuit and Interpretation Combining the grounds results in a pair of coupled inductors + represents the total loop inductance between plane and plane 3 represents the loop inductance between plane 2 and plane 3 There is complete coupling of the magnetic fields between the two loops This is represented by the mutual element + 22

23 M-FDM: Combined Unit Cell and Equivalent Circuit Equivalent circuit R + + R + R + R C G R2 Unit cell model R + + R + R R R R + R + R + R R R C G C G + + R2 R2 R2 R2 R2 R2 R2 G2 R2 G2 C2 C2 R2 R2 Efficiency scales as R2 G2 C2 O(N.5 ) time an O(Nlog(N)) memory + R2 C G R2 G2 C2 R2 R2 Matrix structure is similar (block tridiagonal) K. Bharath, A.E. Engin, M. Swaminathan, K. Uriu and T. Yamada, Computationally Efficient Power Integrity Simulation for System on Package Applications, in Proc. of 44th DAC, pp , June

24 Approach Inputs: ibrary of decoupling capacitors Package/Board design with noise source locations Target impedance requirements (impedance, bandwidth) Number of capacitors to place Methodology: Each chromosome is a string containing decap values and corresponding locations GA works on an initial random population Uses concepts of elitism, mutation and crossover Output: Decap values and location that best satisfy target impedance 24

25 GA Encoding and Mechanics 2 No. of capacitors: 5 Chromosome length: 0 3 Parent C C3 C C5 C Parent Child C3 C2 C C4 C Crossover C C3 C C4 C Mutation C C2 C C4 C

26 Fitness Function Z Z target Fitness function: f i N port N freq w Z tar, Z, ( k) w2 Z tar, Z, ( k) k w and w 2 : empirically determined weights Frequency Z tar, : Target impedance (specification) at the th port Z, : Self impedance (simulated) at the th port 26

27 Capacitor ibrary Cap ESR (mω) ES (nh) Res. Freq (GHz) 27 pf nf Cap ESR (mω) ES (nh) Res. Freq (GHz) uf Madhavan Swaminathan and Ege Engin, Power Integrity Modeling and Design for Semiconductors and Systems, Prentice Hall,

28 Results: Placement 50 µm- 70 Capacitors 25 µm- 20 Capacitors 8 µm- 40 Capacitors 28

29 Results: Test Case Z tar 50 µm- 70 Capacitors 25 µm- 20 Capacitors Simulation Specs: - Time/ GA iteration: 20 s - Max iterations: µm- 40 Capacitors 29

30 Test Case 2: Multilayer Structure SSN can couple vertically in multi-layer structures Port 2 Port Decap placement can be optimized to suppress coupling between vertically separated ports Dimensions 2 mm X 97 mm Solid top and bottom layers Number of Decaps : 200 Z tar = 200 mohm 30

31 After Cap Placement No Capacitors Results: Test Case 2 Z tar 3

32 Thank you! 32

33 Reference Node Assignment for Two-Port Admittance Matrices V l I Y A V r V al I al Y A I ar V ar I 2 I bl I br V 2 l Y B V 2r V bl Y B V br Y Y A B V V l 2l Y Y A 2 B 2 V r V 2r I KC equations for isolated systems written When shifting ground of Y A to ground of Y B, enforce node current I bl to contain return I Rewrite KC equations for revised system I Provides complete system matrix 2 Y I V bl where, I Y V Y l I V 2 al I 2 V r ar 2l bl 2r br A A Val Vbl ) Y2 ( Var Vbr ) bl B ; V V B 2 V V V ; V V ( I I I I I I al ar bl br Y Y A A Y bl Y A A Y B V V V V V br bl br al ar br al 33

34 Reference Assignment for Inductances In this case, The combined 4-port system is represented by Can this be represented by an equivalent circuit? 34 Plane Plane 2 Plane 2 Plane 3 V l V 2l V r V 2r Y A Y B Y A Y B Y

35 M-FDM Results: Scalability and Timing Simulation setup: Dual processor 3.2 GHz workstation with 3 GB RAM # ayers # Nodes Time (s)/freq point 2 38, , , , , , , , representative layers of a realistic package 0 349,

36 Introduction VSI design issues Power optimization High performance, low power consumption Multi-function device on single chip Battery operated power saving chip 36

37 Introduction (cont.) Power consumption Active power and dynamic power 37

38 Introduction (cont.) Voltage islands Reduce active power and dynamic power Performance critical logics (procesor)use highest voltage Memory and control logics use lower voltage Place to nearby power pins evel converters needed Area and delay overhead 38