EMBEDDED passives are gradually replacing discrete

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1 IEEE TRANSACTIONS ON ADVANCED PACKAGING 1 Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package Prathap Muthana, Student Member, IEEE, Arif Ege Engin, Member, IEEE, Madhavan Swaminathan, Fellow, IEEE, Rao Tummala, Fellow, IEEE, Venkatesh Sundaram, Boyd Wiedenman, Daniel Amey, Senior Member, IEEE, Karl H. Dietz, and Sounak Banerji Abstract Embedded passives are gaining in importance due to the reduction in size of electronic products. Capacitors pose the biggest challenge for integration in packages due to the large capacitance required for decoupling high performance circuits. Surface mount discrete (SMD) capacitors become ineffective charge providers above 100 MHz due to the increased effect of loop inductance. This paper focuses on the importance of embedded capacitors above this frequency. Modeling, measurements, and model to hardware correlation of these capacitors are shown. Design and modeling of embedded capacitor arrays for decoupling processors in the midfrequency band (100 MHz 2 GHz) is also highlighted in this paper. Index Terms Decoupling capacitors, embedded capacitors, measurement, midband frequency, modeling, package, power delivery, simulation, simultaneous switching noise, thick film. I. INTRODUCTION EMBEDDED passives are gradually replacing discrete passives due to the miniaturization of electronic products [1]. Integration of these passives within the package increases the real estate for active components therefore improving the functionality of the system. This paper focuses on a technology that enables the integration of decoupling capacitors within a package. The design of power distribution networks (PDN) is critical for the proper functionality of a system. A major challenge in the design of the PDN is to maintain the impedance of the network below the calculated target impedance over a broad frequency range. The target impedance is given by where is the core voltage of the active device and is the current drawn by the device, as described in [2]. The noise voltage that can be tolerated is assumed to be 5% of the core voltage. Also 50% of the switching current is assumed to Manuscript received April 21, 2006; revised February 18, This work was supported by The DuPont Company. P. Muthana, A. E. Engin, M. Swaminathan, R. Tummala, V. Sundaram, and B. Wiedenman are with the Georgia Institute of Technology, Atlanta, GA USA. D. Amey, K. H. Dietz, and S. Banerji are with the Dupont Electronic Technologies, Semiconductor Packaging and Circuit Materials, Research Triangle Park, NC USA. Digital Object Identifier /TADVP (1) flow in the rise and fall time of the clock edge, respectively, to give a 100% switching current over the whole clock period [2]. The target impedance must be met at all frequencies where current transients exist. The operations that may cause these current transients involve data transfer to and from the hard disk and memory or on-chip processing. This translates into a frequency range that varies from direct current (dc) to multiples of the chip operating frequency. Fast switching speeds of these circuits cause an increase in the current demand. This current is supplied by the PDN and if improperly designed could lead to excessive power supply fluctuations in the PDN. A methodology to insure that the PDN is properly designed is by making sure that the target impedance is met over the entire frequency band. Decoupling capacitors aid in the design of PDNs as highlighted in [3]. Power delivery decoupling in today s systems is primarily achieved by using voltage regulator modules (VRMs) and surface mount discrete capacitors (SMDs). The VRM is a dc dc converter, it senses the voltage near the load and adjusts the output current to regulate the load voltage. VRMs are effective till the lower kilohertz region after which they become highly inductive in their behavior. Surface mount capacitors provide decoupling from the kilohertz region till several hundred megahertz. SMDs start becoming ineffective above this frequency because of the increased effect of loop inductance associated with the charge flow from the capacitors to the switching circuits and back again to the capacitors. A methodology for reducing the loop inductance would be to place the decoupling capacitors as close to the switching circuits as possible. One possible solution is to provide on-chip decoupling above 100 MHz. Previous work has illustrated the effect of on-chip capacitance for decoupling switching circuits [4] [6]. The main disadvantage with this approach is the low capacitance value associated with on-chip capacitance. This renders them effective at frequencies beyond 1 2 GHz. The amount of on-chip capacitance can be increased, but this would compromise the amount of real estate available for including logic circuits. Another approach investigated in [8] [12] is to include planar embedded capacitors within a board or package. In this approach, the capacitor is assumed to be a thin dielectric layer within the package or the board. Another innovative method presented in [13] uses a capacitance interposer between the chip and the board to provide decoupling for the switching circuits /$ IEEE

2 2 IEEE TRANSACTIONS ON ADVANCED PACKAGING The work highlighted in this paper focuses on the use of discrete thick film capacitors on copper foil arranged in a capacitive array that can be used within a package to provide decoupling for high performance circuits in the frequency range from 100 MHz to 2 GHz. Using an array of capacitors allows control of the resonant behavior of each capacitor for broadband decoupling. This paper is organized as follows. Section II describes the processor requirements for future technology nodes in terms of power, core voltage, current, and target impedance. Section III describes the limitations of SMDs in meeting the target impedance for cost performance processors. The performance of embedded capacitors and the proposed solution are highlighted in this section. In Section IV, an introduction to the discrete capacitor technology used in this work will be presented. The modeling, measurement, and characterization of these thick film capacitors will also be described. The integration of the embedded capacitors in a package will be described in Section V. This section describes the modeling and design of the capacitive networks in the package using these capacitors. The time and frequency domain analysis of the PDN with embedded package capacitors is described in Section VI. The performance variation with change in embedded capacitor position in the package is also described. Section VII provides and analysis of the SMD savings attainable by introducing embedded capacitors in the package followed by the conclusion in Section VIII. II. PROCESSOR REQUIREMENTS The power densities of microprocessors has grown over the years due to the increase in the number of transistors and the increase in the processor operating frequency. The major contributors to the power dissipation in the sub-100-nm technology nodes are the active and static power dissipation. The active power dissipation of a processor is given by where is the core voltage of the processor, is the activity of the gates of the processor at each clock cycle, is the capacitance that is switched in each clock cycle, and is the clock frequency of operation of the processor. The static power dissipation of the processor is given by where is the total leakage current of the processor. If the trend in the increase in operating frequency continues, the power dissipation of cost performance processors in the 45-nm node would be close to 450 W [14], [15]. Such high values of power dissipation would not be acceptable for cost performance processor packaging solutions as per the numbers listed in [16]. The power dissipation of a processor can be captured by considering the product of the average current of a processor with the core voltage. The power dissipation of a processor is given by (2) (3) (4) TABLE I VARIATION OF PROCESSOR PARAMETERS THROUGH TECHNOLOGY NODES The power dissipation of a 65-nm node cost performance processor should not exceed W as per [16]. The core voltage is 0.9 V for this technology node. Using (4), the average current drawn by the processor is A. The target impedance for this processor is calculated by substituting the value of and in (1). Table I lists the different parameters for processors in the 90-, 65-, and 45-nm nodes. From Table I, it is evident that the target impedance is decreasing with a decrease in the feature size of future technology nodes. As mentioned before, the methodology for meeting the target impedance is to place decoupling capacitors in the PDN. The number and size of decoupling capacitors required depend on the frequency band to be targeted and the equivalent series resistance of each individual capacitor. The number of capacitors of each type can be decided by the equivalent series resistance (ESR) of each type of capacitor and the target impedance to be met III. DECOUPLING SCHEMES This section will briefly describe the decoupling schemes used in today s PDNs and their limitations. The section highlights the limitations of SMDs and embedded planar capacitors. The proposed solution using discrete embedded capacitors is also presented. A. SMD Decoupling Performance To illustrate the limitations of SMD decoupling methodologies, a system simulation using different decoupling components on the board was performed. The schematic of the setup is shown in Fig. 1. The setup includes a 10 cm 10 cm board with a dielectric thickness of 0.8 mm and copper conductor thickness of 30 m. A4cm 4 cm package and a 11.8 mm 11.8 mm processor mounted on the package were also included in the simulations. The input port in the simulation is the processor looking into the package and the board. SMDs and VRMs are the decoupling components used in today s system. The PDN was designed to meet the target impedance of 0.78 mohms for the 20 processor using the above mentioned components. The SMDs were spread on the board close to the package, with the lower value series inductance capacitors placed closer to the package. This was done to reduce the effect of the spreading inductance of the planes on the capacitor performance. As seen from Fig. 2, at frequencies close to 100 MHz, it becomes increasingly difficult to meet the target impedance. This can be attributed to the increased effect of the loop inductance because of charge flow from the capacitors into the package and the return current from (5)

3 MUTHANA et al.: DESIGN, MODELING, AND CHARACTERIZATION OF EMBEDDED CAPACITOR NETWORKS 3 Fig. 3. Cross section of the PDN model showing the embedded planar capacitor in the package. Fig. 1. Decoupling schemes in today s systems. Fig. 4. Embedded planar capacitor performance with 64 via pairs. Fig. 2. Decoupling limitations of SMDs. the active circuits to the capacitors. In order to provide effective decoupling above 100 MHz, it would be required to reduce the effective inductance associated with the capacitors. This paper highlights the DuPont technology that enables embedding capacitors within the package as described in [17] [19]. Introduction of package capacitors reduces the current path enabling decoupling above 100 MHz. B. Embedded Capacitor Performance The focus of this section is on the performance of embedded capacitors. Embedded capacitors can be broadly classified into two categories. 1) Planar capacitors: The power-ground plane in the package or the board is used as a thin high- capacitive layer. 2) Discrete thick or thin film capacitors: Different sized capacitors are used in a layer of the package for decoupling. The performance of an embedded planar capacitor layer in a package with different number of thru hole via connections is investigated in this subsection. A thruhole via pair based on DuPont s ground rules was modeled using Fast Henry [20] and the inductance extracted by the program for a pair was 280 ph. The details of the geometry of the thru hole via pair will be discussed in detail in Section V. The planar capacitor has dimensions of 4 cm 4 cm and included a DuPont substrate which has a dielectric constant of 11 and thickness 14 m. The top and bottom metal layers have a thickness of 35 m each. The cross section is shown in Fig. 3 Fig. 4 shows the impedance profile with 64 via pairs connected to a single embedded planar capacitor layer. A disadvantage of the planar capacitor performance is the frequency band over which the target impedance is met. For example, in the Fig. 4, it is observed that if a target impedance of 2 mohms is to be met, the frequency band over which this is possible is around MHz. C. Proposed Solution Embedded Discrete Capacitors In order to overcome the above disadvantages, we propose to use the discrete thick film capacitor layers in the package for decoupling, as shown in Fig. 5. These capacitors can be designed with variable sizes, have different capacitances and, therefore, resonate at different frequencies. The proximity of these capacitors to the active device reduces the loop inductance as compared to SMDs and are effective in targeting frequencies above 100 MHz. Another advantage of using discrete thick film capacitors is the high value of capacitance that can be obtained by

4 4 IEEE TRANSACTIONS ON ADVANCED PACKAGING Fig. 7. Embedded discrete capacitor in BT laminate. Fig. 5. Discrete capacitor layer in the package. Fig. 8. Cross section of a discrete capacitor. target the lower frequency band. The higher frequency band was targeted using mm 1.2 mm capacitors and mm capacitors. The two combinations of 1.2 mm 1.2 mm capacitors were placed in different levels of the package. Due to their different placement, the via inductance s associated with each combination were different and they therefore resonate at different frequencies. Fig. 6. Impedance profile with embedded capacitors in the package. using this technology. By proper selection of the sizes of the capacitors, the midfrequency band from 100 MHz to 2 GHz can be achieved for decoupling. As an illustration of the concept, a simulation of the performance of a decoupling array within a package was performed. Fig. 6 shows the performance of an embedded decoupling network that can be designed to provide decoupling in the midband frequency range. It can be seen that impedances of the order of 1 mohm can be targeted above 100 MHz as compared to the profile shown in Fig. 2. Care was taken that all the capacitors were placed directly under or around the processor to minimize the effect of the spreading inductance of the power ground planes. The different sized capacitors that were used to obtain the impedance profile shown in Fig. 6 were placed in two discrete capacitor layers within a package. The details regarding the package stack up are presented in Section V. Twenty-five 1.2 mm 1.2 mm capacitors along with mm 0.5 mm capacitors were used to IV. DISCRETE CAPACITOR TECHNOLOGY A brief introduction to the discrete capacitor technology used in this paper will be presented in this section. These thick film discrete capacitor materials are available from DuPont [21]. They are compatible with the standard FR4/BT laminate printed wiring board technology and can be integrated in BT laminate, as shown in Fig. 7. The cross section of a typical capacitor is shown in Fig. 8. The thickness of the dielectric is in the range of (20 24 m), and the dielectric constant is The loss tangent of the dielectric at 1 MHz is less than The top copper foil and the bottom electrodes are 36 m and 5 m thick, respectively. These capacitors are fabricated on a copper foil with discrete patterned dielectrics and electrodes. The process ground rules define the maximum and minimum size of the capacitors which translate to 0.5 mm and 3 mm a side, respectively. A. Measurement and Characterization Methodology A two-port frequency domain measurement methodology was used to measure the impedance of the capacitive structures [22]. The method will be briefly described in this section. The measurement equipment included Agilent s 8720ES vector network analyzer (VNA) with a bandwidth of 50 MHz 20.5 GHz and 500 m GS-SG Cascade probes. A standard SOLT (short, open, load, and thru) calibration was carried out on the probes using Cascade ISS substrates.

5 MUTHANA et al.: DESIGN, MODELING, AND CHARACTERIZATION OF EMBEDDED CAPACITOR NETWORKS 5 Fig. 9. Measurement setup for characterizing the capacitors. The basic equations used to characterize these structures are given below (6) Fig. 10. Impedence profile of different sized discrete capacitors. where and are the real and imaginary parts of the impedance of the device under test. The measurement set up for characterizing the capacitive structure is shown in Fig. 9. Probe 1 is the source and probe two measures the voltage drop across the device in one measurement cycle. The functions of the ports are reversed in the next measurement cycle of the VNA. is the insertion loss measured across the device at each frequency point. By calculating the real and imaginary parts of the device, the impedance profile over the measured frequency band can be obtained. (7) B. Modeling of the Capacitive Structures The capacitors were modelled using the transmission matrix method (TMM) [23]. This tool has been previously used to model power plane structures [24], [25]. In the transmission matrix method, the power plane is divided into unit cells. Each unit cell consists of an equivalent circuit with, and components and are cascaded together in a or network. Further details regarding the setup of the transmission matrix can be found in [23]. In modeling the capacitive structures, the fringing effects have been ignored because of the large ratio of the area of the electrodes compared to the thickness of the structures. Fig. 10 shows the impedance profile of different capacitors that were measured using the two-port methodology. Experimental capacitors of size 10 mm 10 mm and 5 mm 5 mm were fabricated and measured, as shown in Fig. 10. Fig. 11 shows the extracted dielectric constant value, it remains relatively constant as observed from the figure. Figs. 12 and 13 show the model to hardware correlation of a 2 mm 2 mm and 3 mm 3 mm capacitor that were measured and modeled. Ports were appropriately defined in the model to obtain the correct model to hardware correlation. The definition of the ports corresponded to the exact coordinates of the probes on the measurement structure. The parasitic inductance of the probe setup had to be included Fig. 11. Variation of the thick film dielectric constant with frequency. in the model to obtain a good correlation between the model and measurement. The details of the parasitic inductance extraction and model to hardware correlation are given in [26]. The capacitance, inductance, and resistance of the various sized capacitors were extracted from the measured results and are listed in Table II. C. Effect of Vias on Capacitor Performance Fig. 4 in Section III-B shows the performance of the planar embedded capacitors with 64 via pairs connected to it. The placement of vias has an effect on the performance of the capacitors. Fig. 14 shows the placement of eight vias but in different locations on the capacitor. The difference in response can be clearly seen from Fig. 15. The solid line is the simulation result with the vias connected in the hollow positions in Fig. 14 and the dashed result is with the vias connected in the solid positions in Fig. 14. In the simulations, the inductance value of a via pair was 280 ph. The difference in the ESR and the resonant frequency can be clearly seen from the impedance

6 6 IEEE TRANSACTIONS ON ADVANCED PACKAGING Fig. 12. Model to hardware correlation of a 2 mm 2 2 mm thick film capacitor. Fig. 14. Two combinations of four via pair connection stoa4cm 2 4cm planar capacitor. Fig. 13. Model to hardware correlation of a 3 mm 2 3 mm thick film capacitor. TABLE II EXTRACTED CAPACITOR PARAMETERS FROM MEASUREMENTS Fig. 15. Simulation results of the two combinations of four via pair connection stoa4cm2 4 cm planar capacitor. profile. Therefore, via locations could play an important role in the design of embedded capacitors. V. CAPACITOR INTEGRATION IN PACKAGE This section highlights the technology for the integration of these capacitors in a package. The cross section of the proposed package is shown in Fig. 16. The package consists of a core of thickness 0.6 mm shown in Fig. 17. The core is split into seven constituents, as shown in Fig. 16. The total thickness of the structure excluding the metal levels in this case is 600 m. The buildup layers are added to the core in Fig. 17 to obtain the complete package stack up in Fig. 16. The thickness of each Fig. 16. Cross section of the proposed package with discrete capacitors. build up layer is 38 m. The total thickness of the stackup including the top and bottom metal thickness of 35 m each is

7 MUTHANA et al.: DESIGN, MODELING, AND CHARACTERIZATION OF EMBEDDED CAPACITOR NETWORKS 7 Fig. 19. Layout of a discrete capacitor layer in the package. Fig. 17. Cross section of the core stack up with planar and discrete capacitors. Fig. 18. Sensitivity of capacitor performance with position. 822 m. The processor and the PWB solder bumps thickness was neglected in calculating the thickness of the package. There are 14 metal layers in the package and the power and ground rails at the top and bottom of the package are connected to each other using thru and blind vias. The thru vias run through the core and are 0.6 mm in length. The diameter of the thru vias is 200 m and their edge to edge separation is 200 m. A thru hole via pair was modeled in Fast Henry to extract the inductance, the value extracted was 280 ph for a single pair. The length of the blind vias is dependent on the placement of the discrete capacitor in the package. The blind vias have a diameter of 100 m and are spaced 300 m apart and the length of the blind vias can vary from 36 mto171 m. The associated inductance of the blind vias correspondingly varies from 6 to 70.6 ph, respectively. A. Design of Capacitive Network To meet the target impedance between 100 MHz and 2 GHz, a package capacitive network was designed with the discrete thick film capacitor material from DuPont. For simplifying the simulations, planar capacitors were not included in the decoupling network. The capacitor performance is sensitive to position, as shown in Fig. 18. The solid line is the performance of the capacitor at the probe location, while the dashed line is the capacitor performance placed 10 mm away from the probe point. The degradation of the frequency response of the capacitors with location is clearly evident. Therefore, an important requirement of these capacitors is to be able to place them as close to the switching circuits as possible. The capacitive network was designed with all the discrete capacitors placed directly under or around the die shadow in the two layers allocated to them in the package. The size of the die was taken as 11.8 mm 11.8 mm from [16] for a cost performance processor for the 65-nm node. The placement of the capacitors under the die shadow was done to reduce the effect of the spreading inductance of plane pairs of the package as previously highlighted in Fig. 18. The network consists of 18 caps of 1 mm and 18 caps of 0.75 mm in each discrete capacitor layer giving a total of 72 capacitors in the capacitive array. The discrete capacitors in the lower layer of the package were connected to the power and ground bumps of the processor via blind and thru vias as mentioned earlier in this section. The layout of one of the discrete layers is shown in Fig. 19. The network is designed such that majority of the vias from the capacitors connect directly to the flip chip solder bumps of the processor. The design ground rules prevent thru vias to be spread uniformly across the die shadow as seen by the nonuniformity of the position of the thru vias in Fig. 19. Process ground rules specific to DuPont capacitor materials were used to design the embedded capacitor layout. A few of the rules that were used will be briefly mentioned in this part of the section. Fig. 20 captures a few of the design ground rules for the capacitor network layout. The minimum and maximum size of the electrodes as mentioned before are 0.5 mm and 3 mm a side, respectively. The size of a dielectric is mm larger than the size of the electrode on each side, therefore, the area occupied by the structure is larger than that occupied by the effective capacitor. If there are no thru holes between a capacitor, the distance between dielectrics is mm. The spacing between the dielectrics with thru holes between them is 1.05 mm. The embedded capacitor network was designed to target the frequency band between 100 MHz and 2 GHz, as shown in Fig. 21. To provide decoupling over the whole band, VRMs, SMDs, and on-chip capacitance would also be required. SMDs and on-chip capacitance were used below 100 MHz and above 2 GHz, respectively, to get

8 8 IEEE TRANSACTIONS ON ADVANCED PACKAGING Fig. 20. Design ground rules for the capacitor network in the package. Fig. 22. Impedance profile with the VRM, SMDs, package, and chip capacitors. Fig. 21. Impedance profile with package capacitors. the complete frequency response shown in Fig. 22. The figure shows the frequency band over which each decoupling component is effective. VRMs are effective to the lower kilohertz region, SMDs provide decoupling from the kilohertz region till around 100 MHz, and on-chip capacitance is used above 2 GHz. It is evident that a target impedance in the order of 1 mohm can be met over a broad frequency range from dc to multiples of the chip operating frequencies using the combination of different decoupling components. VI. PERFORMANCE INVESTIGATION WITH A LOW-POWER CHIP The previous section shows the impedance profile obtained by using a combination of board, package and on-chip decoupling components designed to meet the 20 cost performance processor target impedance value as given in [16]. Decoupling a high power chip with a target impedance of 0.78 mohms using the present technology is limited to a very narrow frequency band at 600 MHz and 1 GHz. Therefore, this section looks at alternatives where the capacitive network is used to decouple a lower power chip over a broader frequency range. Fig. 23. Input current pulse train to simulate a 2-GHz clock. A. Time Domain Performance of the Capacitive Network The time domain performance of the capacitive network targeting a lower power chip is investigated in this section. The simulations were carried out to capture the performance with a 2-GHz clock as the input to the system. The rise time and fall time of the current pulse is 50 ps, respectively, and the time period of the clock is 500 ps, as shown in Fig. 23. The target impedance to be met decides the magnitude of the current pulse. In this simulation, a 40-W chip was considered and a core voltage of 1 V was assumed. Therefore, from (4), the magnitude of the current pulse calculated assuming a core voltage of 1 V is 40 A. The target impedance from 1 is 2.5 mohms. To get the time domain response of the system, the Fourier transform of the input current pulse train is multiplied with the frequency domain data of the PDN. The inverse Fourier transform of the resultant is then taken to get the time domain response. The system simulation was initially carried out with a VRM, SMDs and on-chip decoupling capacitors. 25 nf of on-chip decoupling capacitance was considered in the simulation. The time domain performance

9 MUTHANA et al.: DESIGN, MODELING, AND CHARACTERIZATION OF EMBEDDED CAPACITOR NETWORKS 9 Fig. 26. Different vertical locations of the embedded capacitor in the package. Fig. 24. Switching noise with VRM, SMDs, and on-chip capacitors. Fig. 25. Switching noise with VRM, SMDs, on chip and embedded package capacitors. of the system is shown in Fig. 24. Switching noise of the order of 400 mv peak-to-peak is observed from the figure. To highlight the improvement with embedded package capacitors, the system was simulated with the VRM, SMDs, package, and on-chip capacitors. The switching noise observed in this case is 80 mv peak-to-peak and is shown in Fig. 25. A five times improvement in the switching noise performance is clearly seen with the inclusion of embedded capacitors in the package for a 40-W chip. From the frequency domain response of the capacitive network, it can be concluded that a 40 W chip can be decoupled in the frequency range from 350 MHz to 2 GHz. Therefore, with the conservative design ground rules used for these examples this technology is more viable for decoupling low power chips. Known material, design, and process improvements will extend the capability to effectively decouple higher power devices. B. Frequency Performance Dependence on Location A series of simulations were carried out to highlight the performance variation of embedded capacitors with change in position within the package. The simulations were carried out to highlight two important position variations. An array of 42 mm 2 mm capacitors was used to highlight the concept instead of the whole decoupling array. The parameters of a single 2 mm 2 mm capacitor is as follows nf, m, and ph. The inductance of the vias was added to the ESL of the capacitors in the simulations. In configuration, as shown in Fig. 26, the capacitor location was changed vertically in the package. In configuration, the capacitor location was changed horizontally with respect to the processor, as shown in Fig. 28. Configuration : The simulations in this case were carried out with the location of the embedded capacitors varying in the vertical distance in the package. There were five test cases that were investigated in these simulations. 1) The discrete capacitor layer is put in the top ABF buildup layer. The length of the blind via is 38 m and the inductance is 6 ph. 2) The discrete embedded capacitors are placed at the top of the core BT laminate. The length of the via pair is 76 m and the inductance of the via pair is ph. 3) The discrete embedded capacitor s are placed 100 m inside the core BT laminate. The length of the via pair is 171 m and the inductance of the pair is 70.6 ph. 4) The discrete capacitor is placed in the middle of the core. The via length comprises half the length of the thru holes and the discrete via pairs. The total length of the vias is 376 m and the total inductance associated with the via pair is ph. 5) The discrete capacitor layer is placed at the bottom of the core laminate, below the bottom most ABF layer. The total length of the thru hole and discrete via pair is 752 m and the associated inductance of the via pair is ph. The via length and inductance values have been summarized for the different cases in Table III. The change in array performance is evident from Fig. 27. The shift in the resonant frequency to the lower frequency band can be attributed to the increase in the via inductance in each corresponding case. The minimum series resistance of the network remains almost constant because of the negligible resistance of the vias. These results can be translated into the design of a capacitive network such that the capacitors that are required

10 10 IEEE TRANSACTIONS ON ADVANCED PACKAGING TABLE III VIA LENGTH AND INDUCTANCE VALUES FOR DIFFERENT CASES Fig. 28. Horizontal variation of the embedded capacitor in the package. Fig. 27. Variation of capacitor array performance with vertical distance. to target the lower frequency band are placed vertically farther away from the active circuit than the capacitors that decouple higher frequency ranges. The number of via connections to the capacitor also effects its performance, as shown in Figs. 4 and 15, respectively. Configuration : This case analyzes the variation of the four 2mm 2 mm capacitor array performance with a change in the horizontal placement as shown in Fig. 28. It had been mentioned previously that all the embedded capacitors were placed close to or slightly around the processor. Fig. 29 shows the performance change with the horizontal variation of the capacitor array position. The vertical distance of the capacitors is kept constant in all the simulation scenarios for this case. The inductance of the via pair was taken as ph, the same as in case (2) of the previous configuration. Two via pairs were considered for each capacitor in the array. Five test cases were investigated as follows: 1) the capacitor array was placed directly under the processor; 2) the array was placed 2 mm away from the processor; 3) the array was placed 4 mm away from the processor; 4) the array was placed 1.2 cm away; 5) the placement of the array was 1.9 cm away from the processor. The reduction in the resonant frequency of the capacitor array is because of the increased effect of the spreading inductance of the planes as they are placed further away from the processor. An increase in the distance of the capacitor array from the processor also leads to the increased effect of the resistance of the planes. The effect can be seen in the variation of the minimum Fig. 29. Variation of capacitor array performance with horizontal distance. series resistance of the array, which increases from 1 to 5. Therefore, from the above analysis it is evident that stacking the capacitors vertically directly under the processor would be advantageous if the PDN is required to decouple active high current density circuits with very low target impedances. VII. SMD SAVING USING EMBEDDED CAPACITORS SMD savings with the introduction of embedded capacitors are highlighted in this section. It has been shown in Section III that SMDs reach their decoupling limitation close to 100 MHz, therefore, this frequency point has been chosen for carrying out the following analysis. The steps involved in determining the number of SMDs that can be saved are determined as follows. Step 1) Use only SMDs in the PDN to meet a target impedance up to 100 MHz. Step 2) Design the PDN by using embedded capacitors to meet the same target impedance and then introduce SMDs to meet the target impedance at 100 MHz.

11 MUTHANA et al.: DESIGN, MODELING, AND CHARACTERIZATION OF EMBEDDED CAPACITOR NETWORKS 11 Fig. 30. Impedance profile of a 5 mm 2 5 mm capacitor used in the analysis. Fig. 31. Profile comparison of simulations with and without embedded capacitors. Observe if there are any savings in the SMDs in step 2 as compared to step 1. In the simulations, it is assumed that the SMDs are connected directly to the PWB solder balls. The dimensions and the pitch of the solder ball are assumed to be 500 m each. A pair of the solder balls were modeled in Fast Henry and the associated inductance of a single pair was calculated to be ph. The SMDs under consideration are the low inductance capacitors that are available from AVX [27]. The lead inductance of the AVX LICA capacitors is 25 ph and that of a single thru hole via pair is 280 ph. One hundred via pairs are assumed within the package, therefore, the effective inductance of the thru vias is 2.8 ph. A single blind via pair is assumed to complete the loop from the bottom and the top of the package. The inductance of a single blind via pair is ph, as in case 2 in Section VI-B, giving a total of ph for the blind via inductance from the top and bottom of the package. The complete loop inductance of a SMD is ph. The ESR of the LICA capacitors is 100 m, as given in [27]. SMD capacitors that resonate at 50 and 100 MHz were chosen to carry out the analysis. The capacitance required to resonate at 50 and 100 MHz with the calculated inductance is and 37 nf, respectively. An experimental embedded capacitor of size 5 mm 5mm was chosen for the analysis as it resonates close to 100 MHz, as seen in Fig. 30. The parameters of the capacitor are as followsnf, ph, and m. The target impedance chosen for the analysis is 2 m. Fig. 31 shows the analysis comparison between the two simulations. The solid line is the simulation result with SMD capacitors, 50 capacitors that resonate at 50 MHz and 50 capacitors that resonate at 100 MHz were used in the analysis. The dashed line is the frequency response of the simulation with 64 SMDs that resonate at 50 MHz and ten 5 mm 5 mm embedded capacitors. The embedded capacitors were placed at the two discrete capacitor layers in the package as previously mentioned in the paper. A savings of 36 SMDs is obtained when using embedded capacitors as compared to the previous case where only SMDs were used. The amount of capacitance available in both cases is almost the same uf of capacitance is available in the case with embedded capacitors as compared to uf of capacitance without embedded capacitors. VIII. CONCLUSION The use of embedded discrete thick film capacitors within the package is a feasible solution for decoupling processors above 100 MHz. They overcome the limitations of SMDs, primarily in decoupling active circuits in the midfrequency band. The modeling, measurement, and characterization of embedded decoupling capacitors in the design of PDN s has been investigated in this paper. It was shown that the performance of these capacitors are highly dependent on their position in the package. Different vertical and horizontal position combinations were simulated and analyzed. The design of decoupling networks in the package by placing these capacitors under the die shadow has been introduced. In the network highlighted in this paper, 72 embedded package capacitors were used to decouple a 40-W chip and show a five times improvement in the switching noise performance. It was also observed that considerable savings of SMDs could be achieved by using embedded capacitors in the PDN. ACKNOWLEDGMENT The authors would like to thank DuPont for initiating this effort and W. Yun for his contribution to the measurements of the capacitors. REFERENCES [1] R. Tummala, Fundamentals of Microsystems Packaging, 1st ed. New York: McGraw Hill, [2] S. J. Chun, Methodologies for modeling simultaneous switching noise in multi-layered packages and boards, Ph.D. dissertation, Georgia Inst. Technol., Atlanta, Apr

12 12 IEEE TRANSACTIONS ON ADVANCED PACKAGING [3] L. Smith, R. Anderson, D. Forehand, T. Pelc, and T. Roy, Power distribution system design methodology and capacitor selection for modern CMOS technology, IEEE Trans. Adv. Packag., vol. 22, no. 3, pp , Aug [4] B. Garben, G. A. Katopis, and W. D. Becker, Package and chip design optimization for mid-frequency power distribution decoupling, Electrical Performance Electronic Packag., pp , [5] O. P. Mandhana and J. Zhao, Comparitive study on the effectiveness of on-chip, on package and PCB decoupling for core noise reduction by using broadband power delivery network models, in Electronic Compon. Technol. Conf., 2005, pp [6] N. Na, T. Budell, C. Chiu, E. Tremble, and I. Wemple, The Effects of On-Chip and Package Decoupling Capacitors and an Efficient ASIC Decoupling Methodology, in Electronic Compon. Technol. Conf., 2004, pp [7] T. Rahal-Arabi, G. Taylor, M. Ma, J. Jones, and C. Webb, Design and Validation of the Core and I/O s decoupling of the Pentium3 and Pentium4 Processors, Electrical Performance Electronic Packag., pp , [8] R. Ulrich, Embedded resistors and capacitors for organic-based SOP, IEEE Trans. Adv. Packag., vol. 27, no. 2, pp , May [9] I. Novak, Lossy power distribution networks with thin dielectric layers and/or thin conductive layers, IEEE Trans. Adv. Packag., vol. 23, no. 3, pp , Aug [10] H. Kim, B. K. Sun, and J. Kim, Suppresion of GHz range power/ ground inductive and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs, IEEE Microw. Wireless Compon. Lett., vol. 14, no. 2, pp , Feb [11] K. Y. Chen, W. D. Brown, L. W. Schaper, S. S. Ang, and H. A. Naseem, A study of high frequency performance of thin film capacitors for electronic packaging, IEEE Trans. Adv. Packag., vol. 23, no. 2, pp , May [12] J. S. Peiffer and W. Balliette, Decoupling of high speed digital electronics with embedded capacitance, presented at the 38th Int. Symp. Microelectron., Philadelphia, PA, Sep [13] J. G. Nickel, Decoupling capacitance platform for substrates, sockets and interposers, presented at the DesignCon, Santa Clara, CA, Feb [14] P. Muthana, M. Swaminathan, R. Tummala, V. Sundaram, L. Wan, S. K. Bhattacharya, and P. M. Raj, Packaging of multi-core processors: Tradeoffs and potential solutions, in Electron. Compon. Technol. Conf., 2005, pp [15] H. P. Hofstee, Future microprocessors and off-chip SOP interconnect, IEEE Trans. Adv. Packag., vol. 27, no. 2, pp , May [16] International Roadmap for Semiconductors (ITRS) 2004 Update, [Online]. Available: [17] J. Felten, R. Snogren, and J. Zhou, Embedded ceramic resistors and capacitors in PWB: Process and performance, in Fall IPC Meeting, Orlando, FL, Oct. 11, [18] W. Borland and J. Felten, Thick film capacitors and resistors inside printed circuit boards, presented at the 34th Int. Symp. Microelectron., Baltimore, MD, Oct. 9-11, [19] W. Borland, Designing for embedded passives, Printed Circuit Board Design, Aug [20] M. Kamon, M. J. Ttsuk, and J. K. White, FASTHENRY: A mutipole-accelerated 3D-inductance extraction program, IEEE Trans. Microwave Theory Tech., vol. 42, no. 9, pp , Sep [21] Interra embedded passive materials. DuPont [Online]. Available: [22] I. Novak and J. R. Miller, Frequency dependent characterization of bulk and ceramic bypass capacitors, in Poster Material 12th Topical Meeting Electrical Performance Electronic Packag., Oct. 2003, pp [23] J. H. Kim and M. Swaminathan, Modeling of irregular shaped power distribution planes using transmission matrix method, IEEE Trans. Adv. Packag., vol. 24, no. 3, pp , Aug [24] J. Choi, S.-H. Min, J.-H. Kim, M. Swaminathan, W. Beyene, and X. Yuan, Modeling and analysis of power distribution networks for gigabit applications, IEEE Trans. Mobile Comput., vol. 2, no. 4, pp , Dec [25] W. Beyene, C. Yuan, J. H. Kim, and M. Swaminathan, Modeling and analysis of power distribution networks for gigabit applications, in Proc. 4th Int. Symp. Quality Electronic Design (ISQED), 2003, pp [26] P. Muthana, M. Swaminathan, R. Tummala, P. M. Raj, E. Engin, L. Wan, D. Balaraman, and S. Bhattacharya, Design, modeling and characterization of embedded capacitors for mid-frequency decoupling in semiconductor systems, Electromagn. Compatibil., pp , [27] AVX. AVX Corp., Myrtle Beach, SC [Online]. Available: avx.com/ Prathap Muthana (S 03) received the B.E. degree from Rashtriya Vidyalaya College of Engineering (RVCE), Bangalore, India, in 1999, and the M.S. degree from the State University of New York (SUNY), Binghamton, in 2002, respectively. He is currently working toward the Ph.D. degree in the Electrical and Computer Engineering Department, the Georgia Institute of Technology, Atlanta. His main research area is in the design of high speed microsystems using embedded decoupling components. Arif Ege Engin (M 05) received the B.S. degree in electrical engineering from Middle East Technical University, Ankara, Turkey, in 1998, and the M.S. degree in electrical engineering from the University of Paderborn, Paderborn, Germany, in 2001, and the Ph.D. degree (summa cum laude) from the University of Hannover, Hannover, Germany, in From 2001 to 2004, he was with the Fraunhofer- Institute for Reliability and Microintegration, Berlin, Germany. He has been with the Packaging Research Center at Georgia Institute of Technology, Atlanta, since His research interests include mixed-signal design, characterization, and test. He has more than 40 publications in peer-reviewed journals and conferences in the areas of signal and power integrity modeling and simulation. Dr. Engin is serving as a Reviewer for the IEEE TRANSACTIONS ON ADVANCED PACKAGING. Madhavan Swaminathan (SM 99 F 06) received the M.S. and Ph.D. degrees in electrical engineering from Syracuse University, Syracuse, NY, in 1989 and 1991, respectively. He is currently the Joseph M. Petit Professor in Electronics in the School of Electrical and Computer Engineering, Georgia Tech and the Deputy Director of the Microsystems Packaging Research Center, Georgia Institute of Technology, Atlanta. He is the cofounder of Jacket Micro Devices, a company specializing in integrated devices and modules for wireless applications where he serves as the Chief Scientist. Prior to joining Georgia Institute of Technology, he was with the Advanced Packaging Laboratory at IBM working on packaging for super computers. He has over 250 publications in refereed journals and conferences, has co-authored 3 book chapters, has 12 issued patents and has 10 patents pending. While at IBM, he reached the second invention plateau. His research interests are in mixed signal system integration. Dr. Swaminathan served as the Co-Chair for the 1998 and 1999 IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), served as the Technical and General Chair for the IMAPS Next Generation IC & Package Design Workshop, serves as the Chair of TC-12, the Technical Committee on Electrical Design, Modeling and Simulation within the IEEE CPMT society and was the Co-Chair for the 2001 IEEE Future Directions in IC and Package Design Workshop. He is the cofounder of the IMAPS Next Generation IC & Package Design Workshop and the IEEE Future Directions in IC and Package Design Workshop. He also serves on the technical program committees of EPEP, Signal Propagation on Interconnects workshop, Solid State Devices

13 MUTHANA et al.: DESIGN, MODELING, AND CHARACTERIZATION OF EMBEDDED CAPACITOR NETWORKS 13 and Materials Conference (SSDM), Electronic Components and Technology Conference (ECTC), and International Symposium on Quality Electronic Design (ISQED). He has been a guest editor for the IEEE TRANSACTIONS ON ADVANCED PACKAGING and IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He was the Associate Editor of the IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES. He is the recipient of the 2002 Outstanding Graduate Research Advisor Award from the School of Electrical and Computer Engineering, Georgia Tech and the 2003 Outstanding Faculty Leadership Award for the mentoring of graduate research assistants from Georgia Tech. He is also the recipient of the 2003 Presidential Special Recognition Award from IEEE CPMT Society for his leadership of TC-12 and the IBM Faculty Award in 2004 and He has also served as the co-author and advisor for a number of outstanding student paper awards at EPEP 00, EPEP 02, EPEP 03, EPEP 04, APMC 05, ECTC 98 and the 1997 IMAPS Education Award. He is the recipient of the Shri. Mukhopadyay best paper award at the International Conference on Electromagnetic Interference and Compatibility (INCEMIC), Chennai, India, 2003, the 2004 best paper award in the IEEE TRANSACTIONS ON ADVANCED PACKAGING, the 2004 commendable paper award in the IEEE TRANSACTIONS ON ADVANCED PACKAGING and the best poster paper award at ECTC 04 and ECTC 06. Boyd Wiedenman received the B.S. degree in chemistry from Colorado State University, Fort Collins, in He has over ten years of industry experience with semiconductor fabrication process integration and M.E.M.S. process development, most recently from Sandia National Laboratories, Livermore, CA. He is currently a Research Engineer with the PRC at Georgia Institute of Technology, Atlanta, working with digital wiring and dielectrics, embedded passives, and process integration for next generation system-on-packages (SOP) platforms. Rao Tummala (F 94) is a Distinguished and Endowed Chair Professor, and Director of NSF ERC at the Georgia Institute of Technology, Atlanta, pioneering system-on-package (SOP) vision. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the first flat panel display based on gas discharge, the first and next three generations of multichip packaging based on 35-layer alumina and 61-layer LTCC with copper and copper-polymer thin film, and materials for ink-jet printing and magnetic storage. He published 375 technical papers, holds 71 patents and inventions; authored the first modern packaging reference book-microelectronics Packaging Handbook (Van Nostrand, 1988) and the first textbook-fundamentals of Microsystems Packaging (McGraw Hill, 2001). Prof. Tummala received many industry, academic, and professional society awards including Industry Week s award for improving U.S. competitiveness, IEEE s David Sarnoff and Major Education awards, Dan Hughes award from IMAPS, Engineering Materials Achievement award from DVM and ASM-International, Total Excellence in Manufacturing award from SME, John Jeppson s award from the American Ceramic Society, as well as the Distinguished Alumni Awards from the University of Illinois, the Indian Institute of Science, and Georgia Tech. He is a Fellow of IMAPS and the American Ceramic Society, and a member of the National Academy of Engineering. He was the President of the IEEE-CPMT and the IMAPS Societies. Venkatesh Sundaram received the B.S. degree in metallurgical engineering from Indian Institute of Technology, Bombay, India, and the M.S. in ceramic and materials engineering from the Georgia Institute of Technology, Atlanta, where he is currently working towards the Ph.D. degree in materials science and engineering. He is Assistant Research Director and a research staff member at Georgia Institute of Technology, Atlanta, Packaging Research Center (PRC) and is currently coleading the SOP package substrate development program at the PRC. He has over seven years experience in high-density microvia board and thin film technology. He has more than 30 publications, four patents pending, and a number of invention disclosures in SOP substrate technology and RF/Digital packaging. He has presented industry short courses on Embedded Passives and High Density PWB Technologies. He is PRC Program Manager for the SOP technology transfer partnership with Endicott Interconnect, NY, and the high-density substrate task leader for the multimillion dollar Nano-Wafer Level Packaging Program. Mr. Sundaram is a member of the High Density Substrate Technical Committee (TC-6) of IEEE-CPMT Society. Daniel Amey (SM 80) received the B.S.E.E. and M.S. of engineering in engineering science from the Pennsylvania State University and the MBA degree from Lehigh University. He is a Research Fellow with E. I. Du Pont de Nemours & Company, Electronics & Communications Technology in Research Triangle Park, NC, where he is performing electronic packaging technology development, high-frequency materials characterization and applications engineering. Prior to joining Du Pont in 1988, he was Director of Engineering for Elco Corporation, Huntingdon, PA, with responsibilities for the design and development of connector and packaging hardware. From 1981 to 1986, he was Director of Electronics Technology for Thomas & Betts, Raritan, NJ, where he was responsible for research and development of packaging and interconnection products. From 1967 to 1981, he was with Sperry Univac, Blue Bell, PA. As Engineering Manager of Packaging Techniques, from 1972 to 1981, he was responsible for interconnection hardware development for small and medium computer systems which included the design and development of LSI packages, hybrid circuits, special connectors, printed wiring board processes and techniques, and interconnection hardware applications. From 1963 to 1967, he worked on military electronic hardware design at the Electronics Division of General Dynamics, which included the design of analog and digital support equipment for aerospace applications. He is the author or coauthor of over 50 technical papers and articles published in conference proceedings (ISHM/IMAPS, ECSG, IEMT, IPC), IEEE TRANSACTIONS, Electronics, EDN, Advanced Packaging, Electronic Packaging and Production, Solid State Technology, Microwaves & RF, and Microwave Journal. He is the author of the Surface Mounted Components chapter in the ISHM (now IMAPS) Book SURFACE MOUNT TECHNOLOGY and author of the chapters on Electronic Packaging and IC Packaging Processes and Semiconductor Package Types and Package Selection in the McGraw Hill VLSI HANDBOOK published in He authored the Integrated Circuit Packaging chapter in the Wiley-VCH HANDBOOK OF SEMICONDUCTOR TECHNOLOGY-VOLUME 2 published in He has developed and taught courses in Electronic Packaging and Printed Wiring Technology for McGraw Hill and the center for Professional Advancement. He holds eight patents and has three patents pending in the fields of electronic packaging and display technologies. Mr. Amey served as Chairman of a JEDEC task group to standardize chip carriers and packages for LSI devices from 1976 to He is the recipient of awards from the IEPS For outstanding contributions to the field of electronics packaging, a Special Award from the IEEE Computer Society For the initiation of packaging standards and leadership in gaining industry-wide approval of JEDEC chip carriers, and the Distinguished Engineering Contribution Award from the EIA in In 2004, he received the IMAPS John A. Wagnon Technical Achievement Award for his significant and continuing technical contributions to IMAPS over the course of many years in the area of electronics and communications technology and his accomplishments in the research and development of electronic packaging. He is a founding member of the IEPS and life member of IMAPS and IMAPS Fellow. He received the IEPS Founders Award in He has participated in numerous IMAPS local and regional workshops serving as Chair, Technical Committee member, and presenter. He was instrumental in the recent reestablishment of the IMAPS Carolinas local chapter.

14 14 IEEE TRANSACTIONS ON ADVANCED PACKAGING Karl H. Dietz received the Ph.D. degree in organic chemistry from the University of Frankfurt, Frankfurt, Germany. He is Technology Manager in DuPont Electronic Technologies Semiconductor Packaging and Circuit Materials Group, Research Triangle Park, NC. He has 39 years experience in a variety of research and development, manufacturing, and quality control functions. Sounak Banerji received the B.S. in metallurgical engineering from the Indian Institute of Technology, Roorkee, India, in 2000, and the M.S. degree in materials science from the Microelectronics Packaging Research Center, Georgia Institute of Technology, Atlanta, in His master s thesis was focussed on novel base substrate materials for System on a Package applications. He did an eight-month internship at Assembly Technology Development, Intel, working on board level assembly of BGAs. Since then, he has been part of the Semiconductor Packaging and Circuit Materials Group, DuPont Electronic Technologies, doing applications research on embedded capacitors for digital packages and RF modules, substrate materials for high-speed interconnects and low loss substrates for RF applications.