580 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007

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1 580 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 High-Q Embedded Passives on Large Panel Multilayer Liquid Crystalline Polymer-Based Substrate Wansuk Yun, Venky Sundaram, and Madhavan Swaminathan, Fellow, IEEE Abstract This paper presents high-q embedded passives on a multilayer liquid crystalline polymer (M-LCP)-based substrate for a low-profile, compact, mixed-signal system integration with high performance. A low loss and a low water absorption are advantages of LCP. It is also lower-cost material than other high-frequency materials such as low-temperature cofired ceramic (LTCC) due to its compatibility to printed wiring board (PWB) process. Low loss characteristics of LCP provide high-q passives such as inductors, capacitors, and matching networks. Seventy-six inductors and sixteen capacitors were characterized from three different 9in 12 in multilayer LCP panels. Two different locations from each board were chosen to preliminarily validate the large panel process of the M-LCP substrate. The highest quality factor (Q) of 164 was achieved with 2.55 nh at 5.05 GHz. The inductors range from 1.45 to nh and Qs range from 43 to 164. Inductors in various embedded layers were characterized for realization of 3-D integration in multilayer LCP substrate for multiband applications. To remove the parasitics from pads and interconnections, a two-step de-embedding technique was applied. The model-tohardware correlations are presented in this paper. Twelve 3-D capacitors were also designed and characterized, which provide more than double the capacitance of standard capacitors. Low-loss filters and baluns at 5 GHz were simulated and measured using the designed high-q passives. The designed high-q embedded passives on M-LCP-based substrates provide a systematic 3-D integration method for achieving low-profile, high-performance, and compact modules. Index Terms Embedded passives, high-, liquid crystalline polymer (LCP), multilayer, three-dimensional (3-D) integration. I. INTRODUCTION COST reduction, fast time to market, compact size, low profile, and high performance make system on package (SOP) an attractive solution for radio-frequency (RF) front-end modules. As shown in Fig. 1, as the number of components in a multiband system have increased exponentially, higher integration such as Fig. 1. Multiband system architecture SOP is very critical. SOP provides functionality in the package through the integration of the passives such as inductors [1], [2], capacitors, and resistors. Highly-integrated SOPs can provide a multiband system solution with all of the benefits mentioned above. Embedded-passive technology is a key technology for higher integration in SOPs. While cost reduction and fast time to Manuscript received March 20, 2006; revised January 6, The authors are with the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA USA. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TADVP market can be achieved by removing surface-mounted devices (SMDs), high-q passives embedded in the substrate enable high performance with compact size. Recently, the use of low-temperature cofired ceramic (LTCC) technology, or multichip module-d (MCM-D) technology [2] [8], in RF circuit design has become very popular because of its advantages, including low loss, high integration density, and high reliability. LTCC, a multilayer ceramic technology, enables the embedding of passive components into multiple layers while active elements are mounted on the surface layer. Although LTCC can also provide high-q passives, it cannot be used as a final substrate for systems. In addition, because of its coefficient of a thermal expansion (CTE) mismatch with a printed wiring board (PWB), it can lead to reliability issues. In contrast, liquid crystalline polymer (LCP) can provide high-q passives embedded in the packaging substrate [9]. However, unlike LTCC, LCP allows designers to achieve completely integrated wireless systems [10] since the LCP process is compatible with PWB process such as FR-4. Therefore, it can be ultimately become the final PWB. If used as a module, LCP has a similar CTE as compared to PWB. Other organic materials have been used for integration. Sanmina ZBC2000 [11] provides improved electromagnetic interference (EMI), improved reliability, and improved manufacturability with lower cost. While LCP has the loss tangent of 0.002, ZBC 2000 has the loss tangent of 0.015, resulting in higher losses for embedded RF circuits. Dupont HK04 is an all polyimide, unfilled dielectric. Even though it provides excellent voltage resistance, its water absorption of 0.8% is much higher than that of LCP, which is at 0.04%[12], and hence causes large variations in RF performance. Since the circuit decreases as operating frequency increases, the impact of water absorption on RF performance can be significant for most organic materials. Due to low loss, minimal dependency on temperature, and near hermiticity of LCP, LCP has been shown to be an excellent candidate for RF applications [13]. In [14], a single-layer LCP shows excellent material characteristics up to 110 GHz. The single-layer LCP substrate for RF front ends has been characterized and applied to various applications such as low-noise amplifiers (LNAs), filters, baluns, and voltage-controlled oscillators (VCOs) [15]. Even though performances of RF front-end components are directly related to the quality factor (Q) of passives, this does not imply that every passive should have a high Q. In this regard, more efficient integration can be achieved using a variety of Qs in a single circuit. In other words, a few high-q passives can be used for critical components while other /$ IEEE

2 YUN et al.: HIGH-Q EMBEDDED PASSIVES ON LARGE PANEL MULTILAYER LIQUID CRYSTALLINE POLYMER-BASED SUBSTRATE 581 Fig. 1. Multiband system architecture. Fig. 2. Cross section of the three layer LCP substrate. (a) Three layer LCP substrate. (b) Balanced double layer LCP substrate. relatively low-q passives can be used for remaining components, which results in more efficient integration. 3-D integration provides more flexibility in achieving higher Qs for the critical components than 2-D integration. In 2-D integration, the Qs are fixed due to the lateral area used. As mentioned above, unlike LTCC, LCP technology can not only be used as integrated passive devices (IPD) or modules, but also be used as the final substrate for systems. Due to the increasing demands for higher integration, RF front-end integration as well as RF-digital integration are essential. In Fig. 1, the front-end module, i.e., the components inside the box, can be integrated as modules, which can then be incorporated with the rest of the RF and baseband modules. Therefore, the vertical integration by 3-D design with multilayer substrates can be a good solution for RF-digital integration. The thickness of a system in compact-size portable devices can be a major restriction as the integration trend continues. In addition, the overall integration cost is a key consideration. The 3-D multilayer LCP (M-LCP)-based integration can provide multifunctional, lowprofile, low-cost, and high-performance systems. In [16], 12 inductors showing the scalability of Qs using the M-LCP process at two different locations in one board were characterized. In this paper, more comprehensive characterization with a de-embedding technique has been conducted. 3-D capacitors have been designed and characterized. In addition, 5-GHz filter and baluns were designed. Therefore, the 3-D integration and characterization of high-q passives and design benefits have been demonstrated in this paper. The main contributions of this paper are as follows. 1) A comparison of the fabrication processing of LTCC- and LCP-based technologies. 2) A characterization of 76 high-q inductors and 16 multilayer capacitors using the M-LCP-based process. 3) A demonstration of the scalability of the Qs in 3-D integration. 4) Preliminary validation for two different locations in three large panels to show repeatability. 5) The simulation-to-measurement correlation using a twostep de-embedding technique. 6) The application of 3-D integration with embedded high-q passives in 5-GHz filters and baluns. II. LCP-BASED TECHNOLOGY Both LCP and LTCC can consist of vertically integrated layers that allow for 3-D integration. However, LCP can be integrated inside printed circuit boards (PCBs), while LTCC is not compatible with PCB processes. The LCP-based technology is available in single-layer [9], [10], [13], [15], three-layer, and balanced configurations. A three-layer LCP cross section is shown in Fig. 2(a). Three LCP layers are bonded together by lower-melt adhesives (CORE). This process combines 25- m-thick LCP dielectrics with low-loss tangent glass-reinforced organic prepregs in a multilayer stack-up. Based on this process, four to ten metal layer laminates can be fabricated. The LCP layers have a dielectric constant of 2.9 and a loss tangent of at 10 GHz and 23 C. The adhesive layers have a loss tangent of with a dielectric constant of The top-metal layer (M1) of the cross section can be used for SMDs and for high-q inductors. The thickness of the copper layers (M1 M8) is 17 m. The bottom-metal layer (M6) can be used as a microstrip ground. The ability to form microvias in the stack up represents an improvement in component and routing density. The cross section of the balanced-lcp substrate is shown in Fig. 2(b). Two balanced-lcp layers were circuitized separately, followed by the lamination of LCP layers using organic prepreg layers. Thru-holes were mechanically drilled and plated to form interconnections. A liquid-photoimageable solder mask was

3 582 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 Fig. 3. Typical LTCC process flow. used, and an electroless nickel immersion gold finish was plated on the bond pads and terminals. All processes, including lamination ( C), electroless and electrolytic copper plating, and dry film photoresists, are compatible with standard FR-4 and PWB manufacturing. The panels were fabricated on 12 in 18 in and 9 in 12 in panels using large-area PWB tooling. The large-panel process results in low-cost implementation that can be easily scaled to an 18 in 24 in panel for further cost reduction. Typically, ceramic or LTCC components are manufactured on a panel size of 8 in 8 in. The fabrication of components on 18 in 24 in panels can yield more than five 400 devices of 5 mm 5 mm size, which results in more than a tenfold increase in number of components for a given board over ceramic-based processes. The high-precision RF passive components in the LCP layers are packaged using laminate layers, providing mechanical strength, and enhanced reliability. Unlike conventional PWB materials, the proprietary process technology utilizes organic dielectrics with extremely low moisture uptake comparable to ceramic dielectrics. Typical moisture uptake rates for the packaging materials are less than 0.05%, leading to ceramic-like near-hermetic packaging at organic PCB manufacturing costs. The fully-packaged substrate has CTE matched to the typical organic materials used in a PWB technology such as FR-4 with CTE around ppm/ C. The CTE match allows for large modules to be implemented with very high reliability. The material set can be adjusted to tailor the CTE of the package in the 3 20 ppm/c range, resulting in expansion-matched packages and modules for various RF IC platforms, including Si CMOS, SiGe, and GaAs. IC assemblies, high-frequency electrical and full functional testings, and over-molding operations are performed on the subpanels of 6 in 6 in prior to dicing the individual modules. A novel and proprietary structure allows for the on-board RF shielding of each of the devices prior to singulation, which in turn precludes the need for EMI cans, which increase both cost and size. This novel and patented approach results in higher performance with a much lower cost than ceramic-based technology [17]. Fig. 3 shows a comparison of the process flows of LCP-based technology and LTCC-based technology, and Fig. 4 shows the processing flow of multilayer LCP technology. LTCC uses layers, which requires more processing time and cost. In contrast, because LCP-based technology uses three to six layers, it results in less processing time and cost. This also makes LCP-based technology more attractive for a low-profile mixed-signal system integration. In addition, LCP-based process has an advantage of the lower processing temperature of 177 C 280 C, while LTCC requires C (see Fig. 3).

4 YUN et al.: HIGH-Q EMBEDDED PASSIVES ON LARGE PANEL MULTILAYER LIQUID CRYSTALLINE POLYMER-BASED SUBSTRATE 583 Fig. 4. Multiple LCP layer process flow. Fig. 5. Photograph of TV1. III. HIGH-Q EMBEDDED INDUCTOR CHARACTERIZATION IN TEST VEHICLE 1 Fig. 5 shows the photograph of test vehicle 1 (TV1) in the balanced configuration shown in Fig. 2(b). TV 1 was fabricated on a 12 in 9 in LCP panel. It has two different test sets: one in the center and the other at the edge. Twelve different rectangular spiral inductors were characterized in two different locations in TV 1. Fig. 6 shows the inductor layout with a GSG pad. The metal width ( ) and line space ( ) were set at 3 mil. The inductors were designed for 3-D integration and high-q using different layers. To show the scalability of Qs, eight same-size inductors were designed in two different layers: one in the topmost layer (M1), and the other in the top LCP layer (M3) [which is embedded in the LCP substrate in Fig. 2(b)]. Inductors were designed using an electromagnetic (EM) simulator, SONNET [18], and verified using measurement Fig. 6. Layout of rectangular spiral inductor. results. The measurements were taken using a GSG 500 um Air Coplanar probe (ACP) with a vector network analyzer. The effective inductance and the Q of the inductors were calculated from the measured S parameters. First, the of the inductor was extracted from the measured S, and then the effective inductance (L ) and Q were calculated as equation (1) and (2) using SONNET (1)

5 584 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 Fig. 7. Measured inductance and Q of set 1. (a) Inductance profile of TV1. (b) Sampled inductance of TV1. (c) Q of TV1. Fig. 7(a) shows inductance profiles, which also show the selfresonant frequencies (SRFs) of the inductors. Fig. 7(b) shows inductances from Set 2: A (2.7 nh at 1 GHz), B (2.9 nh), C (4.3 nh), D (4.7 nh), E (9.3 nh), and F (17.8 nh). All inductors have 3 mil line width of rectangular spirals with varying length. Inductors A (M1) and B (M3) and inductors C (M1) and D (M3) are the same size, but they are in different layers. Inductors E and F are in the topmost layer (M1). Fig. 7(c) shows the averaged measured Q factors up to 10 GHz. The Q of the Inductor A is 126 at 3.68 GHz, while the Q of the inductor B is 75 at 2.52 GHz. Compared to inductor Qs of FR-4 and LTCC (100 with 1.2 nh at 1.9 GHz ([19]), the inductor Qs of LCP show excellent performance. The results also show the scalability of inductor Qs using 3-D integration. While the Q of Inductor B (75) is also high enough for general applications, this higher-q (126) of Inductor A can be used for few critical components in various applications. High-Q passives in the critical components reduce the phase noise of VCOs [15], the noise of LNAs, and the insertion loss of band-pass filters [20]. For example, only one inductor in the VCO was critical to achieve low-phase noise in [15]. Therefore, in an RF front module, only few critical components requiring high Q can be optimized in 3-D integration, and other components can be integrated elsewhere with lower Q. The optimization of 3-D integration in multilayer LCP substrates provides high performance with a compact size and a low profile. (2) The self-resonant frequency (SRF) increases from 2.56 GHz (A) to 9.57 GHz (F) as inductance increases. The inductances of inductors in M3 (B and D) are reduced from those of inductors in M1 (A and C) because the lower distance to the ground increases parasitic capacitances, resulting in reduction of inductance at a given frequency. These inductor characterizations show promising results for high-q inductors allowing scalability; from Q of 126 (2.75 nh) to 58 (9.3 nh). All inductors are located in two different locations on a 9 12 in balanced double LCP panel. For preliminary verification of the large-panel process over different locations on a single board, two sets of inductors were measured in a balanced double layer LCP board. The variation of the performance was minimal and the summary of the characterization results is shown in Table I. IV. HIGH-Q EMBEDDED INDUCTOR CHARACTERIZATION IN TVS 2 AND 3 For more comprehensive characterization, 64 inductors were characterized in two large panel test vehicles, shown in Fig. 8. To achieve higher Qs in these test vehicles, the ground layers below the inductor were removed, as shown in Fig. 9. The absence of ground resulted in low parasitic capacitance through the ground layers, leading to higher Qs in the new test vehicle. Eight different inductors were designed and then located on two different layers, M1 and M3, in Fig. 2(b). Table II summarizes the design parameters of these characterized inductors. The metal width and space were 3 mil. Fig. 9 shows the X-ray picture of Inductor 3.

6 YUN et al.: HIGH-Q EMBEDDED PASSIVES ON LARGE PANEL MULTILAYER LIQUID CRYSTALLINE POLYMER-BASED SUBSTRATE 585 TABLE I SUMMARY OF INDUCTORS AT TWO DIFFERENT LOCATIONS IN TV1 TABLE II PHYSICAL DIMENSIONS AND LOCATIONS OF THE INDUCTORS IN TV2 AND TV3 Fig. 8. Photograph of TV2 and 3. Fig. 9. X-ray of Inductor 3. Fig. 10 shows the averaged Q profiles of 16 inductors at Location 1 from TV 3. The inductance ranges from 1.45 to nh. While Inductors 1 and 2 have similar inductances, Inductor 2 has been designed to have a higher SRF using different size. The highest averaged Q of 164 has been achieved for the 2.53 nh inductor on M1 from the edge location in TV 3. Compared to TV 1, this Q shows improvement of over 30% from 126 for the 2.75 nh inductor. Such an increase of Q results from lower parasitic capacitance by the removal of the ground layer under the inductor. Similar to TV 1, TV 2, and 3 also show the scalability of Qs using different layers. For example, Inductor 5 has lower Q than Q (110) of Inductor 5_top because inductor 5 has a larger parasitic capacitance because it is closer to the ground layer. This parasitic capacitance also has an effect on lowering the SRF of Inductor 5. Thru-hole interconnections used in the embedded inductors (Inductor 1 8) contributed to a slight increase in inductance compared to the top-layer inductors (Inductor 1_top to Inductor 8_top). Table III shows the measured results of the selected inductors at four locations from TVs 2 and 3. As Table III shows, different locations and different TVs create only a small variance in inductance and SRF. However, the measured results present a greater variance in Qs. Such different effects on variance result from the measurement sensitivity rather than the characteristic variance of the large panel since all other parameters show consistent results. To verify this assumption, Fig. 11 and Table IV show the pictures and the measurements of the dimensions of Inductors 3_top, which have the highest Qs. The results reveal very few variations were found among different locations and boards. In [21], additional 0.01 pf parasitic capacitance at the input, which can be generated by slightly different probing points, changes the Q by 23%, but the SRF by less than 10%. One of the main reasons for the variation of Qs is due to the variation of the parasitic capacitances in the measurements. Depending on the probing positions, parasitic capacitances from pads can vary from 0.02 to 0.03 pf. In Fig. 12, the effects of

7 586 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 Fig. 10. Measurement results of Qs of the designed inductors. parasitic capacitance on the input of inductors are shown. The parasitic capacitances, which vary from 0 to 0.05 pf, were connected to the input of Inductor 3_top in TV 3, Set 2. This particular inductor has the highest Q of 164. The Q of Inductor 3_top was reduced to 138 with 0.05 pf capacitance at the input. With a variation from 0.02 to 0.03 pf of the parasitic capacitances at the input, the Q decreased from 164 to 145, resulting in a decrease of Q by 15%. Even though the parasitic inductance associated with pads would also reduce Q, the effect would be minimal compared to the effects of the parasitic capacitances. Aside from the effects of the parasitic capacitances on the input pad, additional variations also result from the effects of averaging the measured Qs. V. TWO-STEP DE-EMBEDDING TECHNIQUE A two-step open-short de-embedding technique was originally developed for the high-frequency characterization of bipolar transistors [22]. This de-embedding technique assumes all parallel parasitics in the signal pads and all series parasitics in the interconnect lines. The de-embedding procedure begins with the open correction, followed by the short correction is a one-port admittance parameter measured on the open dummy structure and is a one-port impedance parameter measured on the short dummy structure. Although (1) de-embedding techniques such as in [23] [26] have been thoroughly researched, the two-step de-embedding technique has been chosen for its simplicity and good matching characteristics. In this paper, 32 inductors on M3 layer, which has thru-hole interconnections with GSG pads, were de-embedded to remove the effect of pads and thru-holes using the two-step de-embedding technique. In Fig. 12, the line with circles is the measured result of Inductor 6 (55 55, 1turn on M1), while the solid line is the simulated result of this inductor. As Fig. 13 shows, the SRF of simulated and measured results differ significantly because of the parasitics from pads and thru-holes. The line with squares is the measured result after the two-step de-embedding procedure was applied using the open-short technique. After the de-embedding procedure was applied, the SRF is well matched, and the inductance value also shows good model-to-hardware correlation, as shown in Table V. Table V shows a summary of the de-embedded inductances and the SRFs of 16 inductors from the two locations of TV 1. The SRFs of Inductors 1 and 2 were not measured because of equipment limitations. The Qs were not de-embedded for these inductors because of measurement sensitivity. VI. DESIGN AND CHARACTERIZATION OF COMPACT 3-D CAPACITORS Along with inductors, capacitors are the basic building blocks in the integration of RF front ends. While high Q is the critical parameter in inductors, size is the main parameter in capacitors

8 YUN et al.: HIGH-Q EMBEDDED PASSIVES ON LARGE PANEL MULTILAYER LIQUID CRYSTALLINE POLYMER-BASED SUBSTRATE 587 Fig. 11. Photographs of Inductor 3 top on the top layer (M1). (a) Photograph of Inductor 3 top. (b) Photograph of line width of Inductor 3 top. since the Q is limited by the loss tangent of the dielectric material. Fig. 14 shows the 3-D capacitors used in this paper for reducing the size. Four different types of 3-D capacitors were designed for characterization. In Fig. 14, Type 1 capacitor had port 1 on both M1 and M3 and ground layers on both M2 and M4. Vertical connections were realized using thru-holes. Table VI summarizes the four different types of 3-D capacitors. Fig. 14 shows 3-D layouts of the four capacitor types. Table VII summarizes the measurement results of the 3-D capacitors in comparison with a same-size single capacitor. 3-D capacitors show more than two-fold increase in capacitance as compared to the single capacitor. 3-D capacitors combined with 3-D inductors provide for an optimal solution for implementing compact RF module designs because of high performance, low profile, and compact size. VII. 5-GHZ FILTER AND BALUN USING EMBEDDED PASSIVES IN M-LCP The inductors and capacitors described in the previous sections using the balanced double LCP substrate, as shown in Fig. 2(b) were used for a 5-GHz filter and lumped balun. The filter was designed as a stripline configuration, i.e., both the top and bottom metal layers were used as the ground planes. This configuration provides excellent EM shielding and prevents any radiation loss. The filter was initially simulated using Agilent Advanced design systems (ADS) with ideal components and then optimized with parasitics. In this procedure, the characterizations described in the previous sections provide for accurate parasitic values, which allow a better match between circuit and EM simulations. Once ADS simulations were finalized, EM simulations were performed using SONNET. The circuit models and the 3-D layout of the filter are shown in Fig. 15. Simulation results using SONNET are shown in Fig. 16 along with measured results. The simulation result shows that 3 db bandwidth starts at 4.93 GHz, but with measured results, it starts at 5.23 GHz. The insertion loss of each result is 0.98 db for the simulation and 1.03 db for the measurement. A lumped-element balun was also designed in the same balanced LCP stack-up. Two PI networks provide a power divider with 180 out of phase at output ports. Fig. 17 shows its circuit model with the layout. Fig. 18 shows measured results with simulated results. While simulated results show 0.5dB insertion loss at 5.78 GHz, the measured results show 0.52 db at 6.08 GHz. Good phase and magnitude differences have been achieved in

9 588 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 TABLE III MEASUREMENTS RESULTS OF THE SELECTED INDUCTORS IN TV2 AND TV3 TABLE IV MEASUREMENTS RESULTS OF THE PHYSICAL DIMENSIONS OF INDUCTOR 3_TOPS IN TV2 AND TV3 Fig. 13. Measured results after the de-embedding with simulation results. achieved. The discrepancy between measurement and simulation results from mismatch at port 3. The openings in the ground plane and multiple thru-hole connections cause couplings between the components. Fig. 12. Effects of the parasitic capacitances at input of Inductor 3_top of TV3, Set 2 Fig. 19. For 5.5 to 6.5 GHz, less than 1 db magnitude difference and less than 10 (from 180 ) of phase imbalance were VIII. CONCLUSION LCP substrates are attractive high-frequency materials due to their low loss, low water absorption, and low cost. The lower cost is realized through larger panel processing, which is also processed at much lower temperature because LCP process is compatible with standard PWB process. In this paper, comprehensive characterizations have been conducted for the efficient 3-D integration of high-q passives using a balanced LCP substrate. At two different locations from three different large M-LCP panels, 76 inductors and 16 3-D capacitors were designed and measured. Inductors on different layers (the top and third layers) clearly show the scalability of Q, ranging from 43 to 164. In addition, the measured results show very little variance over the two different locations in each TV and among the

10 YUN et al.: HIGH-Q EMBEDDED PASSIVES ON LARGE PANEL MULTILAYER LIQUID CRYSTALLINE POLYMER-BASED SUBSTRATE 589 TABLE V MEASURED RESULTS OF THE INDUCTORS AFTER THE DE-EMBEDDING WITH SIMULATED RESULTS TABLE VI FOUR TYPES OF 3-D CAPACITORS Fig. 14. Three-dimensional layout of the four types of 3-D capacitors. Fig. 15. Schematic and layout of designed filter with embedded passives in a multilayer LCP substrate. (a) Schematic of filter. (b) Three-dimension layout of filter. TABLE VII SUMMARY OF MEASURED RESULTS OF 3-D CAPACITORS three different TVs. The results preliminarily validate the large panel process of the M-LCP substrate. To reduce the lateral size, multilayer 3-D capacitors were designed. The designed 3-D capacitors with inductors can provide optimized solutions for more efficient RF front-end module integration. Critical inductors for high performances can be Fig. 16. Measured and simulated results of 5-GHz filter. achieved with the highest Qs in the top-most layer, while other inductors can be embedded on other layers. As discussed in this paper, 3-D capacitors can reduce the size more effectively

11 590 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 REFERENCES Fig. 17. Schematic and layout of the designed lumped balun with embedded passives in multilayer LCP substrate. (a) Schematic of lumped balun. (b) Threedimensional layout of lumped balun. Fig. 18. Fig. 19. Measured and simulated results of a 5-GHz lumped balun. Phase and magnitude difference of the measured balun. than general parallel-plate capacitors. In addition, a two-step de-embedding technique was applied to remove the effect of pads and thru-hole interconnections. This technique resulted in closer correlations between simulation and measured results. As proof of the concept, a 5-GHz filter and lumped balun were designed and measured. Each device showed good performance and good agreement between the simulations and the measurements, which further validates the calibration and de-embedding methods used. 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12 YUN et al.: HIGH-Q EMBEDDED PASSIVES ON LARGE PANEL MULTILAYER LIQUID CRYSTALLINE POLYMER-BASED SUBSTRATE 591 [21] J. K. Lee, C. S. Yoo, H. C. Jung, W. S. Lee, and J. K. Yook, Design of band pass filter for 900 MHz zigbee application using LTCC high Q inductor, in APMC 2005 Microw. Conf. Proc., Dec. 4 7, 2005, vol. 1, pp [22] Coilcraft, Measuring self resonant frequencye Cary, IL, 2003 [Online]. Available: [23] M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, An improved de-embedding technique for on-wafer high frequency characterization, in Proc. BCTM, pp , [24] L. F. Tiemeijer and R. J. Havens, A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors, IEEE Trans. Electron Devices, vol. 50, no. 3, pp , Mar [25] H. Cho and D. Burk, A three step method for the de-embedding of high frequency s-parameter measurements, IEEE Trans. Electron Devices, vol. 38, no. 6, pp , Jun [26] T. E. Kolding, A four-step method for de-embedding gigahertz on-wafer CMOS measurements, IEEE Trans. Electron Devices, vol. 47, no. 4, pp , Apr [27] E. P. Vandamme, D. M. M.-P. Schreurs, and C. van Dinther, Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures, IEEE Trans. Electron Devices, vol. 48, no. 4, pp , Apr Wansuk Yun received the B.S. and M.S. degrees from Yonsei University, Seoul, Korea, and the M.S. degree from the Georgia Institute of Technology, Atlanta, where he is currently working toward the Ph.D. degree in the Electrical and Computer Engineering Department. His research interests are the design of RF front-end module, RF system using embedded passive components, and RFIC. He is also working on the characterization and modeling of interconnects. Venky Sundaram received the B.S. degree in metallurgical engineering from the Indian Institute of Technology, Bombay, India, and the M.S. degree in ceramic and materials engineering from the Georgia Institute of Technology, Atlanta, where he is currently working toward the Ph.D. degree in materials science and engineering. He is Assistant Research Director and a research staff member at Georgia Institute of Technology PRC and is currently co-leading the SOP package substrate development program at the PRC. He has more thank seven years experience in high-density microvia board and thin film technology. He is a PRC program manager for the SOP technology transfer partnership with Endicott Interconnect, New York, and the high-density substrate task leader for the multimillion dollar nano-wafer level packaging program. He has more than 30 publications, four patents pending, and a number of invention disclosures in SOP substrate technology and RF/Digital packaging. He has presented industry short courses on Embedded Passives and High Density PWB Technologies. Mr. Sundaram is a member of the High Density Substrate Technical Committee (TC-6) of IEEE-CPMT Society. Madhavan Swaminathan (M 95 SM 98 F 06) received the B.E. degree in electronics and communication from the University of Madras, Madras, India, and the M.S. and Ph.D. degrees in electrical engineering from Syracuse University, Syracuse, NY. He is currently the Joseph M. Petit Professor of Electronics in the School of Electrical and Computer Engineering, Georgia Institute of Technology, and the Deputy Director of the Packaging Research Center, Georgia Institute of Technology. He is the founder of Jacket Micro Devices, a company specializing in integrated devices and modules for wireless applications where he serves as the Chief Scientist. Prior to joining Georgia Tech, he was with the Advanced Packaging Laboratory at IBM working on packaging for super computers. He has over 250 publications in refereed journals and conferences, has coauthored three book chapters, has 12 issued patents, and has ten patents pending. While at IBM, he reached the second invention plateau. His research interests are in mixed signal microsystems integration which include digital, RF, optoelectronics, and sensors with emphasis on design, modeling, characterization and test. Dr. Swaminathan served as the Co-Chair for the 1998 and 1999 IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), served as the Technical and General Chair for the IMAPS Next Generation IC & Package Design Workshop, serves as the Chair of TC-12, the Technical Committee on Electrical Design, Modeling and Simulation within the IEEE CPMT Society, and was the Co-Chair for the 2001 IEEE Future Directions in IC and Package Design Workshop. He is the co-founder of the IMAPS Next Generation IC and Package Design Workshop and the IEEE Future Directions in IC and Package Design Workshop. He also serves on the technical program committees of EPEP, Signal Propagation on Interconnects workshop, Solid State Devices and Materials Conference (SSDM), Electronic Components and Technology Conference (ECTC), and International Symposium on Quality Electronic Design (ISQED). He has been a guest editor for the IEEE TRANSACTIONS ON ADVANCED PACKAGING and IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He was the Associate Editor of the IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES. He is the recipient of the 2002 Outstanding Graduate Research Advisor Award from the School of Electrical and Computer Engineering, Georgia Institute of Technology and the 2003 Outstanding Faculty Leadership Award for the mentoring of graduate research assistants from Georgia Institute of Technology. He is also the recipient of the 2003 Presidential Special Recognition Award from IEEE CPMT Society for his leadership of TC-12 and the IBM Faculty Award in 2004 and He has also served as the coauthor and advisor for a number of outstanding student paper awards at APMC 05, EPEP 00, EPEP 02, EPEP 03, EPEP 04, ECTC 98, and the 1997 IMAPS Education Award. He is the recipient of the Shri. Mukhopadyay Best Paper Award at the International Conference on Electromagnetic Interference and Compatibility (INCEMIC), Chennai, India, 2003, the 2004 Best Paper Award in the IEEE TRANSACTIONS ON ADVANCED PACKAGING, the 2004 Commendable Paper Award in the IEEE TRANSACTIONS ON ADVANCED PACKAGING and the Best Poster Paper Award at ECTC 04 and ECTC 06.