On-Chip Passive Devices Embedded in Wafer-Level Package

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1 On-Chip Passive Devices Embedded in Wafer-Level Package Kazuya Masu 1, Kenichi Okada 1, Kazuhisa Itoi 2, Masakazu Sato 2, Takuya Aizawa 2 and Tatsuya Ito 2 On-chip high-q spiral and solenoid inductors on Si substrate embedded in WLP have been fabricated. These inductors consisted of a thick Cu electroplated rerouting to reduce electrical resistance and a thick resin layer to separate the inductors typically 2 µm from Si substrate. An inductance L of. and 4.9 nh with a Q of 28.4 and 42.9 were obtained for a 3. turn rectangle spiral inductor at 2 GHz on the Si substrate, which had a resistivity of 4 Ωcm and 1 kωcm, respectively. In addition, the measured results of Q, L and fres corresponded well with the simulated values by HFSS and Sonnet. This technology realizes embedded high quality inductors in WLP. 1. Introduction As wireless communication systems such as cellular phones, wireless local area networks (LAN) and radio frequency identification (RFID) systems are being more widely used, there are greater demands for radio frequency integrated circuit (RFIC) to improve performance, multifunction, small footprint and low cost 1). Recently, the application of Si complementary metal oxide semiconductor (CMOS) process to RFIC system has rapidly improved and has been greatly relied on to achieve these demands. In RF analog system, it is essential to integrate active circuits with passive circuits such as resistor, inductor and capacitors. However, the performance of on-chip inductor on Si substrate is the most restricting element in passive circuits compared to that on GaAs substrate, which has been commonly used for GHz devices. Indeed, it is reported that on-chip inductor on low noise amplifier (LNA) occupies 3 % of noise factor 2) and electric power consumption of voltage-controlled oscillator (VCO) will be cut by half with the enhancement of 3 % of (Q) of on-chip inductor 3). There are two reasons that restrict the improvement of Q in Si RFIC. Firstly, when an onchip inductor on Si substrate operates at high frequency, there is a coupling effect between the on-chip inductor and Si substrate. As a result, the magnetic flux from the on-chip inductor passes close to Si substrate and the consumption of the stored energy by the eddy current in Si substrate leads to low Q. In addition, the magnetic flux will affect active circuit so that it is impossible to locate on-chip inductor on active circuit through a thin passivation layer, and the 1 Precision and Intelligence Laboratory, Tokyo Institute of Technology 2 Micro Device Department, Electron Device Laboratory, Fujikura Ltd. footprint also increases. Secondly, thin metallic layer, usually aluminum (Al), increases DC resistance of onchip inductor. Due to these problems, Q is usually restricted to approximately as high as 1 without using the particular technique. In order to overcome these problems, several techniques have been reported for on-chip inductors with CMOS technology such as using proton implantation 4), ground pattern, optimum routing pattern and multilayer inductors, however, the difficulties of energy consumption by the eddy current in Si substrate and high ohmic resistance of the inductor are intrinsic and inevitably lead to reduced Q and fres. Recently, high Q inductors using thick metal and polyimide layers ) 6) and MEMS technology have been reported. These kinds of inductors are made by etching the Si substrate under a coil pattern 7), a sacrificial layer for air-core inductors and a 3D structure 8)- 13). These studies indicated good performances; however, the special techniques in CMOS technology were essential to fabricate the inductor and the structure of the inductor was so delicate that particular attention had to be paid to package the inductors. From these points of view, this paper describes the fabrication of all on-chip inductors embedded in wafer-level package (WLP). The schematic illustration of the on-chip inductors in WLP is shown in Fig. 1 14). This WLP structure consists of dual Cu electroplated layers, dual resin layers, an encapsulation layer and lead-free solder bumps. The embedding inductors are located between the second resin layer and the encapsulation layer in conjunction with waferlevel packaging process. Accordingly, this technology has the desirable features of (1) having conductive lines separated by a thick resin layer to reduce the Fujikura Technical Review, 26 49

2 Lead-free bump Inductor Die Table 1. Geometrical patterns and typical dimensions of the fabricated inductors. Item Spiral Solenoid Turn number Si resistivity 4 (A-type), > 1k (B-type) Ωcm Cu thickness (1 st ), 1 (2 nd ) µm Resin thickness 1 (1 st ), 1 (2 nd ) µm Line / Space 3 / 2 µm Al pad Cu rerouting 1 st Resin Fig. 1. Schematic illustration of on-chip inductors in WLP. 1 st Resin Si SiO2 induced eddy current in Si substrate; (2) being supported by thick electroplated low-resistive Cu, and (3) eliminating additional inductance from wire bonding. In addition, WLP technology has already achieved thermal stabilization, high reliability and cost efficiency 1). This paper describes the details of fabrication processes of spiral and solenoid inductors on a Si substrate and presents the experimental characteristics as well as comparison with the simulated values. These inductors were made onto bare-si wafer in this work; however, this process is compatible with an actual wafer. 2. Structures and fabrication process A variety of geometry was designed and analyzed by electromagnetic field simulators (HFSS and Sonnet). Table 1 shows geometrical patterns and typical dimensions of the fabricated inductors. Figure 2 shows a schematic fabrication process representing the cross-section of the spiral inductor. 3. Results and discussion Figure 3 shows the SEM photograph of the fabricated 3. turn square spiral inductor and solenoid inductor. DC resistance, effective inductance L and Q of the fabricated inductors were evaluated. The typical DC resistance of a 3. turn spiral inductor was.28 Ω as measured by the standard 4- point probe method and the contact resistance between the first and the second Cu layer via contact pad was about 3 mω by measuring the daisy chain patterns. By contrast, the calculated resistance of the inductor was.271 Ω. Accordingly, the measured result of the 3. turn inductor including the contact resistance due to two contact holes was almost identical with the calculated values. It is important that the resistance of the fabricated inductor was more than 1 times lower than that of the conventional inductor with the resistance of 3.4 Ω, which consisted of dual 1. µm-thick Al layers in the same geometry of a 3. turn spiral inductor. The Q and L were measured using a network ana- (a) Resin coating and curing (b) Formation of bottom conductive layer by Cu electroplating (c) Photosensitive resin coating, patterning and curing (d) Formation of upper conductive layer including coil patterns, grounds pattern and test pads by Cu electroplating (e) Formation of encapsulation layer by coating and curing of resin Fig. 2. Schematic cross-sectional diagram of the fabrication process. Fig. 3. SEM photograph of a fabricated inductor. (Left) Spiral inductor, (Right) Solenoid inductor

3 lyzer and a probe station having ground-signalground (G-S-G) coplanar probes. The evaluation was carried out from 1 MHz to 2 GHz with SOLT calibration. The short and open patterns were applied to de-embed the shunt parasitic capacitance due to G-S- G pads and the series resistance such as the contact resistance between the probe pad and the probe tip as well as the series loss of interconnects. Measurement by the network analyzer extracted the S-parameter of the inductors open and short patterns. After that, S-parameter of the inductor was deembedded from the open and short patterns. The Q and L were derived from the following equations 13). Im Y Q = { 11 }...(1) Re { Y11 } 1 1 L = Im...(2) 2 πf { Y11 } Figure 4 shows the lumped-element equivalent circuit of an on-chip inductor. It is obvious that the cross-sectional structure of the inductor strongly affects Q and fres, which includes the substrate loss by the induced eddy current (RSi), coupling capacitance among Cu layers (CS), and that between coil pattern and resin layers (Cre) or Si substrate (Cox, CSi) in this model. Conversely, the geometrical coil pattern mainly determines its inductance L (LS), and then slightly RSi Cre Cox CSi LS CS RS CSi Cre Cox Fig. 4. The equivalent circuit of the embedded inductor Spiral 2GHz ρ =4Ωcm ρ =1kΩcm number of turns (N) RSi inductance (nh) Fig.. The measured results of Q and L at f = 2GHz of fabricated inductors as a function of different number of turns. affects Q and fres. Figure shows the measured results of Q and L at f = 2GHz of fabricated spiral inductors as a function of different number of turns. The fabricated spiral inductors at 3. turns denote a Q of 28.4, which had a ρ of 4 Ωcm and 1 k Ωcm, respectively. The Q of the fabricated inductors denotes higher performance than that of conventional on-chip inductor, which is usually limited to about 1 or less. The strong points of the embedding inductors in WLP, in which the lower series resistance of the inductor (RS) by the thick Cu electroplating and the thick resin layer to separate the inductor from Si substrate, achieve higher Q in these inductors. Meanwhile, the fabricated inductor of ρ of 1 k Ωcm denoted a Q of 42.9 at 2 GHz and tended to be higher than that of ρ of 4 Ωcm. Although the coil pattern of both types was separated 2 µm from the substrate, the influence of the induced eddy current in Si substrate still existed and reduced the Q in the lower one. The resin thickness of more than 4 µm is required in order to saturate the enhancement of Q in the lower ones by simulating the electromagnetic simulator. As regards the inductance value, the fabricated inductors denote an L of. nh at 2 GHz, which is same as that of the designed value. Measured results of L in all types were almost identical with the designed values. This result supports the finding that mainly the geometrical pattern of spiral inductor determines the inductance value, L, and its cross-sectional structure does not influence this value. The equivalent circuit parameters of the inductor from Fig.4 were analyzed by using Agilent Design System (ADS). The fabricated inductor achieved an RSi of about 6 k Ω at 2. turns. It should be noted that the RSi is about 1 times higher than that of a conventional on-chip inductor on Si substrate 4) ; hence WLP technology obviously denotes the significant features of the embedding inductor for RF applications. The fabricated inductors generally denote much lower RSi than that of the conventional one, which is caused by the thick resin layer and the thick Cu conductor. Figure 6 shows the measured results of fres of the fabricated inductors as a function of different number of turns. The shift toward lower frequency of fres was obtained with increasing number of turns. Generally, it is necessary for fres to exceed 3 times higher than the frequency of the targeting applications. In both types of 3. turn inductors, a good performance of fres of higher than 7 GHz was obtained and was sufficient for the applications that were used in 2 GHz range. In addition, fres close to 1 GHz was obtained in 2. turns with an L of 2. nh. They can be applied to the applications used in GHz range. Figure 7 shows a comparison of simulated Q at f = 2 GHz of the solenoid inductor and a 3. turn spiral Fujikura Technical Review, 26 1

4 SRF (GHz) Spiral inductor ρ =4Ωcm ρ =1kΩcm number of turns (N) turn spiral measured (B) HFSS Sonnet frequency (GHz) Fig. 6. The measured results of fres of fabricated inductors as a function of different number of turns. Fig. 8. Comparison between the measurement results and simulated values in 3. turn spiral inductor f =2GHz Spiral (measured) Spiral (simulated) Solenoid (measured) Solenoid (simulated) thickeness of 1 st resin (µm) Fig. 7. Q of the spiral and the solenoid as a function of the thickness of the first resin layer. inductor with the fabricated result as a function of the thickness of the first resin layer. Q of the spiral-type was more than twice that of the solenoid-type. In solenoid-type inductor, ten contact holes of 2 µm 2 existed and those were narrower than the contact pad of 8 µm 2 because of the margin in the manufacturing, while there were only two contact holes in the spiral-type inductor. It is expected that the difference in the shape between the contact hole and the contact pad forms a discontinuity point in terms of high frequency characteristics and influences on the performances, especially Q. Therefore, it is estimated to be one of the reason that Q of spiral-type was higher than that of solenoid-type in this structure. By contrast, the saturation of Q in solenoid inductor was obtained at the thickness of 2 µm of the first resin layer, while that of about 4 µm was necessary in the spiral-type inductor. It suggests that the effect of the induced eddy current in Si substrate in the spiral inductor is more extensive than that of the solenoid inductor and a thicker resin layer is necessary for the spiral inductor to obtain maximum Q in this geometry. Figure 8 shows a comparison of the simulated Q by HFSS and Sonnet as a function of frequency with the fabricated result of the 3. turn spiral inductor. Both of the simulated values corresponded well with the fabricated result. The differences in Q between the simulated values and the fabricated result at 2 GHz were 9.2 and 7.2 % in HFSS and Sonnet, respectively. Moreover the simulated values of L at 2 GHz were also corresponded with an accuracy of.2 and 1.2 % in HFSS and Sonnet, respectively. The deviations from different number of turns and types stayed within an accuracy of Q of 1 % and L of 1 %. These electromagnetic simulators demonstrated that they were quite effective tools to design the on-chip spiral inductors on Si substrate as well as these inductors were embedded in WLP including thick resin layers and Cu conductors. 4. Conclusion In order to achieve high performance of passive components integrated with CMOS circuit, high-q spiral inductors on Si substrate embedded in WLP have been fabricated. This structure consisted of a thick electroplated copper rerouting layer as a lowloss conductor, thick resin layers in order to reduce the substrate loss and solder bump interconnections to avoid additional inductance from wire bonding. The inductance L of. and 4.9 nh with Q of 28.4 and 42.9 were obtained for a 3. turn rectangular spiral inductor at 2 GHz in ρ of 4-6 Ωcm and 1k Ωcm, respectively. In addition, the simulated results well corresponded with the measured results. We have demonstrated that these embedding inductors in WLP enable us to give a full solution for high-performance of RF-IC to achieve its chip-size footprint with thermal stabilization and high reliability. 2

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