A Small Area 5GHz LC VCO with an On-Chip Solenoid Inductor using a 0.13μm Digital CMOS Technology

Transcription

1 A Small Area 5GHz LC VCO with an On-Chip Solenoid Inductor using a 0.3μm Digital CMOS Technology Chul Nam, Byeungleul Lee 2, Tae-Young Byun 3, Yongjun Jon 4, and Bonghwan Kim 5,* R&D Center/Siliconharmony, Seong Nam-Si, Korea 2 Mechatronics Engineering, Korea University of Technology and Education, Chungnam, Korea 3 School of Information Technology Engineering, Catholic University of Daegu, Gyeongbuk, Korea 4 TIOS Inc., Gyeongbuk, Korea 5 Electronics Engineering, Catholic University of Daegu, Gyeongbuk, Korea * bhkim@cu.ac.kr ABSTRACT This paper presents a small area LC VCO with an on-chip solenoid inductor using 0.3μm digital CMOS technology. This on-chip solenoid inductor is vertically built by metal and via layers with a horizontal occupation which gives the advantages of small area due to 3-D nature compared to a spiral inductor. Based on 3-D EM simulation and analysis, the unified equivalent model for a solenoid inductor is proposed so that it could be adapted for LC Voltage controlled oscillator in the digital standard CMOS process. The designed LC VCO has the occupation area as 0.03 mm 2 and the frequency tuning range as GHz. The measured phase noise of VCO was measured as dBc/Hz at a MHz offset with the power consumption of 3.2mW with total area of 0.028mm 2. KEYWORDS On-chip solenoid inductor, LC VCO, EM simulation, CMOS. INTRODUCTION Even though the high speed digital complementary metal-oxide semiconductor (CMOS) technology has been developed up to several GHz in the frequency, the inductorcapacitor (LC) voltage controlled oscillator (VCO) are still requiring the RF process with the ultra-thick metal spiral inductor. In other hands, for the sake of low cost process, the digitally controlled oscillator (DCO)s have been studied operating at the several gigahertz range in the digital CMOS technology [-2]. The spiral inductor used in DCOs, however, is still a copy of one used in RF process sacrificing quality factor and occupying large area, what is worse, causing the high processing cost. In addition, circuit designers have to face the challenges in designing one s own spiral inductor and take responsibility for its performance even after electromagnetic (EM) simulation was done through EDA tools such as Agilent Momentum, FEMLAB, Sonnet, ASTIC [3] and HFSS [4] etc. A study of solenoid inductor has been done mainly in microelectro-mechanical-systems (MEMS) technology [5]. An electroplated MEMS inductor had been reported with a high quality factor and an inductance of a tenth of nh owing to the good conductivity of copper [6]. However, its application into CMOS process results in the additional mask steps and increases the processing cost. Before 0.3μm CMOS process, the poor conductivity of Al in CMOS process had to use a thick metallization method interconnecting more than two metals to reduce the series resistance of inductor. Therefore, the copper metallization below 0.3μm CMOS standard process has introduced the possibility of implementing a low series resistance inductor in LC type VCO while the large area spiral inductor is still obstacle for the low cost standard CMOS process. ISBN: SDIWC 22

2 In this paper, on-chip solenoid inductors using metal and via stacking were designed and their electrical characteristics in terms of inductance and quality factor were simulated using 3D-EM simulator [7]. Designed inductors according to the different dimension had been implemented and measured its characteristics by two port S- parameters using a HP E4440A. The measured S-parameters were used in analyzing the proposed equivalent lumped model and further the linearized equation through the parameter optimization. Based on this model, a LC type VCO with on-chip solenoid inductor had been designed and measured in regards to its tuning range and phase noise. number of turns (N) and the pitch (p) between each turn. As the cross area is determined by the process technology, the inductance is then proportional to the width (W) and the number of turns (L S N W). Normally, the series resistance of the inductor (R S ), which mainly affects the quality factor, is increased by the skin effect [8] and the proximity effect according to operating frequency. In solenoid inductor, the proximity effect can be ignored as the conductor moves farther from the adjacent turns. R S is rewritten approximately as; R s = R dc t δ ( e t δ ) = ρ 2NW + 2W w W l t δ ( e t δ ) () 2. ON-CHIP SOLENOID INDUCTOR Usually, the magnetic flux of the spiral inductor using the planar CMOS process penetrates the substrate with its axis perpendicular to the surface. Naturally, the spiral inductor has impairment about a low quality factor due to the substrate loss and a reason to put the pattern ground shield under the inductor. On the other hand, the building of solenoid inductor is completed to connect the top plates (M6) and the bottom plates (M) through vias (V-V5) as shown in Fig. [7]. Since its axis is parallel to the substrate, the solenoid inductor is less susceptible to the substrate losses due to the eddy current. 0.37µm H Wl Bottom Plate PORT l W p 0.28µm Ww W Top Plate PORT2 V5 V4 V3 V2 V Figure. A structure of the solenoid inductor [7]. In general analysis, the macro-scale inductance of solenoid is expressed in terms of its dimension such as cross-section area, the M6 M5 M4 M3 M2 M δ = ρ πμf (2) where t, W w and W l represent the metal thickness, the post width and the post length, and ρ, μ and ƒ are the resistivity of the copper, the permeability of the air and the operating frequency, respectively [7]. For 5GHz frequency applications, the skin depth, δ, is about 0.94μm and can be ignored as it is larger than the top metal thickness 0.9μm, for example, in 0.3μm digital CMOS process[7]. The series resistance, R S becomes.2 R dc and in the same way, the quality factor can be expressed as Q = ω L S R dc W N (3) In equation 3, the width (W) is quite larger than the post width (W w ) and length (W l ) and R dc is also proportional to N W, and then the quality factor becomes inversely proportional to N W. From equation (), (2) and (3), we can suggest the design parameters of the solenoid inductor as W and N. These parameters give the good golden rule designing the solenoid inductor. ISBN: SDIWC 23

3 3. LC VCO DESIGN & CHARACTERIZATION The proposed LC VCO with on-chip solenoid inductor consists of a negative-gm circuit, a pair of varactor for fine tuning, and a varactor tuning bank for coarse tuning as show in Fig. 2 and Fig. 3. Once the solenoid inductance (L S ) is determined according to the number of turn (N) from the linearized equation [7], the oscillation frequency of VCO can be calculated with the fine and coarse tuning capacitance by; Equation 4. f osc = P R SI 2π L s (C dsv + C fvar ) (4) N*R S N*C P C SI N*L S R SI P2 N*C P Figure 2. The proposed unified equivalent model of solenoid inductor. C SI the varactor capacitance at nth control signal can be expressed in terms of the effective switchable capacitance and control signals as; C dsv,n = C low,n + D[n] C dsv,n (5) Furthermore, if varactor capacitor array is binary-weighted, the total capacitance of the varactor bank becomes; C dsv = 2 3 C low,0 + C dsv (6) C dsv = C dsv,0 n=2 2 n n=0 D[n] (7) Then, the maximum variable capacitance which contributes the total frequency range is 7 times the effective switchable capacitance, that is ΔC dcv_max = 7 ΔC dsv,0 =7 (C high,0 -C low,0 ), in which the subscript 0 denotes LSB. This makes the tunable frequency range as; f = f max f min = f max ( C low,0 C high,0 (8) f max, f min 2πL s 7 C low,0 2πL s 7 C high,0 (9) where, C fvar < 7 C low,0 <7 C high,0. Figure 3. The proposed LC VCO circuit. In the proposed LC VCO, the varactor tuning bank composed of C -C 6 is controlled by signals, D[2:0] to cover the wide frequency tuning range. The varactor capacitance is highest (C high,n ) when the corresponding control signal, D[n] is asserted high and lowest(c low,n ) when D[n] is low. The difference between the highest and lowest capacitance by nth bit becomes the effective switchable capacitance (ΔC dsv,n ) using ΔC dsv,n =C high,n -C low,n [9]. Thus, Figure 4. The measured VCO spectrum output. The LC tuned VCO adopting of solenoid inductor with W=60μm and N=8 was measured with a spectrum analyzer (HP E4440A) as shown in Fig. 4. The center ISBN: SDIWC 24

4 frequency of VCO is tuned to 5.78 GHz with.5v supply. The measured phase noise was dBc/Hz at an offset frequency of MHz from the carrier frequency as shown in Fig. 5. Figure 6 shows that the measured total tuning range is about 924MHz (20% of the center frequency) by the coarse tuning from 4.8GHz to 5.9GHz. The fine tuning is done after the coarse tuning is performed by an analog signal, V ctrl. The VCO gain (KVCO) was measured at about 24MHz/Volt, which means either increasing the VCO gain or extending more coarse control bits to cover the missing frequency between steps. LC VCOs [0-2]. Figure 7 shows the layout and die photograph of the proposed LC VCO. The figure of merit (FOM) for VCOs can be calculated by; FOM = PN f 20 log( f o f ) + 0 log P mw (0) From the measured phase noise, the FOM was calculated to be -68 dbc/hz dBc/Hz (a) (b) Figure 7. The proposed LC VCO: (a) Layout and (b) die 4. CONCLUSIONS Frequency(GHz) Figure 5. The measured VCO phase noise. f=924mhz D<2:0>=00 D<2:0>=00 D<2:0>=0 D<2:0>=00 D<2:0>=0 D<2:0>=0 D<2:0>= Vctrl(Volt) D<2:0>=000 Figure 6. The VCO frequency tuning curves (W=60 μm N=8) The proposed LC VCO has the smallest size except for by using the small area solenoid; it is about 5 and 0 times smaller than the reported A small area LC VCO with an on-chip solenoid inductor was fabricated using the 0.3μm digital CMOS process without any additional thick metal option required for RF process. Due to the metal and via stacked on-chip solenoid inductor, the area of LC VCO is remarkably reduced to one tenth of the size of the conventional spiral inductor. The LC VCO operates from 4.8 to 5.9GHz with a 20% wide tuning range. The measured phase noise at the MHz offset frequency is dBc/Hz. The power consumption of the VCO core is 3.2mW. This small area LC VCO is suitable for low cost wireless PLLs in the standard CMOS process and can be used as an integrated matching network with small occupation area for LNA or Mixer. With further quality factor improvement, this solenoid inductor can be used in low power mobile applications. ISBN: SDIWC 25

5 ACKNOWLEDGMENT This research was also supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (203RAA4A002255). REFERENCES [] R. B. Staszewski and P. T. Balsara, All-Digital Frequency Sytheszer in Deep-submicron CMOS, A Jon Wiley & Sons, [2] P.-L. Chen, C.-C. Chung, and C.-Y. Lee, A portable Digitally Controlled Oscillator Using Novel Varactors, IEEE Trans. on Circuits and Systems, Vol. 52, No. 5, May 2005, pp [0] R. Tao and M. Berroth, The design of 5GHz voltage controlled ring oscillator using source capacitively coupled current amplifier, IEEE Radio Frequency Integrated Circuits Symposium, pp ,2003. [] B. Soltanian, H. Ainspan, W. Rhee, D. Friedman, and P. Kinget, An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback, IEEE Coustom Integrated Circuits Conference (CICC), Sept. 2006, pp [2] N. Fong, J. Plouchart, N. Zamdmer, L. Duixian, L. Wagner, C. Plett, and N. Tarr, A -V GHz wideband VCO with differentially tuned accumulation MOS varactor for common-mode noise rejection in CMOS SOI technology, IEEE transactions on Microwave Theory and Techniques, Vol. 5, No. 8, Aug. 2003, pp [3] ASTIC; Analysis of Si Inductors and Transformers for ICs, [4] Ansoft HFSS [5] J. B. Yoon, B. K. Kim, C. H. Han, E. Yoon, and C. K. Kim, Surface micromachined solenoid on-si and on-galss inductor for RF applications, IEEE Electron Device Letters, Vol. 20, No. 9, Sept. 999, pp [6] S. Seok, C. Nam, W. Choi, and K. Chun, A High Performance Solenoid-type MEMS Inductor, Journal of semiconductor technology and science, Vol., No. 3, Sep. 200, pp [7] C. Nam, B. Lee, H. C. Kim, J. Kim, D. W. Chang, and B. Kim, 3-D Solenoid Inductor Analysis in a 0.3 μm Digital CMOS Technology, International Journal of Electronics and Electrical Engineering, Vol. 2, No. 4, Dec. 204, pp [8] C. Nam, J.-S. Park, Y.-G. Pu, and K.-Y. Lee, A - GHz Tuning range DCO with a 3.9KHz discrete tuning step for UWB frequency Synthesizer, IEICE trans. on Electronics, E93-C, No.b, Jun. 200, pp [9] T. H. Lee, The Design of CMOS Radio-frequency integrated Circuits, Cambridge, United Kingdon, 998, pp. 50. ISBN: SDIWC 26