A Design of 8.5 GHz META-VCO based-on Meta-material using 65 nm CMOS Process

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1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.5, OCTOBER, 2016 ISSN(Print) ISSN(Online) A Design of 8.5 GHz META-VCO based-on Meta-material using 65 nm Process Jongsuk Lee and Yong Moon Abstract A low phase noise META-VCO based-on meta-structure was designed using 65 nm process. We used a meta-structure to get good phase noise characteristics. The measured phase noises are dbc/hz, dbc/hz, and dbc/hz at 100 khz, 1 MHz, and 10 MHz offset respectively. The META-VCO operates 8.45~8.77 GHz according to V CTRL, and the output power is dbm. The power consumption is 28 mw with 1.2-V supply voltage. The calculated FOM is dbc/hz. Index Terms, voltage controlled oscillator (VCO), Meta-material I. INTRODUCTION Meta-material is artificial structure having the property that does not exist in nature, it enables to realize radio wave characteristics which are impossible in practical like negative permittivity or negative permeability [1]. LC resonator consisting of inductor has low Quality factor (Q-factor) at especially high frequency such as several of GHz or more due to parasitic capacitance and self-resonant frequency of inductor. And capacitor is usually used for MOS varactor but it has leakage current, because gate of MOSFET is very thin. However, metastructure has high Q-factor according to large coupling coefficient, because unit cell having narrow band-pass filtering, low radiation loss and sharp selectivity and unit cell are attached to several of μm [1, 2]. So using Manuscript received Mar. 15, 2016; accepted Jun. 8, 2016 School of Electronic Engineering, Soongsil University, Korea ljs1385@ssu.ac.kr resonator consisting of meta-structure is useful to reduce phase noise of oscillator. If meta-material is applied to analog circuit design, the properties not exist in the conventional circuits could be possible. VCO (Voltage-Controlled Oscillator) is an important analog circuit component for communication systems using clock signal [3-5]. If VCO is implemented using process, it has many advantage of low cost, low power consumption, and small area. So metastructure is implemented by process in order to VCO has these advantages. In this paper, we apply periodic meta-structure to VCO to improve the phase noise characteristics, and the novel META-VCO (meta-structure VCO) using process is proposed. The remainder of this paper is organized as follows. In Section ІІ, the proposed meta-structure design and VCO design are presented. The circuit implementation is described in Section ІІІ while post-simulation results and experimental results of the VCO are provided in Section ІV. Finally, the conclusion is given in Section V. II. META-STRUCTURE AND VCO DESIGN 1. Meta-structure Design The design process can be divided into two main. First, meta-structure was designed and verified using 3-D simulator. In design, thickness and width of pattern, distance between patterns, and so on are only available values implemented in process. Second, metastructure was implemented to chip using 65 nm process with CADENCE CAD tool. The chip was designed with the same pattern and same thickness of

2 536 JONGSUK LEE et al : A DESIGN OF 8.5 GHZ META-VCO BASED-ON META-MATERIAL USING 65 NM PROCESS Passivation Pattern Dielectric µm 1.3 µm 7.55 µm Ground + Substrate µm Fig. 1. Meta-structure top view, cross-section. Fig. 2. Schematic of the META-VCO. layer in the meta-structure of 3-D simulator. Meta-structure was implemented by arranging SRR (Split Ring Resonator) to obtain negative permeability [1]. But we used SRR to realize LC-tank with high Q- factor. The proposed meta-structure is shown in Fig. 1. At same frequency, the area of the proposed metastructure is um 2 and conventional inductor and capacitor is um 2 in 65 nm process. (For this comparison, capacitance of the capacitor is the minimum value.) The inductance is decided by the length of the pattern and the capacitance is decided by the gap between pattern and ground or pattern and pattern. Therefore, the desired frequency characteristic of the LC resonance could be obtained by adjusting the width and length of the pattern, the dielectric thickness, and the distance between the pattern and the pattern. Using these properties, we replaced LC resonator with the proposed meta-structure. We used 3D CAD tool to analyze the property of the meta-structure. Using the process parameters like the thickness of the layers, the relative permittivity, the relative permeability, conductivity, and so on, we could get the parameters of materials composing meta-structure. In Fig. 1, the thickness of the passivation is μm, the pattern is 1.2 μm, dielectric is 7.55 μm, ground is 1.1 μm and substrate is 775 μm. The relative permittivity of each layer is different each other. For example, the Passivation layer is consisted of 3 layers and has relative permittivity of 3, 7, and 4.3 from above. The relative permittivity of pattern is 1, but the Ground layer and Dielectric layer have various relative permittivity because they are composed of other types of metal layers and via layers. The relative permittivity of the Substrate layer is 11.9 silicon dielectric constant. So we could design the desired meta-structure using these thickness and soon. 2. META-VCO Design The schematic and the device size of the VCO applying the meta-structure is shown in Fig. 2. The architecture based-on the proposed META-VCO was composed of LC resonator of the meta-structure, NMOS cross-coupled differential pair to generate negative resistance, and two varactors to control resonance frequency. The oscillation frequency goes down because of the capacitance of the varactor. MN3 and MN4 are output buffer, and VDDA and VDDB are separated to prevent the noise influence from the noise of the output buffer. R ISOL is very small resistor with the value of 4 Ω, and helps to reduce the noise of the power supply in measurement environment. III. CIRCUIT IMPLEMENTATION AND SIMULATION RESULTS A. Meta-structure Implementation HFSS was used to 3-D simulator and the design environment of meta-structure and information of layers are shown in Fig. 3. In order to confirm resonant frequency of the Metastructure, the verification of multiple steps was used. At first, S-parameter characteristic is used and Fig. 4 shows S 21 and S 11 of the meta-structure. From Fig. 4, it

3 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.5, OCTOBER, Fig. 3. The proposed meta-structure on HFSS simulator, Information for the layers of the proposed meta-structure on HFSS simulator. was confirmed that the proposed meta-structure had 51 GHz oscillation frequency. The simulation results of the proposed meta-structure are applied to VCO simulation and Fig. 4 is the example of extracted S-parameters. Secondly, we modeled the meta-structure and the simplified modeling is shown in Fig. 5. Inductance and capacitance value was calculated by Eqs. (1, 2) [6], and ports were connected to OSCP and OSCM, and located at upper side. L» m0 n 2 davg c1 é c2 2ù êln( ) + c3 r + c4 r ú 2 ë r û d out - din r= d out + din Fig. 4. S-parameter simulation result of the meta-structure, Example of extracted S-parameters of the meta-structure. (1) (2) In Eqs. (1, 2), n is the number of turns, davg is the arithmetic mean of the inner and outer diameters, dout is the outer diameter, din is the inner diameter, and ρ is the fill factor. Furthermore, c1-c4 are the coefficients for the current-sheet inductance and they are shown in Table 1. In calculation results, the inductance of two SRRs at upper was 263 ph, since the pattern was split in both side from the port. Two SRRs at lower area down was 526 ph and SRRs between upper side and lower area was coupled by the capacitance between patterns. 1 mm length of pattern was calculated to 1 nh, the inductance Fig. 5. Modeling of the proposed meta-structure. Table 1. Coefficients for current-sheet inductance formula Shape c1 c2 c3 c4 Octagon of the port was about 30 ph [6]. Capacitance was calculated by Eq. (3), and ε is dielectric permittivity of dielectric material, d is the distance between pattern and ground, and A is the area of pattern. In calculation results, the capacitance between patterns was about 2.17 ff and the capacitance between pattern and ground was about 30 ff.

4 538 JONGSUK LEE et al : A DESIGN OF 8.5 GHZ META-VCO BASED-ON META-MATERIAL USING 65 NM PROCESS Fig. 6. Simulation result of the resonant frequency of the proposed meta-structure. Fig. 7. Simulation result of the META-VCO with varactor. A C = e (3) d From the calculation results, the resonant frequency of the modeled meta-structure was about 54 GHz, and simulation result is shown in Fig. 6. It was confirmed that 3-D simulation result and calculation result of the modeling has similar result. So the resonant frequency of the meta-structure was verified. Fig. 8. PEX simulation result of the MET-VCO. 2. Meta-VCO Implementation The proposed META-VCO was verified by CADENCE Spectre RF. The oscillation frequency of the META-VCO is confirmed by importing S-parameter of the meta-structure to resonant part. Because the parasitic capacitance of NMOS and output buffer was added, the oscillation frequency of the META-VCO was lower than self-resonant frequency of meta-structure. Because of the needs to add the varactor for frequency tuning, the oscillation frequency goes down. In the first case, the META-VCO without varactor confirmed the oscillation frequency of GHz. In the second case of adding varactor, the oscillation frequency was 17.8 to GHz and it is shown in Fig. 7. But the previous results does not considered the parasitic components from layout, so the third case was simulated using PEX (Parasitic Extraction) result. In simulation, the META-VCO was operated from 9.05 to 9.12 GHz and it is shown in Fig. 8. From several simulation results, PEX result shows more practical value than when only meta-structure is used for simulation. Fig. 9. Phase noise simulation result of the META-VCO. Fig. 9 is a simulation result of phase noise of META- VCO. In simulation result, good phase noise characteristic was confirmed with dbc/hz and dbc/hz at 1 MHz and 10 MHz offset frequency respectively. IV. EXPERIMENTAL RESULTS The proposed META-VCO was implemented using 65 nm process and the area is mm 2 as

5 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.5, OCTOBER, 2016 Fig. 10. META-VCO chip microphotograph. 539 Fig. 12. Measured frequency tuning range of the META-VCO versus VCTRL. Fig. 13. Measured phase noise of META-VCO. Fig. 11. Measured output frequency at VCTRL=0-V, VCTRL=1.2-V. shown in Fig. 10. In the measurement, on-wafer probing was carried out using the probe station, N9010A spectrum analyzer, and dual power supply. The GSSG Infinity probe could measure the output of the META-VCO, while GSSG means ground-signal-signal-ground. VDDA and VDDB are 1.2-V and it was confirmed that the output frequency was varying according to VCTRL. Fig. 11 shows the output frequency and the output power when VCTRL were 0-V and 1.2-V. We compensated the losses of the cable and probe in the measurement environment, and the compensated output powers were dbm and dbm at 8.45 GHz and 8.77 GHz respectively. Fig. 12 shows the measured frequency tuning range and the META-VCO operated from 8.45 to 8.77 GHz. The maximum KVCO according to VCTRL was 0.27 GHz/V. The reason that META-VCO has narrow tuning range is capacitance of LC resonator of meta-structure is not change. We added a couple of varactor which can change the operating range by VCTRL to solve this problem. If varactor with a big value is used to wide tuning range, the another problem that oscillation frequency is lower is occur. So varactor with a small value was used and META-VCO had smaller operating range than previous works [8, 9]. But META-VCO had advantage of good phase noise characteristic. The measured phase noises were low and dbc/hz, dbc/hz, and dbc/hz at 100 khz, 1 MHz, and 10 MHz respectively as shown in Fig. 13. The power consumption of the META-VCO was 28 mw.

6 540 JONGSUK LEE et al : A DESIGN OF 8.5 GHZ META-VCO BASED-ON META-MATERIAL USING 65 NM PROCESS Table 2. Performance summary and comparisons Process [8]ICECS nm The proposed META-VCO was compared to other works to verify its performance by using measured values. Following FOM equation was used for the evaluation and is defined in Eq. (3) [7]. { } [9]PRIME nm [10]ICCRD nm This work 65 nm Type LC LC Waveguide META Operating Frequency [GHz] Phase noise [dbc/hz] Output power [dbm] 5~ ~ ~ @1 MHz -90@1 MHz -94.8@1 MHz -67.8@100 khz @1 MHz @10 MHz PDC [mw] *28 FOM [dbc/hz] Supply [V] Area [mm 2 ] N/A 0.25 *Power consumption of VCO and output buffer æ f0 ö æ PDC ö FOM = L Δf - 20log ç + 10log Δf ç 1mW è ø è ø L{Δf} is the phase noise, Δf is the offset frequency, f 0 is the oscillation frequency, and P DC is the power consumption of the VCO. Smaller FOM means the better performance of the VCO and the FOM of the designed META-VCO is about dbc/hz and very low. Table 1 summarizes the performance comparison between the proposed work and recently reported works, and we confirmed the good phase noise performance. So, the proposed META-VCO using meta-structure has an advantage in phase noise performance. The proposed VCO shows superior phase noise performance compared with existing VCO s for low phase noise application at similar operating frequency [8-10]. Table 2 summarizes the performance comparison between the proposed work and recently reported works. The proposed META-VCO was confirmed that better phase noise characteristics than the conventional waveguide type as well as LC type. The reason that FOM is poor is because FOM was calculated by power consumption including buffer. (3) V. CONCLUSIONS The low phase noise VCO using 65nm process with meta-structure was designed in this work. In this research, the proposed META-VCO was found to be feasible for applications in millimeter wave data transfer systems and so on. The meta-structure was analyzed by HFSS and the META-VCO was simulated by CADENCE Spectre RF. We verified the META-VCO with five flows, and the final simulation results showed the META-VCO operated at 9.05~9.12 GHz. In measurement results, the META- VCO operated 8.45~8.77 GHz according to V CTRL. The difference between simulation and measurement result was less than 5.4%. The output power of the META- VCO was dbm with the compensated measurement values. The phase noises were dbc/hz, dbc/hz, and dbc/hz at 100 khz, 1 MHz, and 10 MHz offset frequency respectively. The power consumption was 28 mw with 1.2-V supply voltage. In this work, we showed the feasibility that metastructure could be applied to process by the chip implementation and method. VCO is the one of the most important block of the frequency synthesizer [3-5, 8, 9], so the proposed META-VCO could be applied to digital system core clock generator and communication system which needs several GHz frequencies. CAD tool and MPW were supported by IDEC in this work. ACKNOWLEDGMENTS This work was supported by the Human Resources Development program(no ) of the Korea Institute of Energy Technology Evaluation and Planning(KETEP) grant funded by the Korea government Ministry of Trade, Industry and Energy and the MSIP(Ministry of Science, ICT and Future Planning), Korea, under the ITRC(Information Technology Research Center) support program (IITP-2016-H ) supervised by the IITP(Institute for Information & communications Technology Promotion)

7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.5, OCTOBER, REFERENCES [1] Choi Jaewon and Seo Chulhun, Low Phase Noise Push-Push VCO using Microstrip Square Open Loop Multiple Split Ring Resonator and Rat Race Coupler, IEEE, Asia-Pacific Microwave Conference (APMC), pp , Dec [2] J. Choi, and C. Seo, Low Phase Noise VCO using Metamaterial Transmission Line Based on Complementary Spiral Resonator and Interdigital Structure, Journal of The Institute of Electronics Engineers of Korea -Telecommunications, Vol. 48, no. 2, pp , Feb [3] Xuefan Jin, Jun-Han Bae, Jung-Hoon Chun, Jintae Kim, and Kee-Won Kwon, A 1.25 GHz Low Power Multi-phase PLL Using Phase Interpolation between Two Complementary Clocks, IEEE, J. Semiconductor Technology and Science (JSTS), pp , Vol.15, No.6, Dec [4] Sanquan Song, Byungsub Kim, and Wei Xiong, The Oscillation Frequency of CML-based Multipath Ring Oscillators, IEEE, J. Semiconductor Technology and Science (JSTS), pp , Vol.15, No.6, Dec [5] Jin-Wook Choi, Seung-Won Choi, InSeong Kim, DongSoo Lee, HyungGu Park, YoungGun Pu, Kang-Yoon Lee, A Class-C Type Wideband Current-Reused VCO With Two-Step Automatic Amplitude Calibration Loop, IEEE, J. Semiconductor Technology and Science (JSTS), pp , Vol.15, No.5, Oct [6] Thomas. H. Lee, The Design of Radio- Frequency Integrated Circuits, CAMBRIDGE, U.k. : CAMBRIDGE Univ. Press, pp.136, [7] Taemin Kim, Jihoon Son, Hae-ddeul Kim, and Hyunchol Shin, A Two-Point Tuning LC VCO with Minimum Variation of KVCO2 for Quad- Band GSM/GPRS/EDGE Polar Transmitter in 65- nm, IEEE, International SoC design Conference (ISOCC), IEEE, pp , Nov [8] J. Dang, A. Noculak, S. Haddadinejad, C. Jungemann, and B. Meinerzhagen, A fully integrated 5.5 GHz cross-coupled VCO with high output power using 0.25μm technology, IEEE, International Conference on Electronics Circuits Systems (ICECS), pp , Dec [9] Shaahin Haddadinejad, Achim Noculak, Michael Hinz, and Bernd Meinerzhagen, A Low Power, Small Area, Fully Integrated 5.5GHz LC- VCO, IEEE, Ph.D. Research In Microelectronics and Electronics (PRIME), pp.1-4, Jun [10] Long Huang, Shengyue Yuan, Runxi Zhang, and Wei Li, A 15 GHz Low Phase Noise VCO Using Coupled Coplanar Waveguide, IEEE, International Conference on Computer Research and Development (ICCRD), Vol.3, pp , Mar Jongsuk Lee was born in Seoul, Korea, in He received the B.S. degree in the School of Electronic Engineering from Soongsil University, Korea, in He is currently pursuing the Ph.D. degree in the Department of Electronic Engineering from Soongsil University. His research interests include analog PLL and all digital PLL. Yong Moon received the B.S., M.S., and Ph.D. degrees from Electronics Engineering, Seoul National University, Seoul, Korea, in 1990, 1992 and 1997, respectively. From 1997 to 1999, he was with LG Semicon co., Ltd., where he contributed to senior research engineer. Since 1999, he has been with Soongsil University, Seoul, Korea, where he is a professor with School of Electronic Engineering. His research interests include PLL, low-power circuit, mixed signal IC and RF circuits.