Di/dt Mitigation Method in Power Delivery Design & Analysis

Size: px
Start display at page:

Download "Di/dt Mitigation Method in Power Delivery Design & Analysis"

Transcription

1 Di/dt Mitigation Method in Power Delivery Design & Analysis Delino Julius Thao Pham Fattouh Farag DAC 2009, San Francisco July 27, 2009

2 Outlines Introduction Background di/dt Mitigation Modeling di/dt Mitigation Simulation Results Bench Measurements Conclusion 2

3 Abbreviations DVD Dynamic Voltage Drop EA Early Analysis Cdie, Rdie Effective pad to- pad die Cap & Res Icc(t) Equivalent Dynamic Die Current PD Power Delivery PDN Power Delivery Network PI Power Integrity VCD Value-Change-Dump (Vector-based) VLS Vectorless WC Worst Case 3

4 Introduction Extended On-Die VLS PI analysis for PD di/dt mitigation Developed Extended On-Die dynamic VLS PI simulation flow to enable PD analysis to mitigate di/dt issues Using Early Analysis method, enables the PD designers to influence architectural or micro-architectural direction/choices to improve system-level robustness and performance On-die noise can impact system-level voltage margin Mitigation concepts and techniques for di/dt can reduce ondie noise Result: improved system-level voltage margins 4

5 Background: Problem Statement Worst-case (WC) power delivery (PD) noise is not necessarily the result of high-power ops. High-power ops (i.e.., virus-like behavior) results in high % of cell activity for long duration of time WC power delivery noise results from events that occur on the time-scale of Power Delivery Network (PDN) resonance Examples: SCAN, power management (gating), performance or operating mode changes (hi<->low or change frequency of operation) Influencing architectural or micro-architectural design choices requires tools that architects find credible and flexible to use (represent arch performance at the proper level of abstraction with the what-if analysis capabilities) 5

6 Design info. Background: Stages for PD-EA --- Concept/VLS to design/vcd Engineering estimates of model Extracted models from layout VLS database available VCD vectors available We have implemented PD-EA Power Delivery Early Analysis, a way to use tools intended primarily for post-layout at early stages in the design cycle while limited design collaterals available Specific di/dt vectors are generally not available for PD designers until later stage of the design cycle Design collaterals and specific vectors (VCD) may not be compatible at early stages of the design. VLS based analysis can be made to closely represent the global conditions for the VCD-based when given the proper system level parameters (e.g. power, clocking schemes and refined partition level -floorplan- distribution) Time 6

7 di/dt Mitigation concept Sharp di/dt is a risk event associated with fast current transients. di/dt mitigation is a design concept to reduce the sharpness and the impact of those fast current transients Causes and ways to mitigate di/dt issue Clock gating & ungating Power gating & ungating Staggering logic activities So, di/dt mitigation is modifying the events and sequences, to lower the di/dt thus reducing the DVD (dynamic voltage drop) Di/dt mitigation concept Original Power event without di/dt mitigation enabled With di/dt mitigation 7

8 Modeling di/dt Mitigation method Extension of dynamic vectorless, allow the users to specify different power at different stages Default VLS assumes a constant power for clock-clock power analysis Enhanced VLS approach enable scaling power per time region to implement di/dt mitigation concepts at the PDN time scale. Beside the on-die clock-clock operation, the focus is on the Power Delivery larger time scale events (e.g. micro seconds scale for low and mid-frequency operations) Simple input text (or TCL) format allows the users to control: initial, final power and transition time Simple text file input to specify the power profile Clock cycle Power (W) Icc(t) or Power with default VLS with constant power Icc(t)/Power with di/dt mitigation feature enabled 8

9 Usage Flow Layout, Libraries, Package/Board models Power / activity target #1 Power / activity target #2 Power / activity target #n Duration of Duration of Duration of mode mode mode Combined scenario Total duration ~ sum of all mode durations Time domain, multi-cycle analysis 9

10 Simulation Results This is an example of a large clock-clock di/dt (when pico-second time scale current variation is large compared to the nano-second current variation) applied di/dt mitigation method BEFORE: default vectorless Icc(t) with constant average power which can not reflect w/c DVD condition for some power management schemes BEFORE: DVD of the typical package and board PDN when excited by default vectorless Icc(t) AFTER: Icc(t) in the enhanced dynamic vectorless mode to present an example of power management scheme AFTER: DVD in the enhanced dynamic vectorless Icc(t) to reflect power management schemes Top) Supply current Icc(t) in default VLS mode with constant average power not reflecting w/c DVD Dynamic voltage droop (DVD) of the typical package and board PDN when (Bottom) Supply current Icc(t) in Dynamic VLS enhanced Di-Dt Mitigation Method in Power Delivery Design & excited Analysis by large time-scale current variation Icc(t) mode with power variation in larger time scale in certain power management scheme (Top) DVD stimulated by Icc(t) in default VLS mode with constant average power (peak to peak DVD is 48mV) which does not reflect the w/c DVD (Bottom) with di/dt mitigation mode, DVD shows significant larger noise

11 Simulation Results This is an example of small clock-clock scale di/dt (when pico-second time scale current variation is small compared to the nano-second current variation) while applying di/dt mitigation BEFORE: default vectorless Icc(t) with constant average power which can not reflect w/c DVD condition for some power management schemes BEFORE: DVD of the typical package and board PDN when excited by default vectorless Icc(t) AFTER: Icc(t) in the enhanced dynamic vectorless mode to present an example of power management scheme AFTER: DVD in the enhanced dynami vectorless Icc(t) to reflect power management schemes Enhance VSL mode to control power magnitude and slew rates in power management scenarios Worst case DVD in enhanced VSL reflecting different slew rate, power magnitudes 11

12 Simulation Results This is an example of a di/dt mitigation Large scale clock-clock di/dt Di/dt mitigation feature enables the analysis of different Power Architecture changes. Different Power Architecture modes would provide different power transitions resulting in different dynamic voltage drop impacts Dynamic voltage droop impact due to different Power Architecture changes. Dynamic VLS enables the analysis of the DVD impacts of such Power Architecture changes. 12

13 Bench Measurements of di/dt mitigation On-die measurements shows the impact of di/dt mitigation enabled design (significant reduction of on-die P-P noise) di/dt mitigation DISABLED on-die noise mvpp di/dt mitigation ENABLED on-die noise mvpp Silicon measurements show that di/dt mitigation improves the dynamic voltage droop significantly 13

14 Bench measurement of di/dt mitigation --2 On-die measurement with di/dt mitigation DISABLED (Zoom-in) Zoom-in view of dynamic voltage drop without di/dt mitigation 9.8ns 9.8ns 284.4mVpp 258.0mVpp 933MHz Dynamic voltage 1 st droop follows PDN resonant frequency of ~ 100Mhz (9.8nS) 33.5ns Similarly, dynamic voltage 1 st bounce follows PDN resonant frequency of ~ 100Mhz (9.8nS) 14

15 Bench measurement data of di/dt mitigation On-die measurement with di/dt mitigation ENABLED (Zoom-in) Zoom-in view of dynamic voltage drop with di/dt mitigation impact 933MHz 201mVpp 15 di/dt mitigation reduces the dynamic voltage 1 st droop/bounce.

16 Conclusion In enabling a power delivery design & analysis flow from pre-layout to post-layout, we found a need for a full-chip simulation that would have sufficient credibility to enable architectural what-if analysis and changes. In pre-layout phase, we use Vectorless PI-EA (Power Integrity Early Analysis). In post-layout phase, we use vector-driven VCD-based dynamic simulations. Between these two phases, dynamic vectorless is applied and we have enhanced this dynamic vectorless to simulate di/dt mitigation to meet the PDN needs. di/dt mitigation can effectively reduce on-die noise caused, for example, by clock gating, power gating and abrupt changes in activity. In future work we intend to combine this capability with timing or frequency impact so that accurate cost-benefit analysis can be associated with proposed architectural changes. 16

Chip Package - PC Board Co-Design: Applying a Chip Power Model in System Power Integrity Analysis

Chip Package - PC Board Co-Design: Applying a Chip Power Model in System Power Integrity Analysis Chip Package - PC Board Co-Design: Applying a Chip Power Model in System Power Integrity Analysis Authors: Rick Brooks, Cisco, ricbrook@cisco.com Jane Lim, Cisco, honglim@cisco.com Udupi Harisharan, Cisco,

More information

CIRCUITS. Raj Nair Donald Bennett PRENTICE HALL

CIRCUITS. Raj Nair Donald Bennett PRENTICE HALL POWER INTEGRITY ANALYSIS AND MANAGEMENT I CIRCUITS Raj Nair Donald Bennett PRENTICE HALL Upper Saddle River, NJ Boston Indianapolis San Francisco New York Toronto Montreal London Munich Paris Madrid Capetown

More information

Vishram S. Pandit, Intel Corporation (916) ]

Vishram S. Pandit, Intel Corporation (916) ] DesignCon 2008 Simulation and Characterization of GHz On-Chip Power Delivery Network (PDN) Vishram S. Pandit, Intel Corporation [vishram.s.pandit@intel.com, (916)356-2059] Woong Hwan Ryu, Intel Corporation

More information

Engineering the Power Delivery Network

Engineering the Power Delivery Network C HAPTER 1 Engineering the Power Delivery Network 1.1 What Is the Power Delivery Network (PDN) and Why Should I Care? The power delivery network consists of all the interconnects in the power supply path

More information

SUBSTRATE NOISE FULL-CHIP LEVEL ANALYSIS FLOW FROM EARLY DESIGN STAGES TILL TAPEOUT. Hagay Guterman, CSR Jerome Toublanc, Ansys

SUBSTRATE NOISE FULL-CHIP LEVEL ANALYSIS FLOW FROM EARLY DESIGN STAGES TILL TAPEOUT. Hagay Guterman, CSR Jerome Toublanc, Ansys SUBSTRATE NOISE FULL-CHIP LEVEL ANALYSIS FLOW FROM EARLY DESIGN STAGES TILL TAPEOUT Hagay Guterman, CSR Jerome Toublanc, Ansys Speakers Hagay Guterman, CSR Hagay Guterman is a senior signal and power integrity

More information

Wideband On-die Power Supply Decoupling in High Performance DRAM

Wideband On-die Power Supply Decoupling in High Performance DRAM Wideband On-die Power Supply Decoupling in High Performance DRAM Timothy M. Hollis, Senior Member of the Technical Staff Abstract: An on-die decoupling scheme, enabled by memory array cell technology,

More information

Simulation and Measurement of an On-Die Power-Gated Power Delivery System

Simulation and Measurement of an On-Die Power-Gated Power Delivery System DesignCon 2010 Simulation and Measurement of an On-Die Power-Gated Power Delivery System Jimmy Huang, Intel [jimmy.huat.since.huang@intel.com, (+604)-2532385] Tan Fern Nee, Intel [fern.nee.tan@intel.com,

More information

Broadband Methodology for Power Distribution System Analysis of Chip, Package and Board for High Speed IO Design

Broadband Methodology for Power Distribution System Analysis of Chip, Package and Board for High Speed IO Design DesignCon 2009 Broadband Methodology for Power Distribution System Analysis of Chip, Package and Board for High Speed IO Design Hsing-Chou Hsu, VIA Technologies jimmyhsu@via.com.tw Jack Lin, Sigrity Inc.

More information

SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity

SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity DESIGNCON 2009 SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity Vishram S. Pandit, Intel Corporation [vishram.s.pandit@intel.com, (916)356-2059] Ashish N. Pardiwala, Intel Corporation

More information

Myoung Joon Choi, Vishram S. Pandit Intel Corp.

Myoung Joon Choi, Vishram S. Pandit Intel Corp. Myoung Joon Choi, Vishram S. Pandit Intel Corp. IBIS Summit at DesignCon 2010 Acknowledgements: Woong Hwan Ryu, Joe Salmon Copyright 2010, Intel Corporation. All rights reserved. Need for SI/PI Co-analysis

More information

Target Impedance and Rogue Waves

Target Impedance and Rogue Waves TITLE Target Impedance and Rogue Waves Larry Smith (Qualcomm) Image Target Impedance and Rogue Waves Larry Smith (Qualcomm) Larry Smith Principal Power Integrity Engineer, Qualcomm Larrys@qti.qualcomm.com

More information

ΕΠΛ 605: Προχωρημένη Αρχιτεκτονική

ΕΠΛ 605: Προχωρημένη Αρχιτεκτονική ΕΠΛ 605: Προχωρημένη Αρχιτεκτονική Υπολογιστών Presentation of UniServer Horizon 2020 European project findings: X-Gene server chips, voltage-noise characterization, high-bandwidth voltage measurements,

More information

Relationship Between Signal Integrity and EMC

Relationship Between Signal Integrity and EMC Relationship Between Signal Integrity and EMC Presented by Hasnain Syed Solectron USA, Inc. RTP, North Carolina Email: HasnainSyed@solectron.com 06/05/2007 Hasnain Syed 1 What is Signal Integrity (SI)?

More information

PDS Impact for DDR Low Cost Design

PDS Impact for DDR Low Cost Design PDS Impact for DDR3-1600 Low Cost Design Jack W.C. Lin Sr. AE Manager jackl@cadence.com Aug. g 13 2013 Cadence, OrCAD, Allegro, Sigrity and the Cadence logo are trademarks of Cadence Design Systems, Inc.

More information

Effect of Aging on Power Integrity of Digital Integrated Circuits

Effect of Aging on Power Integrity of Digital Integrated Circuits Effect of Aging on Power Integrity of Digital Integrated Circuits A. Boyer, S. Ben Dhia Alexandre.boyer@laas.fr Sonia.bendhia@laas.fr 1 May 14 th, 2013 Introduction and context Long time operation Harsh

More information

Thank you for downloading one of our ANSYS whitepapers we hope you enjoy it.

Thank you for downloading one of our ANSYS whitepapers we hope you enjoy it. Thank you! Thank you for downloading one of our ANSYS whitepapers we hope you enjoy it. Have questions? Need more information? Please don t hesitate to contact us! We have plenty more where this came from.

More information

Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids

Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids Woo Hyung Lee Sanjay Pant David Blaauw Department of Electrical Engineering and Computer Science {leewh, spant, blaauw}@umich.edu

More information

A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping

A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping Jie Gu, Hanyong Eom and Chris H. Kim Department of Electrical and Computer Engineering University of Minnesota, Minneapolis

More information

Basic Concepts C HAPTER 1

Basic Concepts C HAPTER 1 C HAPTER 1 Basic Concepts Power delivery is a major challenge in present-day systems. This challenge is expected to increase in the next decade as systems become smaller and new materials are introduced

More information

Microcontroller Systems. ELET 3232 Topic 13: Load Analysis

Microcontroller Systems. ELET 3232 Topic 13: Load Analysis Microcontroller Systems ELET 3232 Topic 13: Load Analysis 1 Objective To understand hardware constraints on embedded systems Define: Noise Margins Load Currents and Fanout Capacitive Loads Transmission

More information

UNIT-III POWER ESTIMATION AND ANALYSIS

UNIT-III POWER ESTIMATION AND ANALYSIS UNIT-III POWER ESTIMATION AND ANALYSIS In VLSI design implementation simulation software operating at various levels of design abstraction. In general simulation at a lower-level design abstraction offers

More information

MEMS Timing Technology: Shattering the Constraints of Quartz Timing to Improve Smartphones and Mobile Devices

MEMS Timing Technology: Shattering the Constraints of Quartz Timing to Improve Smartphones and Mobile Devices MEMS Timing Technology: Shattering the Constraints of Quartz Timing to The trends toward smaller size and increased functionality continue to dominate in the mobile electronics market. As OEMs and ODMs

More information

Digital Systems Power, Speed and Packages II CMPE 650

Digital Systems Power, Speed and Packages II CMPE 650 Speed VLSI focuses on propagation delay, in contrast to digital systems design which focuses on switching time: A B A B rise time propagation delay Faster switching times introduce problems independent

More information

An Initial Case Study for BIRD95: Enhancing IBIS for SSO Power Integrity Simulation

An Initial Case Study for BIRD95: Enhancing IBIS for SSO Power Integrity Simulation An Initial Case Study for BIRD95: Enhancing IBIS for SSO Power Integrity Simulation Also presented at the January 31, 2005 IBIS Summit SIGRITY, INC. Sam Chitwood Raymond Y. Chen Jiayuan Fang March 2005

More information

This chapter discusses the design issues related to the CDR architectures. The

This chapter discusses the design issues related to the CDR architectures. The Chapter 2 Clock and Data Recovery Architectures 2.1 Principle of Operation This chapter discusses the design issues related to the CDR architectures. The bang-bang CDR architectures have recently found

More information

Debouncing Switches. The non-ideal behavior of the contacts that creates multiple electrical transitions for a single user input.

Debouncing Switches. The non-ideal behavior of the contacts that creates multiple electrical transitions for a single user input. Mechanical switches are one of the most common interfaces to a uc. Switch inputs are asynchronous to the uc and are not electrically clean. Asynchronous inputs can be handled with a synchronizer (2 FF

More information

Active and Passive Techniques for Noise Sensitive Circuits in Integrated Voltage Regulator based Microprocessor Power Delivery

Active and Passive Techniques for Noise Sensitive Circuits in Integrated Voltage Regulator based Microprocessor Power Delivery Active and Passive Techniques for Noise Sensitive Circuits in Integrated Voltage Regulator based Microprocessor Power Delivery Amit K. Jain, Sameer Shekhar, Yan Z. Li Client Computing Group, Intel Corporation

More information

DesignCon On-Chip Power Supply Noise and Reliability Analysis for Multi-Gigabit I/O Interfaces

DesignCon On-Chip Power Supply Noise and Reliability Analysis for Multi-Gigabit I/O Interfaces DesignCon 2010 On-Chip Power Supply Noise and Reliability Analysis for Multi-Gigabit I/O Interfaces Ralf Schmitt, Rambus Inc. [Email: rschmitt@rambus.com] Hai Lan, Rambus Inc. Ling Yang, Rambus Inc. Abstract

More information

A Survey of the Low Power Design Techniques at the Circuit Level

A Survey of the Low Power Design Techniques at the Circuit Level A Survey of the Low Power Design Techniques at the Circuit Level Hari Krishna B Assistant Professor, Department of Electronics and Communication Engineering, Vagdevi Engineering College, Warangal, India

More information

A 4 µa-quiescent-current Dual- Mode Digitally-Controlled Buck Converter IC for Cellular Phone Applications

A 4 µa-quiescent-current Dual- Mode Digitally-Controlled Buck Converter IC for Cellular Phone Applications A 4 µa-quiescent-current Dual- Mode Digitally-Controlled Buck Converter IC for Cellular Phone Applications Jinwen Xiao Angel Peterchev Jianhui Zhang Prof. Seth Sanders Power Electronics Group Dept. of

More information

Dynamic Threshold for Advanced CMOS Logic

Dynamic Threshold for Advanced CMOS Logic AN-680 Fairchild Semiconductor Application Note February 1990 Revised June 2001 Dynamic Threshold for Advanced CMOS Logic Introduction Most users of digital logic are quite familiar with the threshold

More information

Low power SERDES transceiver for supply-induced jitter sensitivity methodology analysis

Low power SERDES transceiver for supply-induced jitter sensitivity methodology analysis Low power SERDES transceiver for supply-induced jitter sensitivity methodology analysis Micro Chang htc Michael_Chang@hTC.com Jan 9, 2019 X 1 Agenda Jitter-aware target impedance of power delivery network

More information

Design of the Power Delivery System for Next Generation Gigahertz Packages

Design of the Power Delivery System for Next Generation Gigahertz Packages Design of the Power Delivery System for Next Generation Gigahertz Packages Madhavan Swaminathan Professor School of Electrical and Computer Engg. Packaging Research Center madhavan.swaminathan@ece.gatech.edu

More information

ASICs Concept to Product

ASICs Concept to Product ASICs Concept to Product Synopsis This course is aimed to provide an opportunity for the participant to acquire comprehensive technical and business insight into the ASIC world. As most of these aspects

More information

How to Design an R g Resistor for a Vishay Trench PT IGBT

How to Design an R g Resistor for a Vishay Trench PT IGBT VISHAY SEMICONDUCTORS www.vishay.com Rectifiers By Carmelo Sanfilippo and Filippo Crudelini INTRODUCTION In low-switching-frequency applications like DC/AC stages for TIG welding equipment, the slow leg

More information

Using IBIS Models for Timing Analysis

Using IBIS Models for Timing Analysis Application Report SPRA839A - April 2003 Using IBIS Models for Timing Analysis ABSTRACT C6000 Hardware Applications Today s high-speed interfaces require strict timings and accurate system design. To achieve

More information

AN EFFICIENT APPROACH TO MINIMIZE POWER AND AREA IN CARRY SELECT ADDER USING BINARY TO EXCESS ONE CONVERTER

AN EFFICIENT APPROACH TO MINIMIZE POWER AND AREA IN CARRY SELECT ADDER USING BINARY TO EXCESS ONE CONVERTER AN EFFICIENT APPROACH TO MINIMIZE POWER AND AREA IN CARRY SELECT ADDER USING BINARY TO EXCESS ONE CONVERTER K. RAMAMOORTHY 1 T. CHELLADURAI 2 V. MANIKANDAN 3 1 Department of Electronics and Communication

More information

High and Low Speed Output Buffer Design with Reduced Switching Noise for USB Applications

High and Low Speed Output Buffer Design with Reduced Switching Noise for USB Applications High and Low Speed Output Buffer Design with Reduced Switching Noise for USB Applications HWANG-CHERNG CHOW, C. HUANG and HSING-CHUNG LIANG Department of Electronics Engineering, Chang Gung University

More information

CAPLESS REGULATORS DEALING WITH LOAD TRANSIENT

CAPLESS REGULATORS DEALING WITH LOAD TRANSIENT CAPLESS REGULATORS DEALING WITH LOAD TRANSIENT 1. Introduction In the promising market of the Internet of Things (IoT), System-on-Chips (SoCs) are facing complexity challenges and stringent integration

More information

RTH GHz Bandwidth High Linearity Track-and-Hold REV-DATE PA FILE DS_0162PA2-3215

RTH GHz Bandwidth High Linearity Track-and-Hold REV-DATE PA FILE DS_0162PA2-3215 RTH090 25 GHz Bandwidth High Linearity Track-and-Hold REV-DATE PA2-3215 FILE DS RTH090 25 GHz Bandwidth High Linearity Track-and-Hold Features 25 GHz Input Bandwidth Better than -40dBc THD Over the Total

More information

Low Power Design Methods: Design Flows and Kits

Low Power Design Methods: Design Flows and Kits JOINT ADVANCED STUDENT SCHOOL 2011, Moscow Low Power Design Methods: Design Flows and Kits Reported by Shushanik Karapetyan Synopsys Armenia Educational Department State Engineering University of Armenia

More information

SSTVN bit 1:2 SSTL_2 registered buffer for DDR

SSTVN bit 1:2 SSTL_2 registered buffer for DDR INTEGRATED CIRCUITS 2004 Jul 15 Philips Semiconductors FEATURES Stub-series terminated logic for 2.5 V V DD (SSTL_2) Designed for PC1600 PC2700 (at 2.5 V) and PC3200 (at 2.6 V) applications Pin and function

More information

SSTV V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

SSTV V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM INTEGRATED CIRCUITS 2000 Dec 01 File under Integrated Circuits ICL03 2002 Feb 19 FEATURES Stub-series terminated logic for 2.5 V (SSTL_2) Optimized for stacked DDR (Double Data Rate) SDRAM applications

More information

An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks

An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks Sanjay Pant, David Blaauw University of Michigan, Ann Arbor, MI Abstract The placement of on-die decoupling

More information

Supplementary Figures

Supplementary Figures Supplementary Figures Supplementary Figure 1. The schematic of the perceptron. Here m is the index of a pixel of an input pattern and can be defined from 1 to 320, j represents the number of the output

More information

Geared Oscillator Project Final Design Review. Nick Edwards Richard Wright

Geared Oscillator Project Final Design Review. Nick Edwards Richard Wright Geared Oscillator Project Final Design Review Nick Edwards Richard Wright This paper outlines the implementation and results of a variable-rate oscillating clock supply. The circuit is designed using a

More information

Transient Load Tester for Time Domain PDN Analysis. Ethan Koether (Oracle) Istvan Novak (Oracle)

Transient Load Tester for Time Domain PDN Analysis. Ethan Koether (Oracle) Istvan Novak (Oracle) Transient Load Tester for Time Domain PDN Analysis Ethan Koether (Oracle) Istvan Novak (Oracle) Speakers Ethan Koether Hardware Engineer, Oracle ethan.koether@oracle.com He is currently focusing on system

More information

Foundry WLSI Technology for Power Management System Integration

Foundry WLSI Technology for Power Management System Integration 1 Foundry WLSI Technology for Power Management System Integration Chuei-Tang Wang, Chih-Lin Chen, Jeng-Shien Hsieh, Victor C.Y. Chang, Douglas Yu R&D,TSMC Oct. 2016 2 Motivation Outline PMIC system integration

More information

Performance Improvement by System Aware Substrate Noise Analysis for Mixed-signal IC

Performance Improvement by System Aware Substrate Noise Analysis for Mixed-signal IC DesignCon 2017 Performance Improvement by System Aware Substrate Noise Analysis for Mixed-signal IC Kwangseok Choi, Samsung Electronics Inc. [aquarian505@gmail.com] Byunghyun Lee, Samsung Electronics Inc.

More information

High Speed Design Issues and Jitter Estimation Techniques. Jai Narayan Tripathi

High Speed Design Issues and Jitter Estimation Techniques. Jai Narayan Tripathi High Speed Design Issues and Jitter Estimation Techniques Jai Narayan Tripathi (jainarayan.tripathi@st.com) Outline Part 1 High-speed Design Issues Signal Integrity Power Integrity Jitter Power Delivery

More information

04/29/03 EE371 Power Delivery D. Ayers 1. VLSI Power Delivery. David Ayers

04/29/03 EE371 Power Delivery D. Ayers 1. VLSI Power Delivery. David Ayers 04/29/03 EE371 Power Delivery D. Ayers 1 VLSI Power Delivery David Ayers 04/29/03 EE371 Power Delivery D. Ayers 2 Outline Die power delivery Die power goals Typical processor power grid Transistor power

More information

On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital VLSI

On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital VLSI ELEN 689 606 Techniques for Layout Synthesis and Simulation in EDA Project Report On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital

More information

Hello, and welcome to the Texas Instruments Precision overview of AC specifications for Precision DACs. In this presentation we will briefly cover

Hello, and welcome to the Texas Instruments Precision overview of AC specifications for Precision DACs. In this presentation we will briefly cover Hello, and welcome to the Texas Instruments Precision overview of AC specifications for Precision DACs. In this presentation we will briefly cover the three most important AC specifications of DACs: settling

More information

SY55859L. General Description. Features. Applications. 3.3V, 3.2Gbps Dual 2X2 Crosspoint Switch

SY55859L. General Description. Features. Applications. 3.3V, 3.2Gbps Dual 2X2 Crosspoint Switch 3.3V, 3.2Gbps Dual 2X2 Crosspoint Switch General Description The is a dual CML 2x2 crosspoint switch optimized for high-speed data and/or clock applications (up to 3.2Gbps or 2.7GHz) where low jitter and

More information

USE GAL DEVICES FOR NEW DESIGNS

USE GAL DEVICES FOR NEW DESIGNS PALLV22V PALLV22VZ COM'L: -7//5 IND: -5 IND: -25 PALLV22V and PALLV22VZ Families Low-Voltage (Zero Power) 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS Low-voltage operation, 3.3 V JEDEC

More information

MDLL & Slave Delay Line performance analysis using novel delay modeling

MDLL & Slave Delay Line performance analysis using novel delay modeling MDLL & Slave Delay Line performance analysis using novel delay modeling Abhijith Kashyap, Avinash S and Kalpesh Shah Backplane IP division, Texas Instruments, Bangalore, India E-mail : abhijith.r.kashyap@ti.com

More information

Chapter 10: Compensation of Power Transmission Systems

Chapter 10: Compensation of Power Transmission Systems Chapter 10: Compensation of Power Transmission Systems Introduction The two major problems that the modern power systems are facing are voltage and angle stabilities. There are various approaches to overcome

More information

How to Design a PDN for Worst Case?

How to Design a PDN for Worst Case? PCB Design 007 QuietPower columns How to Design a PDN for Worst Case? Istvan Novak, Oracle, December 205 In the previous column [] we showed that for Linear and Time Invariant (LTI) systems the Reverse

More information

3D IC-Package-Board Co-analysis using 3D EM Simulation for Mobile Applications

3D IC-Package-Board Co-analysis using 3D EM Simulation for Mobile Applications 3D IC-Package-Board Co-analysis using 3D EM Simulation for Mobile Applications Darryl Kostka, CST of America Taigon Song and Sung Kyu Lim, Georgia Institute of Technology Outline Introduction TSV Array

More information

High Speed Digital Systems Require Advanced Probing Techniques for Logic Analyzer Debug

High Speed Digital Systems Require Advanced Probing Techniques for Logic Analyzer Debug JEDEX 2003 Memory Futures (Track 2) High Speed Digital Systems Require Advanced Probing Techniques for Logic Analyzer Debug Brock J. LaMeres Agilent Technologies Abstract Digital systems are turning out

More information

PART MAX2265 MAX2266 TOP VIEW. TDMA AT +30dBm. Maxim Integrated Products 1

PART MAX2265 MAX2266 TOP VIEW. TDMA AT +30dBm. Maxim Integrated Products 1 19-; Rev 3; 2/1 EVALUATION KIT MANUAL FOLLOWS DATA SHEET 2.7V, Single-Supply, Cellular-Band General Description The // power amplifiers are designed for operation in IS-9-based CDMA, IS-136- based TDMA,

More information

Module 1. Power Semiconductor Devices. Version 2 EE IIT, Kharagpur 1

Module 1. Power Semiconductor Devices. Version 2 EE IIT, Kharagpur 1 Module 1 Power Semiconductor Devices Version EE IIT, Kharagpur 1 Lesson 8 Hard and Soft Switching of Power Semiconductors Version EE IIT, Kharagpur This lesson provides the reader the following (i) (ii)

More information

Dual-Rate Fibre Channel Repeaters

Dual-Rate Fibre Channel Repeaters 9-292; Rev ; 7/04 Dual-Rate Fibre Channel Repeaters General Description The are dual-rate (.0625Gbps and 2.25Gbps) fibre channel repeaters. They are optimized for use in fibre channel arbitrated loop applications

More information

Power Supply Networks: Analysis and Synthesis. What is Power Supply Noise?

Power Supply Networks: Analysis and Synthesis. What is Power Supply Noise? Power Supply Networs: Analysis and Synthesis What is Power Supply Noise? Problem: Degraded voltage level at the delivery point of the power/ground grid causes performance and/or functional failure Lower

More information

Research in Support of the Die / Package Interface

Research in Support of the Die / Package Interface Research in Support of the Die / Package Interface Introduction As the microelectronics industry continues to scale down CMOS in accordance with Moore s Law and the ITRS roadmap, the minimum feature size

More information

5. CMOS Gates: DC and Transient Behavior

5. CMOS Gates: DC and Transient Behavior 5. CMOS Gates: DC and Transient Behavior Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 18, 2017 ECE Department, University

More information

PI5C3253. Dual 4:1 Mux/DeMux Bus Switch

PI5C3253. Dual 4:1 Mux/DeMux Bus Switch Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON ESD Protection up to 2kV HBM Ultra Low Quiescent Power (0.2μA typical) Ideally suited

More information

MEMS Oscillators: Enabling Smaller, Lower Power IoT & Wearables

MEMS Oscillators: Enabling Smaller, Lower Power IoT & Wearables MEMS Oscillators: Enabling Smaller, Lower Power IoT & Wearables The explosive growth in Internet-connected devices, or the Internet of Things (IoT), is driven by the convergence of people, device and data

More information

Microcircuit Electrical Issues

Microcircuit Electrical Issues Microcircuit Electrical Issues Distortion The frequency at which transmitted power has dropped to 50 percent of the injected power is called the "3 db" point and is used to define the bandwidth of the

More information

Power Distribution Network Design for Stratix IV GX and Arria II GX FPGAs

Power Distribution Network Design for Stratix IV GX and Arria II GX FPGAs Power Distribution Network Design for Stratix IV GX and Arria II GX FPGAs Transceiver Portfolio Workshops 2009 Question What is Your PDN Design Methodology? Easy Complex Historical Full SPICE simulation

More information

Low Power, Area Efficient FinFET Circuit Design

Low Power, Area Efficient FinFET Circuit Design Low Power, Area Efficient FinFET Circuit Design Michael C. Wang, Princeton University Abstract FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate

More information

Rohde & Schwarz EMI/EMC debugging with modern oscilloscope. Ing. Leonardo Nanetti Rohde&Schwarz

Rohde & Schwarz EMI/EMC debugging with modern oscilloscope. Ing. Leonardo Nanetti Rohde&Schwarz Rohde & Schwarz EMI/EMC debugging with modern oscilloscope Ing. Leonardo Nanetti Rohde&Schwarz EMI debugging Agenda l The basics l l l l The idea of EMI debugging How is it done? Application example What

More information

Compensation for Simultaneous Switching Noise in VLSI Packaging Brock J. LaMeres University of Colorado September 15, 2005

Compensation for Simultaneous Switching Noise in VLSI Packaging Brock J. LaMeres University of Colorado September 15, 2005 Compensation for Simultaneous Switching Noise in VLSI Packaging Brock J. LaMeres University of Colorado 1 Problem Statement Package Interconnect Limits VLSI System Performance The three main components

More information

A 2.4 GHZ RECEIVER IN SILICON-ON-SAPPHIRE MICHAEL PETERS. B.S., Kansas State University, 2009 A REPORT

A 2.4 GHZ RECEIVER IN SILICON-ON-SAPPHIRE MICHAEL PETERS. B.S., Kansas State University, 2009 A REPORT A 2.4 GHZ RECEIVER IN SILICON-ON-SAPPHIRE by MICHAEL PETERS B.S., Kansas State University, 2009 A REPORT submitted in partial fulfillment of the requirements for the degree MASTER OF SCIENCE Department

More information

Low Cost, Dual, High Current Output Line Driver with Shutdown ADA4311-1

Low Cost, Dual, High Current Output Line Driver with Shutdown ADA4311-1 Low Cost, Dual, High Current Output Line Driver with Shutdown ADA4311-1 FEATURES High speed 3 db bandwidth: 310 MHz, G = +5, RLOAD = 50 Ω Slew rate: 1050 V/μs, RLOAD = 50 Ω Wide output swing 20.6 V p-p

More information

SAMPLE/HOLD AMPLIFIER

SAMPLE/HOLD AMPLIFIER SAMPLE/HOLD AMPLIFIER FEATURES FAST (µs max) ACQUISITION TIME (1-bit) APERTURE JITTER: 00ps POWER DISSIPATION: 300mW COMPATIBLE WITH HIGH RESOLUTION A/D CONVERTERS ADC7, PCM75, AND ADC71 DESCRIPTION The

More information

QUICKSWITCH BASICS AND APPLICATIONS

QUICKSWITCH BASICS AND APPLICATIONS QUICKSWITCH GENERAL INFORMATION QUICKSWITCH BASICS AND APPLICATIONS INTRODUCTION The QuickSwitch family of FET switches was pioneered in 1990 to offer designers products for high-speed bus connection and

More information

An Analog Phase-Locked Loop

An Analog Phase-Locked Loop 1 An Analog Phase-Locked Loop Greg Flewelling ABSTRACT This report discusses the design, simulation, and layout of an Analog Phase-Locked Loop (APLL). The circuit consists of five major parts: A differential

More information

SURVEY AND EVALUATION OF LOW-POWER FULL-ADDER CELLS

SURVEY AND EVALUATION OF LOW-POWER FULL-ADDER CELLS SURVEY ND EVLUTION OF LOW-POWER FULL-DDER CELLS hmed Sayed and Hussain l-saad Department of Electrical & Computer Engineering University of California Davis, C, U.S.. STRCT In this paper, we survey various

More information

BCD Smart Power Roadmap Trends and Challenges. Giuseppe Croce NEREID WORKSHOP Smart Energy Bertinoro, October 20 th

BCD Smart Power Roadmap Trends and Challenges. Giuseppe Croce NEREID WORKSHOP Smart Energy Bertinoro, October 20 th BCD Smart Power Roadmap Trends and Challenges Giuseppe Croce NEREID WORKSHOP Smart Energy Bertinoro, October 20 th Outline 2 Introduction Major Trends in Smart Power ASICs An insight on (some) differentiating

More information

Digital Controller Chip Set for Isolated DC Power Supplies

Digital Controller Chip Set for Isolated DC Power Supplies Digital Controller Chip Set for Isolated DC Power Supplies Aleksandar Prodic, Dragan Maksimovic and Robert W. Erickson Colorado Power Electronics Center Department of Electrical and Computer Engineering

More information

Module -18 Flip flops

Module -18 Flip flops 1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip

More information

System Power Distribution Network Theory and Performance with Various Noise Current Stimuli Including Impacts on Chip Level Timing

System Power Distribution Network Theory and Performance with Various Noise Current Stimuli Including Impacts on Chip Level Timing System Power Distribution Network Theory and Performance with Various Noise Current Stimuli Including Impacts on Chip Level Timing Larry Smith, Shishuang Sun, Peter Boyle, Bozidar Krsnik Altera Corp. Abstract-Power

More information

Converter IC for Cellular Phone. Mode Digitally-Controlled Buck. A 4 µa-quiescent-current Dual- Applications. Jianhui Zhang Prof.

Converter IC for Cellular Phone. Mode Digitally-Controlled Buck. A 4 µa-quiescent-current Dual- Applications. Jianhui Zhang Prof. A 4 µa-quiescent-current Dual- Mode Digitally-Controlled Buck Converter IC for Cellular Phone Applications Jinwen Xiao Angel Peterchev Jianhui Zhang Prof. Seth Sanders Power Electronics Group Dept. of

More information

Low Power Design for Systems on a Chip. Tutorial Outline

Low Power Design for Systems on a Chip. Tutorial Outline Low Power Design for Systems on a Chip Mary Jane Irwin Dept of CSE Penn State University (www.cse.psu.edu/~mji) Low Power Design for SoCs ASIC Tutorial Intro.1 Tutorial Outline Introduction and motivation

More information

An Efficent Real Time Analysis of Carry Select Adder

An Efficent Real Time Analysis of Carry Select Adder An Efficent Real Time Analysis of Carry Select Adder Geetika Gesu Department of Electronics Engineering Abha Gaikwad-Patil College of Engineering Nagpur, Maharashtra, India E-mail: geetikagesu@gmail.com

More information

Timing analysis can be done right after synthesis. But it can only be accurately done when layout is available

Timing analysis can be done right after synthesis. But it can only be accurately done when layout is available Timing Analysis Lecture 9 ECE 156A-B 1 General Timing analysis can be done right after synthesis But it can only be accurately done when layout is available Timing analysis at an early stage is not accurate

More information

MEMS Ultra-Low Power Oscillator, khz Quartz XTAL Replacement

MEMS Ultra-Low Power Oscillator, khz Quartz XTAL Replacement 33Features: MEMS Technology Small SMD package: 2.0 x 1.2 mm (2012) Fixed 32.768 khz output frequency NanoDrve TM programmable output swing for lowest power Pb-free, RoHS and REACH compliant Typical Applications:

More information

The challenges of low power design Karen Yorav

The challenges of low power design Karen Yorav The challenges of low power design Karen Yorav The challenges of low power design What this tutorial is NOT about: Electrical engineering CMOS technology but also not Hand waving nonsense about trends

More information

Sensing Voltage Transients Using Built-in Voltage Sensor

Sensing Voltage Transients Using Built-in Voltage Sensor Sensing Voltage Transients Using Built-in Voltage Sensor ABSTRACT Voltage transient is a kind of voltage fluctuation caused by circuit inductance. If strong enough, voltage transients can cause system

More information

Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths

Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths Junxia Ma, Jeremy Lee and Mohammad Tehranipoor ECE Department, University of Connecticut, CT, 06269 {junxia, jslee,

More information

12-bit 140 MSPS IQ DAC

12-bit 140 MSPS IQ DAC SPECIFICATION 1 FEATURES TSMC CMOS 65 nm Resolution 12 bit Current-sinking DAC Different power supplies for digital (1.2 V) and analog parts (2.5 V) Sampling rate up to 140 MSPS Optional internal differential

More information

Voltage Transient Detection and Induction for Debug and Test

Voltage Transient Detection and Induction for Debug and Test Voltage Transient Detection and Induction for Debug and Test Rex Petersen, Pankaj Pant, Pablo Lopez, Aaron Barton, Jim Ignowski, Doug Josephson Intel Corporation Hudson, MA and Fort Collins, CO Abstract

More information

Power-Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

Power-Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS -Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS Jiajun Shi, Mingyu Li and Csaba Andras Moritz Department of Electrical and Computer Engineering University of Massachusetts, Amherst, MA,

More information

Lecture 16: Design for Testability. MAH, AEN EE271 Lecture 16 1

Lecture 16: Design for Testability. MAH, AEN EE271 Lecture 16 1 Lecture 16: Testing, Design for Testability MAH, AEN EE271 Lecture 16 1 Overview Reading W&E 7.1-7.3 - Testing Introduction Up to this place in the class we have spent all of time trying to figure out

More information

UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency

UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter

More information

SPT BIT, 100 MWPS TTL D/A CONVERTER

SPT BIT, 100 MWPS TTL D/A CONVERTER FEATURES 12-Bit, 100 MWPS digital-to-analog converter TTL compatibility Low power: 640 mw 1/2 LSB DNL 40 MHz multiplying bandwidth Industrial temperature range Superior performance over AD9713 Improved

More information

Reliable World Class Insights Your Silicon Valley Partner in Simulation ANSYS Sales, Consulting, Training & Support

Reliable World Class Insights Your Silicon Valley Partner in Simulation ANSYS Sales, Consulting, Training & Support www.ozeninc.com info@ozeninc.com (408) 732 4665 1210 E Arques Ave St 207 Sunnyvale, CA 94085 Reliable World Class Insights Your Silicon Valley Partner in Simulation ANSYS Sales, Consulting, Training &

More information

LSI Design Flow Development for Advanced Technology

LSI Design Flow Development for Advanced Technology LSI Design Flow Development for Advanced Technology Atsushi Tsuchiya LSIs that adopt advanced technologies, as represented by imaging LSIs, now contain 30 million or more logic gates and the scale is beginning

More information

Reduce Load Capacitance in Noise-Sensitive, High-Transient Applications, through Implementation of Active Filtering

Reduce Load Capacitance in Noise-Sensitive, High-Transient Applications, through Implementation of Active Filtering WHITE PAPER Reduce Load Capacitance in Noise-Sensitive, High-Transient Applications, through Implementation of Active Filtering Written by: Chester Firek, Product Marketing Manager and Bob Kent, Applications

More information